1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2// 3// This file is provided under a dual BSD/GPLv2 license. When using or 4// redistributing this file, you may do so under either license. 5// 6// Copyright(c) 2018 Intel Corporation. All rights reserved. 7// 8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10// Rander Wang <rander.wang@intel.com> 11// Keyon Jie <yang.jie@linux.intel.com> 12// 13 14/* 15 * Hardware interface for audio DSP on Cannonlake. 16 */ 17 18#include "../ops.h" 19#include "hda.h" 20#include "hda-ipc.h" 21#include "../sof-audio.h" 22 23static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = { 24 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 25 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 26 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 27}; 28 29static void cnl_ipc_host_done(struct snd_sof_dev *sdev); 30static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev); 31 32irqreturn_t cnl_ipc_irq_thread(int irq, void *context) 33{ 34 struct snd_sof_dev *sdev = context; 35 u32 hipci; 36 u32 hipcida; 37 u32 hipctdr; 38 u32 hipctdd; 39 u32 msg; 40 u32 msg_ext; 41 bool ipc_irq = false; 42 43 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); 44 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); 45 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD); 46 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR); 47 48 /* reply message from DSP */ 49 if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) { 50 msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK; 51 msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK; 52 53 dev_vdbg(sdev->dev, 54 "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n", 55 msg, msg_ext); 56 57 /* mask Done interrupt */ 58 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 59 CNL_DSP_REG_HIPCCTL, 60 CNL_DSP_REG_HIPCCTL_DONE, 0); 61 62 spin_lock_irq(&sdev->ipc_lock); 63 64 /* handle immediate reply from DSP core */ 65 hda_dsp_ipc_get_reply(sdev); 66 snd_sof_ipc_reply(sdev, msg); 67 68 cnl_ipc_dsp_done(sdev); 69 70 spin_unlock_irq(&sdev->ipc_lock); 71 72 ipc_irq = true; 73 } 74 75 /* new message from DSP */ 76 if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) { 77 msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK; 78 msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK; 79 80 dev_vdbg(sdev->dev, 81 "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n", 82 msg, msg_ext); 83 84 /* handle messages from DSP */ 85 if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) == 86 SOF_IPC_PANIC_MAGIC) { 87 snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext)); 88 } else { 89 snd_sof_ipc_msgs_rx(sdev); 90 } 91 92 cnl_ipc_host_done(sdev); 93 94 ipc_irq = true; 95 } 96 97 if (!ipc_irq) { 98 /* 99 * This interrupt is not shared so no need to return IRQ_NONE. 100 */ 101 dev_dbg_ratelimited(sdev->dev, 102 "nothing to do in IPC IRQ thread\n"); 103 } 104 105 return IRQ_HANDLED; 106} 107 108static void cnl_ipc_host_done(struct snd_sof_dev *sdev) 109{ 110 /* 111 * clear busy interrupt to tell dsp controller this 112 * interrupt has been accepted, not trigger it again 113 */ 114 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 115 CNL_DSP_REG_HIPCTDR, 116 CNL_DSP_REG_HIPCTDR_BUSY, 117 CNL_DSP_REG_HIPCTDR_BUSY); 118 /* 119 * set done bit to ack dsp the msg has been 120 * processed and send reply msg to dsp 121 */ 122 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 123 CNL_DSP_REG_HIPCTDA, 124 CNL_DSP_REG_HIPCTDA_DONE, 125 CNL_DSP_REG_HIPCTDA_DONE); 126} 127 128static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev) 129{ 130 /* 131 * set DONE bit - tell DSP we have received the reply msg 132 * from DSP, and processed it, don't send more reply to host 133 */ 134 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 135 CNL_DSP_REG_HIPCIDA, 136 CNL_DSP_REG_HIPCIDA_DONE, 137 CNL_DSP_REG_HIPCIDA_DONE); 138 139 /* unmask Done interrupt */ 140 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 141 CNL_DSP_REG_HIPCCTL, 142 CNL_DSP_REG_HIPCCTL_DONE, 143 CNL_DSP_REG_HIPCCTL_DONE); 144} 145 146static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg, 147 u32 *dr, u32 *dd) 148{ 149 struct sof_ipc_pm_gate *pm_gate; 150 151 if (msg->header == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) { 152 pm_gate = msg->msg_data; 153 154 /* send the compact message via the primary register */ 155 *dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE; 156 157 /* send payload via the extended data register */ 158 *dd = pm_gate->flags; 159 160 return true; 161 } 162 163 return false; 164} 165 166int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 167{ 168 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 169 struct sof_ipc_cmd_hdr *hdr; 170 u32 dr = 0; 171 u32 dd = 0; 172 173 /* 174 * Currently the only compact IPC supported is the PM_GATE 175 * IPC which is used for transitioning the DSP between the 176 * D0I0 and D0I3 states. And these are sent only during the 177 * set_power_state() op. Therefore, there will never be a case 178 * that a compact IPC results in the DSP exiting D0I3 without 179 * the host and FW being in sync. 180 */ 181 if (cnl_compact_ipc_compress(msg, &dr, &dd)) { 182 /* send the message via IPC registers */ 183 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD, 184 dd); 185 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR, 186 CNL_DSP_REG_HIPCIDR_BUSY | dr); 187 return 0; 188 } 189 190 /* send the message via mailbox */ 191 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 192 msg->msg_size); 193 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR, 194 CNL_DSP_REG_HIPCIDR_BUSY); 195 196 hdr = msg->msg_data; 197 198 /* 199 * Use mod_delayed_work() to schedule the delayed work 200 * to avoid scheduling multiple workqueue items when 201 * IPCs are sent at a high-rate. mod_delayed_work() 202 * modifies the timer if the work is pending. 203 * Also, a new delayed work should not be queued after the 204 * CTX_SAVE IPC, which is sent before the DSP enters D3. 205 */ 206 if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE)) 207 mod_delayed_work(system_wq, &hdev->d0i3_work, 208 msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS)); 209 210 return 0; 211} 212 213void cnl_ipc_dump(struct snd_sof_dev *sdev) 214{ 215 u32 hipcctl; 216 u32 hipcida; 217 u32 hipctdr; 218 219 hda_ipc_irq_dump(sdev); 220 221 /* read IPC status */ 222 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); 223 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL); 224 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); 225 226 /* dump the IPC regs */ 227 /* TODO: parse the raw msg */ 228 dev_err(sdev->dev, 229 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 230 hipcida, hipctdr, hipcctl); 231} 232 233/* cannonlake ops */ 234const struct snd_sof_dsp_ops sof_cnl_ops = { 235 /* probe and remove */ 236 .probe = hda_dsp_probe, 237 .remove = hda_dsp_remove, 238 239 /* Register IO */ 240 .write = sof_io_write, 241 .read = sof_io_read, 242 .write64 = sof_io_write64, 243 .read64 = sof_io_read64, 244 245 /* Block IO */ 246 .block_read = sof_block_read, 247 .block_write = sof_block_write, 248 249 /* doorbell */ 250 .irq_thread = cnl_ipc_irq_thread, 251 252 /* ipc */ 253 .send_msg = cnl_ipc_send_msg, 254 .fw_ready = sof_fw_ready, 255 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 256 .get_window_offset = hda_dsp_ipc_get_window_offset, 257 258 .ipc_msg_data = hda_ipc_msg_data, 259 .ipc_pcm_params = hda_ipc_pcm_params, 260 261 /* machine driver */ 262 .machine_select = hda_machine_select, 263 .machine_register = sof_machine_register, 264 .machine_unregister = sof_machine_unregister, 265 .set_mach_params = hda_set_mach_params, 266 267 /* debug */ 268 .debug_map = cnl_dsp_debugfs, 269 .debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs), 270 .dbg_dump = hda_dsp_dump, 271 .ipc_dump = cnl_ipc_dump, 272 273 /* stream callbacks */ 274 .pcm_open = hda_dsp_pcm_open, 275 .pcm_close = hda_dsp_pcm_close, 276 .pcm_hw_params = hda_dsp_pcm_hw_params, 277 .pcm_hw_free = hda_dsp_stream_hw_free, 278 .pcm_trigger = hda_dsp_pcm_trigger, 279 .pcm_pointer = hda_dsp_pcm_pointer, 280 281#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 282 /* probe callbacks */ 283 .probe_assign = hda_probe_compr_assign, 284 .probe_free = hda_probe_compr_free, 285 .probe_set_params = hda_probe_compr_set_params, 286 .probe_trigger = hda_probe_compr_trigger, 287 .probe_pointer = hda_probe_compr_pointer, 288#endif 289 290 /* firmware loading */ 291 .load_firmware = snd_sof_load_firmware_raw, 292 293 /* pre/post fw run */ 294 .pre_fw_run = hda_dsp_pre_fw_run, 295 .post_fw_run = hda_dsp_post_fw_run, 296 297 /* dsp core power up/down */ 298 .core_power_up = hda_dsp_enable_core, 299 .core_power_down = hda_dsp_core_reset_power_down, 300 301 /* firmware run */ 302 .run = hda_dsp_cl_boot_firmware, 303 304 /* trace callback */ 305 .trace_init = hda_dsp_trace_init, 306 .trace_release = hda_dsp_trace_release, 307 .trace_trigger = hda_dsp_trace_trigger, 308 309 /* DAI drivers */ 310 .drv = skl_dai, 311 .num_drv = SOF_SKL_NUM_DAIS, 312 313 /* PM */ 314 .suspend = hda_dsp_suspend, 315 .resume = hda_dsp_resume, 316 .runtime_suspend = hda_dsp_runtime_suspend, 317 .runtime_resume = hda_dsp_runtime_resume, 318 .runtime_idle = hda_dsp_runtime_idle, 319 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 320 .set_power_state = hda_dsp_set_power_state, 321 322 /* ALSA HW info flags */ 323 .hw_info = SNDRV_PCM_INFO_MMAP | 324 SNDRV_PCM_INFO_MMAP_VALID | 325 SNDRV_PCM_INFO_INTERLEAVED | 326 SNDRV_PCM_INFO_PAUSE | 327 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 328 329 .arch_ops = &sof_xtensa_arch_ops, 330}; 331EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 332 333const struct sof_intel_dsp_desc cnl_chip_info = { 334 /* Cannonlake */ 335 .cores_num = 4, 336 .init_core_mask = 1, 337 .host_managed_cores_mask = GENMASK(3, 0), 338 .ipc_req = CNL_DSP_REG_HIPCIDR, 339 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 340 .ipc_ack = CNL_DSP_REG_HIPCIDA, 341 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 342 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 343 .rom_init_timeout = 300, 344 .ssp_count = CNL_SSP_COUNT, 345 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 346}; 347EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 348 349const struct sof_intel_dsp_desc icl_chip_info = { 350 /* Icelake */ 351 .cores_num = 4, 352 .init_core_mask = 1, 353 .host_managed_cores_mask = GENMASK(3, 0), 354 .ipc_req = CNL_DSP_REG_HIPCIDR, 355 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 356 .ipc_ack = CNL_DSP_REG_HIPCIDA, 357 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 358 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 359 .rom_init_timeout = 300, 360 .ssp_count = ICL_SSP_COUNT, 361 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 362}; 363EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 364 365const struct sof_intel_dsp_desc ehl_chip_info = { 366 /* Elkhartlake */ 367 .cores_num = 4, 368 .init_core_mask = 1, 369 .host_managed_cores_mask = BIT(0), 370 .ipc_req = CNL_DSP_REG_HIPCIDR, 371 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 372 .ipc_ack = CNL_DSP_REG_HIPCIDA, 373 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 374 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 375 .rom_init_timeout = 300, 376 .ssp_count = ICL_SSP_COUNT, 377 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 378}; 379EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 380 381const struct sof_intel_dsp_desc jsl_chip_info = { 382 /* Jasperlake */ 383 .cores_num = 2, 384 .init_core_mask = 1, 385 .host_managed_cores_mask = GENMASK(1, 0), 386 .ipc_req = CNL_DSP_REG_HIPCIDR, 387 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 388 .ipc_ack = CNL_DSP_REG_HIPCIDA, 389 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 390 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 391 .rom_init_timeout = 300, 392 .ssp_count = ICL_SSP_COUNT, 393 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 394}; 395EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 396