1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2// 3// This file is provided under a dual BSD/GPLv2 license. When using or 4// redistributing this file, you may do so under either license. 5// 6// Copyright(c) 2018 Intel Corporation. All rights reserved. 7// 8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10// Rander Wang <rander.wang@intel.com> 11// Keyon Jie <yang.jie@linux.intel.com> 12// 13 14/* 15 * Hardware interface for audio DSP on Apollolake and GeminiLake 16 */ 17 18#include "../sof-priv.h" 19#include "hda.h" 20#include "../sof-audio.h" 21 22static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = { 23 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 24 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 25 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 26}; 27 28/* apollolake ops */ 29const struct snd_sof_dsp_ops sof_apl_ops = { 30 /* probe and remove */ 31 .probe = hda_dsp_probe, 32 .remove = hda_dsp_remove, 33 34 /* Register IO */ 35 .write = sof_io_write, 36 .read = sof_io_read, 37 .write64 = sof_io_write64, 38 .read64 = sof_io_read64, 39 40 /* Block IO */ 41 .block_read = sof_block_read, 42 .block_write = sof_block_write, 43 44 /* doorbell */ 45 .irq_thread = hda_dsp_ipc_irq_thread, 46 47 /* ipc */ 48 .send_msg = hda_dsp_ipc_send_msg, 49 .fw_ready = sof_fw_ready, 50 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 51 .get_window_offset = hda_dsp_ipc_get_window_offset, 52 53 .ipc_msg_data = hda_ipc_msg_data, 54 .ipc_pcm_params = hda_ipc_pcm_params, 55 56 /* machine driver */ 57 .machine_select = hda_machine_select, 58 .machine_register = sof_machine_register, 59 .machine_unregister = sof_machine_unregister, 60 .set_mach_params = hda_set_mach_params, 61 62 /* debug */ 63 .debug_map = apl_dsp_debugfs, 64 .debug_map_count = ARRAY_SIZE(apl_dsp_debugfs), 65 .dbg_dump = hda_dsp_dump, 66 .ipc_dump = hda_ipc_dump, 67 68 /* stream callbacks */ 69 .pcm_open = hda_dsp_pcm_open, 70 .pcm_close = hda_dsp_pcm_close, 71 .pcm_hw_params = hda_dsp_pcm_hw_params, 72 .pcm_hw_free = hda_dsp_stream_hw_free, 73 .pcm_trigger = hda_dsp_pcm_trigger, 74 .pcm_pointer = hda_dsp_pcm_pointer, 75 76#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 77 /* probe callbacks */ 78 .probe_assign = hda_probe_compr_assign, 79 .probe_free = hda_probe_compr_free, 80 .probe_set_params = hda_probe_compr_set_params, 81 .probe_trigger = hda_probe_compr_trigger, 82 .probe_pointer = hda_probe_compr_pointer, 83#endif 84 85 /* firmware loading */ 86 .load_firmware = snd_sof_load_firmware_raw, 87 88 /* firmware run */ 89 .run = hda_dsp_cl_boot_firmware, 90 91 /* pre/post fw run */ 92 .pre_fw_run = hda_dsp_pre_fw_run, 93 .post_fw_run = hda_dsp_post_fw_run, 94 95 /* dsp core power up/down */ 96 .core_power_up = hda_dsp_enable_core, 97 .core_power_down = hda_dsp_core_reset_power_down, 98 99 /* trace callback */ 100 .trace_init = hda_dsp_trace_init, 101 .trace_release = hda_dsp_trace_release, 102 .trace_trigger = hda_dsp_trace_trigger, 103 104 /* DAI drivers */ 105 .drv = skl_dai, 106 .num_drv = SOF_SKL_NUM_DAIS, 107 108 /* PM */ 109 .suspend = hda_dsp_suspend, 110 .resume = hda_dsp_resume, 111 .runtime_suspend = hda_dsp_runtime_suspend, 112 .runtime_resume = hda_dsp_runtime_resume, 113 .runtime_idle = hda_dsp_runtime_idle, 114 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 115 .set_power_state = hda_dsp_set_power_state, 116 117 /* ALSA HW info flags */ 118 .hw_info = SNDRV_PCM_INFO_MMAP | 119 SNDRV_PCM_INFO_MMAP_VALID | 120 SNDRV_PCM_INFO_INTERLEAVED | 121 SNDRV_PCM_INFO_PAUSE | 122 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 123 124 .arch_ops = &sof_xtensa_arch_ops, 125}; 126EXPORT_SYMBOL_NS(sof_apl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 127 128const struct sof_intel_dsp_desc apl_chip_info = { 129 /* Apollolake */ 130 .cores_num = 2, 131 .init_core_mask = 1, 132 .host_managed_cores_mask = GENMASK(1, 0), 133 .ipc_req = HDA_DSP_REG_HIPCI, 134 .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY, 135 .ipc_ack = HDA_DSP_REG_HIPCIE, 136 .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE, 137 .ipc_ctl = HDA_DSP_REG_HIPCCTL, 138 .rom_init_timeout = 150, 139 .ssp_count = APL_SSP_COUNT, 140 .ssp_base_offset = APL_SSP_BASE_OFFSET, 141}; 142EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 143