xref: /kernel/linux/linux-5.10/sound/soc/sh/rcar/adg.c (revision 8c2ecf20) 
1// SPDX-License-Identifier: GPL-2.0
2//
3// Helper routines for R-Car sound ADG.
4//
5//  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6
7#include <linux/clk-provider.h>
8#include "rsnd.h"
9
10#define CLKA	0
11#define CLKB	1
12#define CLKC	2
13#define CLKI	3
14#define CLKMAX	4
15
16#define CLKOUT	0
17#define CLKOUT1	1
18#define CLKOUT2	2
19#define CLKOUT3	3
20#define CLKOUTMAX 4
21
22#define BRRx_MASK(x) (0x3FF & x)
23
24static struct rsnd_mod_ops adg_ops = {
25	.name = "adg",
26};
27
28struct rsnd_adg {
29	struct clk *clk[CLKMAX];
30	struct clk *clkout[CLKOUTMAX];
31	struct clk_onecell_data onecell;
32	struct rsnd_mod mod;
33	int clk_rate[CLKMAX];
34	u32 flags;
35	u32 ckr;
36	u32 rbga;
37	u32 rbgb;
38
39	int rbga_rate_for_441khz; /* RBGA */
40	int rbgb_rate_for_48khz;  /* RBGB */
41};
42
43#define LRCLK_ASYNC	(1 << 0)
44#define AUDIO_OUT_48	(1 << 1)
45
46#define for_each_rsnd_clk(pos, adg, i)		\
47	for (i = 0;				\
48	     (i < CLKMAX) &&			\
49	     ((pos) = adg->clk[i]);		\
50	     i++)
51#define for_each_rsnd_clkout(pos, adg, i)	\
52	for (i = 0;				\
53	     (i < CLKOUTMAX) &&			\
54	     ((pos) = adg->clkout[i]);	\
55	     i++)
56#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
57
58static const char * const clk_name[] = {
59	[CLKA]	= "clk_a",
60	[CLKB]	= "clk_b",
61	[CLKC]	= "clk_c",
62	[CLKI]	= "clk_i",
63};
64
65static u32 rsnd_adg_calculate_rbgx(unsigned long div)
66{
67	int i, ratio;
68
69	if (!div)
70		return 0;
71
72	for (i = 3; i >= 0; i--) {
73		ratio = 2 << (i * 2);
74		if (0 == (div % ratio))
75			return (u32)((i << 8) | ((div / ratio) - 1));
76	}
77
78	return ~0;
79}
80
81static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
82{
83	struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
84	int id = rsnd_mod_id(ssi_mod);
85	int ws = id;
86
87	if (rsnd_ssi_is_pin_sharing(io)) {
88		switch (id) {
89		case 1:
90		case 2:
91		case 9:
92			ws = 0;
93			break;
94		case 4:
95			ws = 3;
96			break;
97		case 8:
98			ws = 7;
99			break;
100		}
101	}
102
103	return (0x6 + ws) << 8;
104}
105
106static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
107				       struct rsnd_dai_stream *io,
108				       unsigned int target_rate,
109				       unsigned int *target_val,
110				       unsigned int *target_en)
111{
112	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
113	struct device *dev = rsnd_priv_to_dev(priv);
114	int idx, sel, div, step;
115	unsigned int val, en;
116	unsigned int min, diff;
117	unsigned int sel_rate[] = {
118		adg->clk_rate[CLKA],	/* 0000: CLKA */
119		adg->clk_rate[CLKB],	/* 0001: CLKB */
120		adg->clk_rate[CLKC],	/* 0010: CLKC */
121		adg->rbga_rate_for_441khz,	/* 0011: RBGA */
122		adg->rbgb_rate_for_48khz,	/* 0100: RBGB */
123	};
124
125	min = ~0;
126	val = 0;
127	en = 0;
128	for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
129		idx = 0;
130		step = 2;
131
132		if (!sel_rate[sel])
133			continue;
134
135		for (div = 2; div <= 98304; div += step) {
136			diff = abs(target_rate - sel_rate[sel] / div);
137			if (min > diff) {
138				val = (sel << 8) | idx;
139				min = diff;
140				en = 1 << (sel + 1); /* fixme */
141			}
142
143			/*
144			 * step of 0_0000 / 0_0001 / 0_1101
145			 * are out of order
146			 */
147			if ((idx > 2) && (idx % 2))
148				step *= 2;
149			if (idx == 0x1c) {
150				div += step;
151				step *= 2;
152			}
153			idx++;
154		}
155	}
156
157	if (min == ~0) {
158		dev_err(dev, "no Input clock\n");
159		return;
160	}
161
162	*target_val = val;
163	if (target_en)
164		*target_en = en;
165}
166
167static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
168				       struct rsnd_dai_stream *io,
169				       unsigned int in_rate,
170				       unsigned int out_rate,
171				       u32 *in, u32 *out, u32 *en)
172{
173	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
174	unsigned int target_rate;
175	u32 *target_val;
176	u32 _in;
177	u32 _out;
178	u32 _en;
179
180	/* default = SSI WS */
181	_in =
182	_out = rsnd_adg_ssi_ws_timing_gen2(io);
183
184	target_rate = 0;
185	target_val = NULL;
186	_en = 0;
187	if (runtime->rate != in_rate) {
188		target_rate = out_rate;
189		target_val  = &_out;
190	} else if (runtime->rate != out_rate) {
191		target_rate = in_rate;
192		target_val  = &_in;
193	}
194
195	if (target_rate)
196		__rsnd_adg_get_timesel_ratio(priv, io,
197					     target_rate,
198					     target_val, &_en);
199
200	if (in)
201		*in = _in;
202	if (out)
203		*out = _out;
204	if (en)
205		*en = _en;
206}
207
208int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
209				 struct rsnd_dai_stream *io)
210{
211	struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
212	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
213	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
214	int id = rsnd_mod_id(cmd_mod);
215	int shift = (id % 2) ? 16 : 0;
216	u32 mask, val;
217
218	rsnd_adg_get_timesel_ratio(priv, io,
219				   rsnd_src_get_in_rate(priv, io),
220				   rsnd_src_get_out_rate(priv, io),
221				   NULL, &val, NULL);
222
223	val  = val	<< shift;
224	mask = 0x0f1f	<< shift;
225
226	rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
227
228	return 0;
229}
230
231int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
232				  struct rsnd_dai_stream *io,
233				  unsigned int in_rate,
234				  unsigned int out_rate)
235{
236	struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
237	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
238	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
239	u32 in, out;
240	u32 mask, en;
241	int id = rsnd_mod_id(src_mod);
242	int shift = (id % 2) ? 16 : 0;
243
244	rsnd_mod_confirm_src(src_mod);
245
246	rsnd_adg_get_timesel_ratio(priv, io,
247				   in_rate, out_rate,
248				   &in, &out, &en);
249
250	in   = in	<< shift;
251	out  = out	<< shift;
252	mask = 0x0f1f	<< shift;
253
254	rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2),  mask, in);
255	rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
256
257	if (en)
258		rsnd_mod_bset(adg_mod, DIV_EN, en, en);
259
260	return 0;
261}
262
263static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
264{
265	struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
266	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
267	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
268	struct device *dev = rsnd_priv_to_dev(priv);
269	int id = rsnd_mod_id(ssi_mod);
270	int shift = (id % 4) * 8;
271	u32 mask = 0xFF << shift;
272
273	rsnd_mod_confirm_ssi(ssi_mod);
274
275	val = val << shift;
276
277	/*
278	 * SSI 8 is not connected to ADG.
279	 * it works with SSI 7
280	 */
281	if (id == 8)
282		return;
283
284	rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
285
286	dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
287}
288
289int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
290{
291	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
292	int i;
293	int sel_table[] = {
294		[CLKA] = 0x1,
295		[CLKB] = 0x2,
296		[CLKC] = 0x3,
297		[CLKI] = 0x0,
298	};
299
300	/*
301	 * find suitable clock from
302	 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
303	 */
304	for (i = 0; i < CLKMAX; i++)
305		if (rate == adg->clk_rate[i])
306			return sel_table[i];
307
308	/*
309	 * find divided clock from BRGA/BRGB
310	 */
311	if (rate == adg->rbga_rate_for_441khz)
312		return 0x10;
313
314	if (rate == adg->rbgb_rate_for_48khz)
315		return 0x20;
316
317	return -EIO;
318}
319
320int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
321{
322	rsnd_adg_set_ssi_clk(ssi_mod, 0);
323
324	return 0;
325}
326
327int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
328{
329	struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
330	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
331	struct device *dev = rsnd_priv_to_dev(priv);
332	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
333	int data;
334	u32 ckr = 0;
335
336	data = rsnd_adg_clk_query(priv, rate);
337	if (data < 0)
338		return data;
339
340	rsnd_adg_set_ssi_clk(ssi_mod, data);
341
342	if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
343		if (rsnd_flags_has(adg, AUDIO_OUT_48))
344			ckr = 0x80000000;
345	} else {
346		if (0 == (rate % 8000))
347			ckr = 0x80000000;
348	}
349
350	rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
351	rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
352	rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
353
354	dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
355		(ckr) ? 'B' : 'A',
356		(ckr) ?	adg->rbgb_rate_for_48khz :
357			adg->rbga_rate_for_441khz);
358
359	return 0;
360}
361
362void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
363{
364	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
365	struct device *dev = rsnd_priv_to_dev(priv);
366	struct clk *clk;
367	int i, ret;
368
369	for_each_rsnd_clk(clk, adg, i) {
370		ret = 0;
371		if (enable) {
372			ret = clk_prepare_enable(clk);
373
374			/*
375			 * We shouldn't use clk_get_rate() under
376			 * atomic context. Let's keep it when
377			 * rsnd_adg_clk_enable() was called
378			 */
379			adg->clk_rate[i] = clk_get_rate(adg->clk[i]);
380		} else {
381			clk_disable_unprepare(clk);
382		}
383
384		if (ret < 0)
385			dev_warn(dev, "can't use clk %d\n", i);
386	}
387}
388
389static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
390			       struct rsnd_adg *adg)
391{
392	struct device *dev = rsnd_priv_to_dev(priv);
393	struct clk *clk;
394	int i;
395
396	for (i = 0; i < CLKMAX; i++) {
397		clk = devm_clk_get(dev, clk_name[i]);
398		adg->clk[i] = IS_ERR(clk) ? NULL : clk;
399	}
400}
401
402static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
403				struct rsnd_adg *adg)
404{
405	struct clk *clk;
406	struct device *dev = rsnd_priv_to_dev(priv);
407	struct device_node *np = dev->of_node;
408	struct property *prop;
409	u32 ckr, rbgx, rbga, rbgb;
410	u32 rate, div;
411#define REQ_SIZE 2
412	u32 req_rate[REQ_SIZE] = {};
413	uint32_t count = 0;
414	unsigned long req_48kHz_rate, req_441kHz_rate;
415	int i, req_size;
416	const char *parent_clk_name = NULL;
417	static const char * const clkout_name[] = {
418		[CLKOUT]  = "audio_clkout",
419		[CLKOUT1] = "audio_clkout1",
420		[CLKOUT2] = "audio_clkout2",
421		[CLKOUT3] = "audio_clkout3",
422	};
423	int brg_table[] = {
424		[CLKA] = 0x0,
425		[CLKB] = 0x1,
426		[CLKC] = 0x4,
427		[CLKI] = 0x2,
428	};
429
430	ckr = 0;
431	rbga = 2; /* default 1/6 */
432	rbgb = 2; /* default 1/6 */
433
434	/*
435	 * ADG supports BRRA/BRRB output only
436	 * this means all clkout0/1/2/3 will be same rate
437	 */
438	prop = of_find_property(np, "clock-frequency", NULL);
439	if (!prop)
440		goto rsnd_adg_get_clkout_end;
441
442	req_size = prop->length / sizeof(u32);
443	if (req_size > REQ_SIZE) {
444		dev_err(dev,
445			"too many clock-frequency, use top %d\n", REQ_SIZE);
446		req_size = REQ_SIZE;
447	}
448
449	of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
450	req_48kHz_rate = 0;
451	req_441kHz_rate = 0;
452	for (i = 0; i < req_size; i++) {
453		if (0 == (req_rate[i] % 44100))
454			req_441kHz_rate = req_rate[i];
455		if (0 == (req_rate[i] % 48000))
456			req_48kHz_rate = req_rate[i];
457	}
458
459	if (req_rate[0] % 48000 == 0)
460		rsnd_flags_set(adg, AUDIO_OUT_48);
461
462	if (of_get_property(np, "clkout-lr-asynchronous", NULL))
463		rsnd_flags_set(adg, LRCLK_ASYNC);
464
465	/*
466	 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
467	 * have 44.1kHz or 48kHz base clocks for now.
468	 *
469	 * SSI itself can divide parent clock by 1/1 - 1/16
470	 * see
471	 *	rsnd_adg_ssi_clk_try_start()
472	 *	rsnd_ssi_master_clk_start()
473	 */
474	adg->rbga_rate_for_441khz	= 0;
475	adg->rbgb_rate_for_48khz	= 0;
476	for_each_rsnd_clk(clk, adg, i) {
477		rate = clk_get_rate(clk);
478
479		if (0 == rate) /* not used */
480			continue;
481
482		/* RBGA */
483		if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
484			div = 6;
485			if (req_441kHz_rate)
486				div = rate / req_441kHz_rate;
487			rbgx = rsnd_adg_calculate_rbgx(div);
488			if (BRRx_MASK(rbgx) == rbgx) {
489				rbga = rbgx;
490				adg->rbga_rate_for_441khz = rate / div;
491				ckr |= brg_table[i] << 20;
492				if (req_441kHz_rate &&
493				    !rsnd_flags_has(adg, AUDIO_OUT_48))
494					parent_clk_name = __clk_get_name(clk);
495			}
496		}
497
498		/* RBGB */
499		if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
500			div = 6;
501			if (req_48kHz_rate)
502				div = rate / req_48kHz_rate;
503			rbgx = rsnd_adg_calculate_rbgx(div);
504			if (BRRx_MASK(rbgx) == rbgx) {
505				rbgb = rbgx;
506				adg->rbgb_rate_for_48khz = rate / div;
507				ckr |= brg_table[i] << 16;
508				if (req_48kHz_rate &&
509				    rsnd_flags_has(adg, AUDIO_OUT_48))
510					parent_clk_name = __clk_get_name(clk);
511			}
512		}
513	}
514
515	/*
516	 * ADG supports BRRA/BRRB output only.
517	 * this means all clkout0/1/2/3 will be * same rate
518	 */
519
520	of_property_read_u32(np, "#clock-cells", &count);
521	/*
522	 * for clkout
523	 */
524	if (!count) {
525		clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
526					      parent_clk_name, 0, req_rate[0]);
527		if (!IS_ERR(clk)) {
528			adg->clkout[CLKOUT] = clk;
529			of_clk_add_provider(np, of_clk_src_simple_get, clk);
530		}
531	}
532	/*
533	 * for clkout0/1/2/3
534	 */
535	else {
536		for (i = 0; i < CLKOUTMAX; i++) {
537			clk = clk_register_fixed_rate(dev, clkout_name[i],
538						      parent_clk_name, 0,
539						      req_rate[0]);
540			if (!IS_ERR(clk))
541				adg->clkout[i] = clk;
542		}
543		adg->onecell.clks	= adg->clkout;
544		adg->onecell.clk_num	= CLKOUTMAX;
545		of_clk_add_provider(np, of_clk_src_onecell_get,
546				    &adg->onecell);
547	}
548
549rsnd_adg_get_clkout_end:
550	adg->ckr = ckr;
551	adg->rbga = rbga;
552	adg->rbgb = rbgb;
553}
554
555#ifdef DEBUG
556static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg)
557{
558	struct device *dev = rsnd_priv_to_dev(priv);
559	struct clk *clk;
560	int i;
561
562	for_each_rsnd_clk(clk, adg, i)
563		dev_dbg(dev, "%s    : %pa : %ld\n",
564			clk_name[i], clk, clk_get_rate(clk));
565
566	dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
567		adg->ckr, adg->rbga, adg->rbgb);
568	dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
569	dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
570
571	/*
572	 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
573	 * by BRGCKR::BRGCKR_31
574	 */
575	for_each_rsnd_clkout(clk, adg, i)
576		dev_dbg(dev, "clkout %d : %pa : %ld\n", i,
577			clk, clk_get_rate(clk));
578}
579#else
580#define rsnd_adg_clk_dbg_info(priv, adg)
581#endif
582
583int rsnd_adg_probe(struct rsnd_priv *priv)
584{
585	struct rsnd_adg *adg;
586	struct device *dev = rsnd_priv_to_dev(priv);
587	int ret;
588
589	adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
590	if (!adg)
591		return -ENOMEM;
592
593	ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
594		      NULL, 0, 0);
595	if (ret)
596		return ret;
597
598	rsnd_adg_get_clkin(priv, adg);
599	rsnd_adg_get_clkout(priv, adg);
600	rsnd_adg_clk_dbg_info(priv, adg);
601
602	priv->adg = adg;
603
604	rsnd_adg_clk_enable(priv);
605
606	return 0;
607}
608
609void rsnd_adg_remove(struct rsnd_priv *priv)
610{
611	struct device *dev = rsnd_priv_to_dev(priv);
612	struct device_node *np = dev->of_node;
613	struct rsnd_adg *adg = priv->adg;
614	struct clk *clk;
615	int i;
616
617	for_each_rsnd_clkout(clk, adg, i)
618		if (adg->clkout[i])
619			clk_unregister_fixed_rate(adg->clkout[i]);
620
621	of_clk_del_provider(np);
622
623	rsnd_adg_clk_disable(priv);
624}
625