1// SPDX-License-Identifier: GPL-2.0 2// 3// Fifo-attached Serial Interface (FSI) support for SH7724 4// 5// Copyright (C) 2009 Renesas Solutions Corp. 6// Kuninori Morimoto <morimoto.kuninori@renesas.com> 7// 8// Based on ssi.c 9// Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 10 11#include <linux/delay.h> 12#include <linux/dma-mapping.h> 13#include <linux/pm_runtime.h> 14#include <linux/io.h> 15#include <linux/of.h> 16#include <linux/of_device.h> 17#include <linux/scatterlist.h> 18#include <linux/sh_dma.h> 19#include <linux/slab.h> 20#include <linux/module.h> 21#include <linux/workqueue.h> 22#include <sound/soc.h> 23#include <sound/pcm_params.h> 24#include <sound/sh_fsi.h> 25 26/* PortA/PortB register */ 27#define REG_DO_FMT 0x0000 28#define REG_DOFF_CTL 0x0004 29#define REG_DOFF_ST 0x0008 30#define REG_DI_FMT 0x000C 31#define REG_DIFF_CTL 0x0010 32#define REG_DIFF_ST 0x0014 33#define REG_CKG1 0x0018 34#define REG_CKG2 0x001C 35#define REG_DIDT 0x0020 36#define REG_DODT 0x0024 37#define REG_MUTE_ST 0x0028 38#define REG_OUT_DMAC 0x002C 39#define REG_OUT_SEL 0x0030 40#define REG_IN_DMAC 0x0038 41 42/* master register */ 43#define MST_CLK_RST 0x0210 44#define MST_SOFT_RST 0x0214 45#define MST_FIFO_SZ 0x0218 46 47/* core register (depend on FSI version) */ 48#define A_MST_CTLR 0x0180 49#define B_MST_CTLR 0x01A0 50#define CPU_INT_ST 0x01F4 51#define CPU_IEMSK 0x01F8 52#define CPU_IMSK 0x01FC 53#define INT_ST 0x0200 54#define IEMSK 0x0204 55#define IMSK 0x0208 56 57/* DO_FMT */ 58/* DI_FMT */ 59#define CR_BWS_MASK (0x3 << 20) /* FSI2 */ 60#define CR_BWS_24 (0x0 << 20) /* FSI2 */ 61#define CR_BWS_16 (0x1 << 20) /* FSI2 */ 62#define CR_BWS_20 (0x2 << 20) /* FSI2 */ 63 64#define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 65#define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 66#define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 67 68#define CR_MONO (0x0 << 4) 69#define CR_MONO_D (0x1 << 4) 70#define CR_PCM (0x2 << 4) 71#define CR_I2S (0x3 << 4) 72#define CR_TDM (0x4 << 4) 73#define CR_TDM_D (0x5 << 4) 74 75/* OUT_DMAC */ 76/* IN_DMAC */ 77#define VDMD_MASK (0x3 << 4) 78#define VDMD_FRONT (0x0 << 4) /* Package in front */ 79#define VDMD_BACK (0x1 << 4) /* Package in back */ 80#define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ 81 82#define DMA_ON (0x1 << 0) 83 84/* DOFF_CTL */ 85/* DIFF_CTL */ 86#define IRQ_HALF 0x00100000 87#define FIFO_CLR 0x00000001 88 89/* DOFF_ST */ 90#define ERR_OVER 0x00000010 91#define ERR_UNDER 0x00000001 92#define ST_ERR (ERR_OVER | ERR_UNDER) 93 94/* CKG1 */ 95#define ACKMD_MASK 0x00007000 96#define BPFMD_MASK 0x00000700 97#define DIMD (1 << 4) 98#define DOMD (1 << 0) 99 100/* A/B MST_CTLR */ 101#define BP (1 << 4) /* Fix the signal of Biphase output */ 102#define SE (1 << 0) /* Fix the master clock */ 103 104/* CLK_RST */ 105#define CRB (1 << 4) 106#define CRA (1 << 0) 107 108/* IO SHIFT / MACRO */ 109#define BI_SHIFT 12 110#define BO_SHIFT 8 111#define AI_SHIFT 4 112#define AO_SHIFT 0 113#define AB_IO(param, shift) (param << shift) 114 115/* SOFT_RST */ 116#define PBSR (1 << 12) /* Port B Software Reset */ 117#define PASR (1 << 8) /* Port A Software Reset */ 118#define IR (1 << 4) /* Interrupt Reset */ 119#define FSISR (1 << 0) /* Software Reset */ 120 121/* OUT_SEL (FSI2) */ 122#define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 123 /* 1: Biphase and serial */ 124 125/* FIFO_SZ */ 126#define FIFO_SZ_MASK 0x7 127 128#define FSI_RATES SNDRV_PCM_RATE_8000_96000 129 130#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 131 132/* 133 * bus options 134 * 135 * 0x000000BA 136 * 137 * A : sample widtht 16bit setting 138 * B : sample widtht 24bit setting 139 */ 140 141#define SHIFT_16DATA 0 142#define SHIFT_24DATA 4 143 144#define PACKAGE_24BITBUS_BACK 0 145#define PACKAGE_24BITBUS_FRONT 1 146#define PACKAGE_16BITBUS_STREAM 2 147 148#define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) 149#define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) 150 151/* 152 * FSI driver use below type name for variable 153 * 154 * xxx_num : number of data 155 * xxx_pos : position of data 156 * xxx_capa : capacity of data 157 */ 158 159/* 160 * period/frame/sample image 161 * 162 * ex) PCM (2ch) 163 * 164 * period pos period pos 165 * [n] [n + 1] 166 * |<-------------------- period--------------------->| 167 * ==|============================================ ... =|== 168 * | | 169 * ||<----- frame ----->|<------ frame ----->| ... | 170 * |+--------------------+--------------------+- ... | 171 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | 172 * |+--------------------+--------------------+- ... | 173 * ==|============================================ ... =|== 174 */ 175 176/* 177 * FSI FIFO image 178 * 179 * | | 180 * | | 181 * | [ sample ] | 182 * | [ sample ] | 183 * | [ sample ] | 184 * | [ sample ] | 185 * --> go to codecs 186 */ 187 188/* 189 * FSI clock 190 * 191 * FSIxCLK [CPG] (ick) -------> | 192 * |-> FSI_DIV (div)-> FSI2 193 * FSIxCK [external] (xck) ---> | 194 */ 195 196/* 197 * struct 198 */ 199 200struct fsi_stream_handler; 201struct fsi_stream { 202 203 /* 204 * these are initialized by fsi_stream_init() 205 */ 206 struct snd_pcm_substream *substream; 207 int fifo_sample_capa; /* sample capacity of FSI FIFO */ 208 int buff_sample_capa; /* sample capacity of ALSA buffer */ 209 int buff_sample_pos; /* sample position of ALSA buffer */ 210 int period_samples; /* sample number / 1 period */ 211 int period_pos; /* current period position */ 212 int sample_width; /* sample width */ 213 int uerr_num; 214 int oerr_num; 215 216 /* 217 * bus options 218 */ 219 u32 bus_option; 220 221 /* 222 * thse are initialized by fsi_handler_init() 223 */ 224 struct fsi_stream_handler *handler; 225 struct fsi_priv *priv; 226 227 /* 228 * these are for DMAEngine 229 */ 230 struct dma_chan *chan; 231 int dma_id; 232}; 233 234struct fsi_clk { 235 /* see [FSI clock] */ 236 struct clk *own; 237 struct clk *xck; 238 struct clk *ick; 239 struct clk *div; 240 int (*set_rate)(struct device *dev, 241 struct fsi_priv *fsi); 242 243 unsigned long rate; 244 unsigned int count; 245}; 246 247struct fsi_priv { 248 void __iomem *base; 249 phys_addr_t phys; 250 struct fsi_master *master; 251 252 struct fsi_stream playback; 253 struct fsi_stream capture; 254 255 struct fsi_clk clock; 256 257 u32 fmt; 258 259 int chan_num:16; 260 unsigned int clk_master:1; 261 unsigned int clk_cpg:1; 262 unsigned int spdif:1; 263 unsigned int enable_stream:1; 264 unsigned int bit_clk_inv:1; 265 unsigned int lr_clk_inv:1; 266}; 267 268struct fsi_stream_handler { 269 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); 270 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); 271 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); 272 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); 273 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); 274 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, 275 int enable); 276}; 277#define fsi_stream_handler_call(io, func, args...) \ 278 (!(io) ? -ENODEV : \ 279 !((io)->handler->func) ? 0 : \ 280 (io)->handler->func(args)) 281 282struct fsi_core { 283 int ver; 284 285 u32 int_st; 286 u32 iemsk; 287 u32 imsk; 288 u32 a_mclk; 289 u32 b_mclk; 290}; 291 292struct fsi_master { 293 void __iomem *base; 294 struct fsi_priv fsia; 295 struct fsi_priv fsib; 296 const struct fsi_core *core; 297 spinlock_t lock; 298}; 299 300static inline int fsi_stream_is_play(struct fsi_priv *fsi, 301 struct fsi_stream *io) 302{ 303 return &fsi->playback == io; 304} 305 306 307/* 308 * basic read write function 309 */ 310 311static void __fsi_reg_write(u32 __iomem *reg, u32 data) 312{ 313 /* valid data area is 24bit */ 314 data &= 0x00ffffff; 315 316 __raw_writel(data, reg); 317} 318 319static u32 __fsi_reg_read(u32 __iomem *reg) 320{ 321 return __raw_readl(reg); 322} 323 324static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) 325{ 326 u32 val = __fsi_reg_read(reg); 327 328 val &= ~mask; 329 val |= data & mask; 330 331 __fsi_reg_write(reg, val); 332} 333 334#define fsi_reg_write(p, r, d)\ 335 __fsi_reg_write((p->base + REG_##r), d) 336 337#define fsi_reg_read(p, r)\ 338 __fsi_reg_read((p->base + REG_##r)) 339 340#define fsi_reg_mask_set(p, r, m, d)\ 341 __fsi_reg_mask_set((p->base + REG_##r), m, d) 342 343#define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 344#define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 345static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 346{ 347 u32 ret; 348 unsigned long flags; 349 350 spin_lock_irqsave(&master->lock, flags); 351 ret = __fsi_reg_read(master->base + reg); 352 spin_unlock_irqrestore(&master->lock, flags); 353 354 return ret; 355} 356 357#define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 358#define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 359static void _fsi_master_mask_set(struct fsi_master *master, 360 u32 reg, u32 mask, u32 data) 361{ 362 unsigned long flags; 363 364 spin_lock_irqsave(&master->lock, flags); 365 __fsi_reg_mask_set(master->base + reg, mask, data); 366 spin_unlock_irqrestore(&master->lock, flags); 367} 368 369/* 370 * basic function 371 */ 372static int fsi_version(struct fsi_master *master) 373{ 374 return master->core->ver; 375} 376 377static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 378{ 379 return fsi->master; 380} 381 382static int fsi_is_clk_master(struct fsi_priv *fsi) 383{ 384 return fsi->clk_master; 385} 386 387static int fsi_is_port_a(struct fsi_priv *fsi) 388{ 389 return fsi->master->base == fsi->base; 390} 391 392static int fsi_is_spdif(struct fsi_priv *fsi) 393{ 394 return fsi->spdif; 395} 396 397static int fsi_is_enable_stream(struct fsi_priv *fsi) 398{ 399 return fsi->enable_stream; 400} 401 402static int fsi_is_play(struct snd_pcm_substream *substream) 403{ 404 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 405} 406 407static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 408{ 409 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 410 411 return asoc_rtd_to_cpu(rtd, 0); 412} 413 414static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 415{ 416 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 417 418 if (dai->id == 0) 419 return &master->fsia; 420 else 421 return &master->fsib; 422} 423 424static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 425{ 426 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 427} 428 429static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) 430{ 431 int is_play = fsi_stream_is_play(fsi, io); 432 int is_porta = fsi_is_port_a(fsi); 433 u32 shift; 434 435 if (is_porta) 436 shift = is_play ? AO_SHIFT : AI_SHIFT; 437 else 438 shift = is_play ? BO_SHIFT : BI_SHIFT; 439 440 return shift; 441} 442 443static int fsi_frame2sample(struct fsi_priv *fsi, int frames) 444{ 445 return frames * fsi->chan_num; 446} 447 448static int fsi_sample2frame(struct fsi_priv *fsi, int samples) 449{ 450 return samples / fsi->chan_num; 451} 452 453static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, 454 struct fsi_stream *io) 455{ 456 int is_play = fsi_stream_is_play(fsi, io); 457 u32 status; 458 int frames; 459 460 status = is_play ? 461 fsi_reg_read(fsi, DOFF_ST) : 462 fsi_reg_read(fsi, DIFF_ST); 463 464 frames = 0x1ff & (status >> 8); 465 466 return fsi_frame2sample(fsi, frames); 467} 468 469static void fsi_count_fifo_err(struct fsi_priv *fsi) 470{ 471 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 472 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 473 474 if (ostatus & ERR_OVER) 475 fsi->playback.oerr_num++; 476 477 if (ostatus & ERR_UNDER) 478 fsi->playback.uerr_num++; 479 480 if (istatus & ERR_OVER) 481 fsi->capture.oerr_num++; 482 483 if (istatus & ERR_UNDER) 484 fsi->capture.uerr_num++; 485 486 fsi_reg_write(fsi, DOFF_ST, 0); 487 fsi_reg_write(fsi, DIFF_ST, 0); 488} 489 490/* 491 * fsi_stream_xx() function 492 */ 493static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, 494 struct snd_pcm_substream *substream) 495{ 496 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; 497} 498 499static int fsi_stream_is_working(struct fsi_priv *fsi, 500 struct fsi_stream *io) 501{ 502 struct fsi_master *master = fsi_get_master(fsi); 503 unsigned long flags; 504 int ret; 505 506 spin_lock_irqsave(&master->lock, flags); 507 ret = !!(io->substream && io->substream->runtime); 508 spin_unlock_irqrestore(&master->lock, flags); 509 510 return ret; 511} 512 513static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) 514{ 515 return io->priv; 516} 517 518static void fsi_stream_init(struct fsi_priv *fsi, 519 struct fsi_stream *io, 520 struct snd_pcm_substream *substream) 521{ 522 struct snd_pcm_runtime *runtime = substream->runtime; 523 struct fsi_master *master = fsi_get_master(fsi); 524 unsigned long flags; 525 526 spin_lock_irqsave(&master->lock, flags); 527 io->substream = substream; 528 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); 529 io->buff_sample_pos = 0; 530 io->period_samples = fsi_frame2sample(fsi, runtime->period_size); 531 io->period_pos = 0; 532 io->sample_width = samples_to_bytes(runtime, 1); 533 io->bus_option = 0; 534 io->oerr_num = -1; /* ignore 1st err */ 535 io->uerr_num = -1; /* ignore 1st err */ 536 fsi_stream_handler_call(io, init, fsi, io); 537 spin_unlock_irqrestore(&master->lock, flags); 538} 539 540static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) 541{ 542 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 543 struct fsi_master *master = fsi_get_master(fsi); 544 unsigned long flags; 545 546 spin_lock_irqsave(&master->lock, flags); 547 548 if (io->oerr_num > 0) 549 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 550 551 if (io->uerr_num > 0) 552 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 553 554 fsi_stream_handler_call(io, quit, fsi, io); 555 io->substream = NULL; 556 io->buff_sample_capa = 0; 557 io->buff_sample_pos = 0; 558 io->period_samples = 0; 559 io->period_pos = 0; 560 io->sample_width = 0; 561 io->bus_option = 0; 562 io->oerr_num = 0; 563 io->uerr_num = 0; 564 spin_unlock_irqrestore(&master->lock, flags); 565} 566 567static int fsi_stream_transfer(struct fsi_stream *io) 568{ 569 struct fsi_priv *fsi = fsi_stream_to_priv(io); 570 if (!fsi) 571 return -EIO; 572 573 return fsi_stream_handler_call(io, transfer, fsi, io); 574} 575 576#define fsi_stream_start(fsi, io)\ 577 fsi_stream_handler_call(io, start_stop, fsi, io, 1) 578 579#define fsi_stream_stop(fsi, io)\ 580 fsi_stream_handler_call(io, start_stop, fsi, io, 0) 581 582static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) 583{ 584 struct fsi_stream *io; 585 int ret1, ret2; 586 587 io = &fsi->playback; 588 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); 589 590 io = &fsi->capture; 591 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); 592 593 if (ret1 < 0) 594 return ret1; 595 if (ret2 < 0) 596 return ret2; 597 598 return 0; 599} 600 601static int fsi_stream_remove(struct fsi_priv *fsi) 602{ 603 struct fsi_stream *io; 604 int ret1, ret2; 605 606 io = &fsi->playback; 607 ret1 = fsi_stream_handler_call(io, remove, fsi, io); 608 609 io = &fsi->capture; 610 ret2 = fsi_stream_handler_call(io, remove, fsi, io); 611 612 if (ret1 < 0) 613 return ret1; 614 if (ret2 < 0) 615 return ret2; 616 617 return 0; 618} 619 620/* 621 * format/bus/dma setting 622 */ 623static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, 624 u32 bus, struct device *dev) 625{ 626 struct fsi_master *master = fsi_get_master(fsi); 627 int is_play = fsi_stream_is_play(fsi, io); 628 u32 fmt = fsi->fmt; 629 630 if (fsi_version(master) >= 2) { 631 u32 dma = 0; 632 633 /* 634 * FSI2 needs DMA/Bus setting 635 */ 636 switch (bus) { 637 case PACKAGE_24BITBUS_FRONT: 638 fmt |= CR_BWS_24; 639 dma |= VDMD_FRONT; 640 dev_dbg(dev, "24bit bus / package in front\n"); 641 break; 642 case PACKAGE_16BITBUS_STREAM: 643 fmt |= CR_BWS_16; 644 dma |= VDMD_STREAM; 645 dev_dbg(dev, "16bit bus / stream mode\n"); 646 break; 647 case PACKAGE_24BITBUS_BACK: 648 default: 649 fmt |= CR_BWS_24; 650 dma |= VDMD_BACK; 651 dev_dbg(dev, "24bit bus / package in back\n"); 652 break; 653 } 654 655 if (is_play) 656 fsi_reg_write(fsi, OUT_DMAC, dma); 657 else 658 fsi_reg_write(fsi, IN_DMAC, dma); 659 } 660 661 if (is_play) 662 fsi_reg_write(fsi, DO_FMT, fmt); 663 else 664 fsi_reg_write(fsi, DI_FMT, fmt); 665} 666 667/* 668 * irq function 669 */ 670 671static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) 672{ 673 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 674 struct fsi_master *master = fsi_get_master(fsi); 675 676 fsi_core_mask_set(master, imsk, data, data); 677 fsi_core_mask_set(master, iemsk, data, data); 678} 679 680static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) 681{ 682 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 683 struct fsi_master *master = fsi_get_master(fsi); 684 685 fsi_core_mask_set(master, imsk, data, 0); 686 fsi_core_mask_set(master, iemsk, data, 0); 687} 688 689static u32 fsi_irq_get_status(struct fsi_master *master) 690{ 691 return fsi_core_read(master, int_st); 692} 693 694static void fsi_irq_clear_status(struct fsi_priv *fsi) 695{ 696 u32 data = 0; 697 struct fsi_master *master = fsi_get_master(fsi); 698 699 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); 700 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); 701 702 /* clear interrupt factor */ 703 fsi_core_mask_set(master, int_st, data, 0); 704} 705 706/* 707 * SPDIF master clock function 708 * 709 * These functions are used later FSI2 710 */ 711static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 712{ 713 struct fsi_master *master = fsi_get_master(fsi); 714 u32 mask, val; 715 716 mask = BP | SE; 717 val = enable ? mask : 0; 718 719 fsi_is_port_a(fsi) ? 720 fsi_core_mask_set(master, a_mclk, mask, val) : 721 fsi_core_mask_set(master, b_mclk, mask, val); 722} 723 724/* 725 * clock function 726 */ 727static int fsi_clk_init(struct device *dev, 728 struct fsi_priv *fsi, 729 int xck, 730 int ick, 731 int div, 732 int (*set_rate)(struct device *dev, 733 struct fsi_priv *fsi)) 734{ 735 struct fsi_clk *clock = &fsi->clock; 736 int is_porta = fsi_is_port_a(fsi); 737 738 clock->xck = NULL; 739 clock->ick = NULL; 740 clock->div = NULL; 741 clock->rate = 0; 742 clock->count = 0; 743 clock->set_rate = set_rate; 744 745 clock->own = devm_clk_get(dev, NULL); 746 if (IS_ERR(clock->own)) 747 return -EINVAL; 748 749 /* external clock */ 750 if (xck) { 751 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); 752 if (IS_ERR(clock->xck)) { 753 dev_err(dev, "can't get xck clock\n"); 754 return -EINVAL; 755 } 756 if (clock->xck == clock->own) { 757 dev_err(dev, "cpu doesn't support xck clock\n"); 758 return -EINVAL; 759 } 760 } 761 762 /* FSIACLK/FSIBCLK */ 763 if (ick) { 764 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); 765 if (IS_ERR(clock->ick)) { 766 dev_err(dev, "can't get ick clock\n"); 767 return -EINVAL; 768 } 769 if (clock->ick == clock->own) { 770 dev_err(dev, "cpu doesn't support ick clock\n"); 771 return -EINVAL; 772 } 773 } 774 775 /* FSI-DIV */ 776 if (div) { 777 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); 778 if (IS_ERR(clock->div)) { 779 dev_err(dev, "can't get div clock\n"); 780 return -EINVAL; 781 } 782 if (clock->div == clock->own) { 783 dev_err(dev, "cpu doesn't support div clock\n"); 784 return -EINVAL; 785 } 786 } 787 788 return 0; 789} 790 791#define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) 792static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) 793{ 794 fsi->clock.rate = rate; 795} 796 797static int fsi_clk_is_valid(struct fsi_priv *fsi) 798{ 799 return fsi->clock.set_rate && 800 fsi->clock.rate; 801} 802 803static int fsi_clk_enable(struct device *dev, 804 struct fsi_priv *fsi) 805{ 806 struct fsi_clk *clock = &fsi->clock; 807 int ret = -EINVAL; 808 809 if (!fsi_clk_is_valid(fsi)) 810 return ret; 811 812 if (0 == clock->count) { 813 ret = clock->set_rate(dev, fsi); 814 if (ret < 0) { 815 fsi_clk_invalid(fsi); 816 return ret; 817 } 818 819 ret = clk_enable(clock->xck); 820 if (ret) 821 goto err; 822 ret = clk_enable(clock->ick); 823 if (ret) 824 goto disable_xck; 825 ret = clk_enable(clock->div); 826 if (ret) 827 goto disable_ick; 828 829 clock->count++; 830 } 831 832 return ret; 833 834disable_ick: 835 clk_disable(clock->ick); 836disable_xck: 837 clk_disable(clock->xck); 838err: 839 return ret; 840} 841 842static int fsi_clk_disable(struct device *dev, 843 struct fsi_priv *fsi) 844{ 845 struct fsi_clk *clock = &fsi->clock; 846 847 if (!fsi_clk_is_valid(fsi)) 848 return -EINVAL; 849 850 if (1 == clock->count--) { 851 clk_disable(clock->xck); 852 clk_disable(clock->ick); 853 clk_disable(clock->div); 854 } 855 856 return 0; 857} 858 859static int fsi_clk_set_ackbpf(struct device *dev, 860 struct fsi_priv *fsi, 861 int ackmd, int bpfmd) 862{ 863 u32 data = 0; 864 865 /* check ackmd/bpfmd relationship */ 866 if (bpfmd > ackmd) { 867 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); 868 return -EINVAL; 869 } 870 871 /* ACKMD */ 872 switch (ackmd) { 873 case 512: 874 data |= (0x0 << 12); 875 break; 876 case 256: 877 data |= (0x1 << 12); 878 break; 879 case 128: 880 data |= (0x2 << 12); 881 break; 882 case 64: 883 data |= (0x3 << 12); 884 break; 885 case 32: 886 data |= (0x4 << 12); 887 break; 888 default: 889 dev_err(dev, "unsupported ackmd (%d)\n", ackmd); 890 return -EINVAL; 891 } 892 893 /* BPFMD */ 894 switch (bpfmd) { 895 case 32: 896 data |= (0x0 << 8); 897 break; 898 case 64: 899 data |= (0x1 << 8); 900 break; 901 case 128: 902 data |= (0x2 << 8); 903 break; 904 case 256: 905 data |= (0x3 << 8); 906 break; 907 case 512: 908 data |= (0x4 << 8); 909 break; 910 case 16: 911 data |= (0x7 << 8); 912 break; 913 default: 914 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); 915 return -EINVAL; 916 } 917 918 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); 919 920 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 921 udelay(10); 922 923 return 0; 924} 925 926static int fsi_clk_set_rate_external(struct device *dev, 927 struct fsi_priv *fsi) 928{ 929 struct clk *xck = fsi->clock.xck; 930 struct clk *ick = fsi->clock.ick; 931 unsigned long rate = fsi->clock.rate; 932 unsigned long xrate; 933 int ackmd, bpfmd; 934 int ret = 0; 935 936 /* check clock rate */ 937 xrate = clk_get_rate(xck); 938 if (xrate % rate) { 939 dev_err(dev, "unsupported clock rate\n"); 940 return -EINVAL; 941 } 942 943 clk_set_parent(ick, xck); 944 clk_set_rate(ick, xrate); 945 946 bpfmd = fsi->chan_num * 32; 947 ackmd = xrate / rate; 948 949 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); 950 951 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 952 if (ret < 0) 953 dev_err(dev, "%s failed", __func__); 954 955 return ret; 956} 957 958static int fsi_clk_set_rate_cpg(struct device *dev, 959 struct fsi_priv *fsi) 960{ 961 struct clk *ick = fsi->clock.ick; 962 struct clk *div = fsi->clock.div; 963 unsigned long rate = fsi->clock.rate; 964 unsigned long target = 0; /* 12288000 or 11289600 */ 965 unsigned long actual, cout; 966 unsigned long diff, min; 967 unsigned long best_cout, best_act; 968 int adj; 969 int ackmd, bpfmd; 970 int ret = -EINVAL; 971 972 if (!(12288000 % rate)) 973 target = 12288000; 974 if (!(11289600 % rate)) 975 target = 11289600; 976 if (!target) { 977 dev_err(dev, "unsupported rate\n"); 978 return ret; 979 } 980 981 bpfmd = fsi->chan_num * 32; 982 ackmd = target / rate; 983 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 984 if (ret < 0) { 985 dev_err(dev, "%s failed", __func__); 986 return ret; 987 } 988 989 /* 990 * The clock flow is 991 * 992 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] 993 * 994 * But, it needs to find best match of CPG and FSI_DIV 995 * combination, since it is difficult to generate correct 996 * frequency of audio clock from ick clock only. 997 * Because ick is created from its parent clock. 998 * 999 * target = rate x [512/256/128/64]fs 1000 * cout = round(target x adjustment) 1001 * actual = cout / adjustment (by FSI-DIV) ~= target 1002 * audio = actual 1003 */ 1004 min = ~0; 1005 best_cout = 0; 1006 best_act = 0; 1007 for (adj = 1; adj < 0xffff; adj++) { 1008 1009 cout = target * adj; 1010 if (cout > 100000000) /* max clock = 100MHz */ 1011 break; 1012 1013 /* cout/actual audio clock */ 1014 cout = clk_round_rate(ick, cout); 1015 actual = cout / adj; 1016 1017 /* find best frequency */ 1018 diff = abs(actual - target); 1019 if (diff < min) { 1020 min = diff; 1021 best_cout = cout; 1022 best_act = actual; 1023 } 1024 } 1025 1026 ret = clk_set_rate(ick, best_cout); 1027 if (ret < 0) { 1028 dev_err(dev, "ick clock failed\n"); 1029 return -EIO; 1030 } 1031 1032 ret = clk_set_rate(div, clk_round_rate(div, best_act)); 1033 if (ret < 0) { 1034 dev_err(dev, "div clock failed\n"); 1035 return -EIO; 1036 } 1037 1038 dev_dbg(dev, "ick/div = %ld/%ld\n", 1039 clk_get_rate(ick), clk_get_rate(div)); 1040 1041 return ret; 1042} 1043 1044static void fsi_pointer_update(struct fsi_stream *io, int size) 1045{ 1046 io->buff_sample_pos += size; 1047 1048 if (io->buff_sample_pos >= 1049 io->period_samples * (io->period_pos + 1)) { 1050 struct snd_pcm_substream *substream = io->substream; 1051 struct snd_pcm_runtime *runtime = substream->runtime; 1052 1053 io->period_pos++; 1054 1055 if (io->period_pos >= runtime->periods) { 1056 io->buff_sample_pos = 0; 1057 io->period_pos = 0; 1058 } 1059 1060 snd_pcm_period_elapsed(substream); 1061 } 1062} 1063 1064/* 1065 * pio data transfer handler 1066 */ 1067static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) 1068{ 1069 int i; 1070 1071 if (fsi_is_enable_stream(fsi)) { 1072 /* 1073 * stream mode 1074 * see 1075 * fsi_pio_push_init() 1076 */ 1077 u32 *buf = (u32 *)_buf; 1078 1079 for (i = 0; i < samples / 2; i++) 1080 fsi_reg_write(fsi, DODT, buf[i]); 1081 } else { 1082 /* normal mode */ 1083 u16 *buf = (u16 *)_buf; 1084 1085 for (i = 0; i < samples; i++) 1086 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); 1087 } 1088} 1089 1090static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) 1091{ 1092 u16 *buf = (u16 *)_buf; 1093 int i; 1094 1095 for (i = 0; i < samples; i++) 1096 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 1097} 1098 1099static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) 1100{ 1101 u32 *buf = (u32 *)_buf; 1102 int i; 1103 1104 for (i = 0; i < samples; i++) 1105 fsi_reg_write(fsi, DODT, *(buf + i)); 1106} 1107 1108static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) 1109{ 1110 u32 *buf = (u32 *)_buf; 1111 int i; 1112 1113 for (i = 0; i < samples; i++) 1114 *(buf + i) = fsi_reg_read(fsi, DIDT); 1115} 1116 1117static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) 1118{ 1119 struct snd_pcm_runtime *runtime = io->substream->runtime; 1120 1121 return runtime->dma_area + 1122 samples_to_bytes(runtime, io->buff_sample_pos); 1123} 1124 1125static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, 1126 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), 1127 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), 1128 int samples) 1129{ 1130 u8 *buf; 1131 1132 if (!fsi_stream_is_working(fsi, io)) 1133 return -EINVAL; 1134 1135 buf = fsi_pio_get_area(fsi, io); 1136 1137 switch (io->sample_width) { 1138 case 2: 1139 run16(fsi, buf, samples); 1140 break; 1141 case 4: 1142 run32(fsi, buf, samples); 1143 break; 1144 default: 1145 return -EINVAL; 1146 } 1147 1148 fsi_pointer_update(io, samples); 1149 1150 return 0; 1151} 1152 1153static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) 1154{ 1155 int sample_residues; /* samples in FSI fifo */ 1156 int sample_space; /* ALSA free samples space */ 1157 int samples; 1158 1159 sample_residues = fsi_get_current_fifo_samples(fsi, io); 1160 sample_space = io->buff_sample_capa - io->buff_sample_pos; 1161 1162 samples = min(sample_residues, sample_space); 1163 1164 return fsi_pio_transfer(fsi, io, 1165 fsi_pio_pop16, 1166 fsi_pio_pop32, 1167 samples); 1168} 1169 1170static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) 1171{ 1172 int sample_residues; /* ALSA residue samples */ 1173 int sample_space; /* FSI fifo free samples space */ 1174 int samples; 1175 1176 sample_residues = io->buff_sample_capa - io->buff_sample_pos; 1177 sample_space = io->fifo_sample_capa - 1178 fsi_get_current_fifo_samples(fsi, io); 1179 1180 samples = min(sample_residues, sample_space); 1181 1182 return fsi_pio_transfer(fsi, io, 1183 fsi_pio_push16, 1184 fsi_pio_push32, 1185 samples); 1186} 1187 1188static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1189 int enable) 1190{ 1191 struct fsi_master *master = fsi_get_master(fsi); 1192 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1193 1194 if (enable) 1195 fsi_irq_enable(fsi, io); 1196 else 1197 fsi_irq_disable(fsi, io); 1198 1199 if (fsi_is_clk_master(fsi)) 1200 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1201 1202 return 0; 1203} 1204 1205static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) 1206{ 1207 /* 1208 * we can use 16bit stream mode 1209 * when "playback" and "16bit data" 1210 * and platform allows "stream mode" 1211 * see 1212 * fsi_pio_push16() 1213 */ 1214 if (fsi_is_enable_stream(fsi)) 1215 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1216 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1217 else 1218 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1219 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1220 return 0; 1221} 1222 1223static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) 1224{ 1225 /* 1226 * always 24bit bus, package back when "capture" 1227 */ 1228 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1229 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1230 return 0; 1231} 1232 1233static struct fsi_stream_handler fsi_pio_push_handler = { 1234 .init = fsi_pio_push_init, 1235 .transfer = fsi_pio_push, 1236 .start_stop = fsi_pio_start_stop, 1237}; 1238 1239static struct fsi_stream_handler fsi_pio_pop_handler = { 1240 .init = fsi_pio_pop_init, 1241 .transfer = fsi_pio_pop, 1242 .start_stop = fsi_pio_start_stop, 1243}; 1244 1245static irqreturn_t fsi_interrupt(int irq, void *data) 1246{ 1247 struct fsi_master *master = data; 1248 u32 int_st = fsi_irq_get_status(master); 1249 1250 /* clear irq status */ 1251 fsi_master_mask_set(master, SOFT_RST, IR, 0); 1252 fsi_master_mask_set(master, SOFT_RST, IR, IR); 1253 1254 if (int_st & AB_IO(1, AO_SHIFT)) 1255 fsi_stream_transfer(&master->fsia.playback); 1256 if (int_st & AB_IO(1, BO_SHIFT)) 1257 fsi_stream_transfer(&master->fsib.playback); 1258 if (int_st & AB_IO(1, AI_SHIFT)) 1259 fsi_stream_transfer(&master->fsia.capture); 1260 if (int_st & AB_IO(1, BI_SHIFT)) 1261 fsi_stream_transfer(&master->fsib.capture); 1262 1263 fsi_count_fifo_err(&master->fsia); 1264 fsi_count_fifo_err(&master->fsib); 1265 1266 fsi_irq_clear_status(&master->fsia); 1267 fsi_irq_clear_status(&master->fsib); 1268 1269 return IRQ_HANDLED; 1270} 1271 1272/* 1273 * dma data transfer handler 1274 */ 1275static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) 1276{ 1277 /* 1278 * 24bit data : 24bit bus / package in back 1279 * 16bit data : 16bit bus / stream mode 1280 */ 1281 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1282 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1283 1284 return 0; 1285} 1286 1287static void fsi_dma_complete(void *data) 1288{ 1289 struct fsi_stream *io = (struct fsi_stream *)data; 1290 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1291 1292 fsi_pointer_update(io, io->period_samples); 1293 1294 fsi_count_fifo_err(fsi); 1295} 1296 1297static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) 1298{ 1299 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1300 struct snd_pcm_substream *substream = io->substream; 1301 struct dma_async_tx_descriptor *desc; 1302 int is_play = fsi_stream_is_play(fsi, io); 1303 enum dma_transfer_direction dir; 1304 int ret = -EIO; 1305 1306 if (is_play) 1307 dir = DMA_MEM_TO_DEV; 1308 else 1309 dir = DMA_DEV_TO_MEM; 1310 1311 desc = dmaengine_prep_dma_cyclic(io->chan, 1312 substream->runtime->dma_addr, 1313 snd_pcm_lib_buffer_bytes(substream), 1314 snd_pcm_lib_period_bytes(substream), 1315 dir, 1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1317 if (!desc) { 1318 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n"); 1319 goto fsi_dma_transfer_err; 1320 } 1321 1322 desc->callback = fsi_dma_complete; 1323 desc->callback_param = io; 1324 1325 if (dmaengine_submit(desc) < 0) { 1326 dev_err(dai->dev, "tx_submit() fail\n"); 1327 goto fsi_dma_transfer_err; 1328 } 1329 1330 dma_async_issue_pending(io->chan); 1331 1332 /* 1333 * FIXME 1334 * 1335 * In DMAEngine case, codec and FSI cannot be started simultaneously 1336 * since FSI is using the scheduler work queue. 1337 * Therefore, in capture case, probably FSI FIFO will have got 1338 * overflow error in this point. 1339 * in that case, DMA cannot start transfer until error was cleared. 1340 */ 1341 if (!is_play) { 1342 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { 1343 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1344 fsi_reg_write(fsi, DIFF_ST, 0); 1345 } 1346 } 1347 1348 ret = 0; 1349 1350fsi_dma_transfer_err: 1351 return ret; 1352} 1353 1354static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1355 int start) 1356{ 1357 struct fsi_master *master = fsi_get_master(fsi); 1358 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1359 u32 enable = start ? DMA_ON : 0; 1360 1361 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); 1362 1363 dmaengine_terminate_all(io->chan); 1364 1365 if (fsi_is_clk_master(fsi)) 1366 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1367 1368 return 0; 1369} 1370 1371static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) 1372{ 1373 int is_play = fsi_stream_is_play(fsi, io); 1374 1375#ifdef CONFIG_SUPERH 1376 dma_cap_mask_t mask; 1377 dma_cap_zero(mask); 1378 dma_cap_set(DMA_SLAVE, mask); 1379 1380 io->chan = dma_request_channel(mask, shdma_chan_filter, 1381 (void *)io->dma_id); 1382#else 1383 io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx"); 1384#endif 1385 if (io->chan) { 1386 struct dma_slave_config cfg = {}; 1387 int ret; 1388 1389 if (is_play) { 1390 cfg.dst_addr = fsi->phys + REG_DODT; 1391 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1392 cfg.direction = DMA_MEM_TO_DEV; 1393 } else { 1394 cfg.src_addr = fsi->phys + REG_DIDT; 1395 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1396 cfg.direction = DMA_DEV_TO_MEM; 1397 } 1398 1399 ret = dmaengine_slave_config(io->chan, &cfg); 1400 if (ret < 0) { 1401 dma_release_channel(io->chan); 1402 io->chan = NULL; 1403 } 1404 } 1405 1406 if (!io->chan) { 1407 1408 /* switch to PIO handler */ 1409 if (is_play) 1410 fsi->playback.handler = &fsi_pio_push_handler; 1411 else 1412 fsi->capture.handler = &fsi_pio_pop_handler; 1413 1414 dev_info(dev, "switch handler (dma => pio)\n"); 1415 1416 /* probe again */ 1417 return fsi_stream_probe(fsi, dev); 1418 } 1419 1420 return 0; 1421} 1422 1423static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) 1424{ 1425 fsi_stream_stop(fsi, io); 1426 1427 if (io->chan) 1428 dma_release_channel(io->chan); 1429 1430 io->chan = NULL; 1431 return 0; 1432} 1433 1434static struct fsi_stream_handler fsi_dma_push_handler = { 1435 .init = fsi_dma_init, 1436 .probe = fsi_dma_probe, 1437 .transfer = fsi_dma_transfer, 1438 .remove = fsi_dma_remove, 1439 .start_stop = fsi_dma_push_start_stop, 1440}; 1441 1442/* 1443 * dai ops 1444 */ 1445static void fsi_fifo_init(struct fsi_priv *fsi, 1446 struct fsi_stream *io, 1447 struct device *dev) 1448{ 1449 struct fsi_master *master = fsi_get_master(fsi); 1450 int is_play = fsi_stream_is_play(fsi, io); 1451 u32 shift, i; 1452 int frame_capa; 1453 1454 /* get on-chip RAM capacity */ 1455 shift = fsi_master_read(master, FIFO_SZ); 1456 shift >>= fsi_get_port_shift(fsi, io); 1457 shift &= FIFO_SZ_MASK; 1458 frame_capa = 256 << shift; 1459 dev_dbg(dev, "fifo = %d words\n", frame_capa); 1460 1461 /* 1462 * The maximum number of sample data varies depending 1463 * on the number of channels selected for the format. 1464 * 1465 * FIFOs are used in 4-channel units in 3-channel mode 1466 * and in 8-channel units in 5- to 7-channel mode 1467 * meaning that more FIFOs than the required size of DPRAM 1468 * are used. 1469 * 1470 * ex) if 256 words of DP-RAM is connected 1471 * 1 channel: 256 (256 x 1 = 256) 1472 * 2 channels: 128 (128 x 2 = 256) 1473 * 3 channels: 64 ( 64 x 3 = 192) 1474 * 4 channels: 64 ( 64 x 4 = 256) 1475 * 5 channels: 32 ( 32 x 5 = 160) 1476 * 6 channels: 32 ( 32 x 6 = 192) 1477 * 7 channels: 32 ( 32 x 7 = 224) 1478 * 8 channels: 32 ( 32 x 8 = 256) 1479 */ 1480 for (i = 1; i < fsi->chan_num; i <<= 1) 1481 frame_capa >>= 1; 1482 dev_dbg(dev, "%d channel %d store\n", 1483 fsi->chan_num, frame_capa); 1484 1485 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); 1486 1487 /* 1488 * set interrupt generation factor 1489 * clear FIFO 1490 */ 1491 if (is_play) { 1492 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 1493 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 1494 } else { 1495 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 1496 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1497 } 1498} 1499 1500static int fsi_hw_startup(struct fsi_priv *fsi, 1501 struct fsi_stream *io, 1502 struct device *dev) 1503{ 1504 u32 data = 0; 1505 1506 /* clock setting */ 1507 if (fsi_is_clk_master(fsi)) 1508 data = DIMD | DOMD; 1509 1510 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 1511 1512 /* clock inversion (CKG2) */ 1513 data = 0; 1514 if (fsi->bit_clk_inv) 1515 data |= (1 << 0); 1516 if (fsi->lr_clk_inv) 1517 data |= (1 << 4); 1518 if (fsi_is_clk_master(fsi)) 1519 data <<= 8; 1520 fsi_reg_write(fsi, CKG2, data); 1521 1522 /* spdif ? */ 1523 if (fsi_is_spdif(fsi)) { 1524 fsi_spdif_clk_ctrl(fsi, 1); 1525 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); 1526 } 1527 1528 /* 1529 * get bus settings 1530 */ 1531 data = 0; 1532 switch (io->sample_width) { 1533 case 2: 1534 data = BUSOP_GET(16, io->bus_option); 1535 break; 1536 case 4: 1537 data = BUSOP_GET(24, io->bus_option); 1538 break; 1539 } 1540 fsi_format_bus_setup(fsi, io, data, dev); 1541 1542 /* irq clear */ 1543 fsi_irq_disable(fsi, io); 1544 fsi_irq_clear_status(fsi); 1545 1546 /* fifo init */ 1547 fsi_fifo_init(fsi, io, dev); 1548 1549 /* start master clock */ 1550 if (fsi_is_clk_master(fsi)) 1551 return fsi_clk_enable(dev, fsi); 1552 1553 return 0; 1554} 1555 1556static int fsi_hw_shutdown(struct fsi_priv *fsi, 1557 struct device *dev) 1558{ 1559 /* stop master clock */ 1560 if (fsi_is_clk_master(fsi)) 1561 return fsi_clk_disable(dev, fsi); 1562 1563 return 0; 1564} 1565 1566static int fsi_dai_startup(struct snd_pcm_substream *substream, 1567 struct snd_soc_dai *dai) 1568{ 1569 struct fsi_priv *fsi = fsi_get_priv(substream); 1570 1571 fsi_clk_invalid(fsi); 1572 1573 return 0; 1574} 1575 1576static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 1577 struct snd_soc_dai *dai) 1578{ 1579 struct fsi_priv *fsi = fsi_get_priv(substream); 1580 1581 fsi_clk_invalid(fsi); 1582} 1583 1584static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 1585 struct snd_soc_dai *dai) 1586{ 1587 struct fsi_priv *fsi = fsi_get_priv(substream); 1588 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1589 int ret = 0; 1590 1591 switch (cmd) { 1592 case SNDRV_PCM_TRIGGER_START: 1593 fsi_stream_init(fsi, io, substream); 1594 if (!ret) 1595 ret = fsi_hw_startup(fsi, io, dai->dev); 1596 if (!ret) 1597 ret = fsi_stream_start(fsi, io); 1598 if (!ret) 1599 ret = fsi_stream_transfer(io); 1600 break; 1601 case SNDRV_PCM_TRIGGER_STOP: 1602 if (!ret) 1603 ret = fsi_hw_shutdown(fsi, dai->dev); 1604 fsi_stream_stop(fsi, io); 1605 fsi_stream_quit(fsi, io); 1606 break; 1607 } 1608 1609 return ret; 1610} 1611 1612static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) 1613{ 1614 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1615 case SND_SOC_DAIFMT_I2S: 1616 fsi->fmt = CR_I2S; 1617 fsi->chan_num = 2; 1618 break; 1619 case SND_SOC_DAIFMT_LEFT_J: 1620 fsi->fmt = CR_PCM; 1621 fsi->chan_num = 2; 1622 break; 1623 default: 1624 return -EINVAL; 1625 } 1626 1627 return 0; 1628} 1629 1630static int fsi_set_fmt_spdif(struct fsi_priv *fsi) 1631{ 1632 struct fsi_master *master = fsi_get_master(fsi); 1633 1634 if (fsi_version(master) < 2) 1635 return -EINVAL; 1636 1637 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; 1638 fsi->chan_num = 2; 1639 1640 return 0; 1641} 1642 1643static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1644{ 1645 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 1646 int ret; 1647 1648 /* set clock master audio interface */ 1649 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1650 case SND_SOC_DAIFMT_CBM_CFM: 1651 break; 1652 case SND_SOC_DAIFMT_CBS_CFS: 1653 fsi->clk_master = 1; /* cpu is master */ 1654 break; 1655 default: 1656 return -EINVAL; 1657 } 1658 1659 /* set clock inversion */ 1660 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1661 case SND_SOC_DAIFMT_NB_IF: 1662 fsi->bit_clk_inv = 0; 1663 fsi->lr_clk_inv = 1; 1664 break; 1665 case SND_SOC_DAIFMT_IB_NF: 1666 fsi->bit_clk_inv = 1; 1667 fsi->lr_clk_inv = 0; 1668 break; 1669 case SND_SOC_DAIFMT_IB_IF: 1670 fsi->bit_clk_inv = 1; 1671 fsi->lr_clk_inv = 1; 1672 break; 1673 case SND_SOC_DAIFMT_NB_NF: 1674 default: 1675 fsi->bit_clk_inv = 0; 1676 fsi->lr_clk_inv = 0; 1677 break; 1678 } 1679 1680 if (fsi_is_clk_master(fsi)) { 1681 if (fsi->clk_cpg) 1682 fsi_clk_init(dai->dev, fsi, 0, 1, 1, 1683 fsi_clk_set_rate_cpg); 1684 else 1685 fsi_clk_init(dai->dev, fsi, 1, 1, 0, 1686 fsi_clk_set_rate_external); 1687 } 1688 1689 /* set format */ 1690 if (fsi_is_spdif(fsi)) 1691 ret = fsi_set_fmt_spdif(fsi); 1692 else 1693 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1694 1695 return ret; 1696} 1697 1698static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 1699 struct snd_pcm_hw_params *params, 1700 struct snd_soc_dai *dai) 1701{ 1702 struct fsi_priv *fsi = fsi_get_priv(substream); 1703 1704 if (fsi_is_clk_master(fsi)) 1705 fsi_clk_valid(fsi, params_rate(params)); 1706 1707 return 0; 1708} 1709 1710static const struct snd_soc_dai_ops fsi_dai_ops = { 1711 .startup = fsi_dai_startup, 1712 .shutdown = fsi_dai_shutdown, 1713 .trigger = fsi_dai_trigger, 1714 .set_fmt = fsi_dai_set_fmt, 1715 .hw_params = fsi_dai_hw_params, 1716}; 1717 1718/* 1719 * pcm ops 1720 */ 1721 1722static const struct snd_pcm_hardware fsi_pcm_hardware = { 1723 .info = SNDRV_PCM_INFO_INTERLEAVED | 1724 SNDRV_PCM_INFO_MMAP | 1725 SNDRV_PCM_INFO_MMAP_VALID, 1726 .buffer_bytes_max = 64 * 1024, 1727 .period_bytes_min = 32, 1728 .period_bytes_max = 8192, 1729 .periods_min = 1, 1730 .periods_max = 32, 1731 .fifo_size = 256, 1732}; 1733 1734static int fsi_pcm_open(struct snd_soc_component *component, 1735 struct snd_pcm_substream *substream) 1736{ 1737 struct snd_pcm_runtime *runtime = substream->runtime; 1738 int ret = 0; 1739 1740 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1741 1742 ret = snd_pcm_hw_constraint_integer(runtime, 1743 SNDRV_PCM_HW_PARAM_PERIODS); 1744 1745 return ret; 1746} 1747 1748static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component, 1749 struct snd_pcm_substream *substream) 1750{ 1751 struct fsi_priv *fsi = fsi_get_priv(substream); 1752 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1753 1754 return fsi_sample2frame(fsi, io->buff_sample_pos); 1755} 1756 1757/* 1758 * snd_soc_component 1759 */ 1760 1761#define PREALLOC_BUFFER (32 * 1024) 1762#define PREALLOC_BUFFER_MAX (32 * 1024) 1763 1764static int fsi_pcm_new(struct snd_soc_component *component, 1765 struct snd_soc_pcm_runtime *rtd) 1766{ 1767 snd_pcm_set_managed_buffer_all( 1768 rtd->pcm, 1769 SNDRV_DMA_TYPE_DEV, 1770 rtd->card->snd_card->dev, 1771 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1772 return 0; 1773} 1774 1775/* 1776 * alsa struct 1777 */ 1778 1779static struct snd_soc_dai_driver fsi_soc_dai[] = { 1780 { 1781 .name = "fsia-dai", 1782 .playback = { 1783 .rates = FSI_RATES, 1784 .formats = FSI_FMTS, 1785 .channels_min = 2, 1786 .channels_max = 2, 1787 }, 1788 .capture = { 1789 .rates = FSI_RATES, 1790 .formats = FSI_FMTS, 1791 .channels_min = 2, 1792 .channels_max = 2, 1793 }, 1794 .ops = &fsi_dai_ops, 1795 }, 1796 { 1797 .name = "fsib-dai", 1798 .playback = { 1799 .rates = FSI_RATES, 1800 .formats = FSI_FMTS, 1801 .channels_min = 2, 1802 .channels_max = 2, 1803 }, 1804 .capture = { 1805 .rates = FSI_RATES, 1806 .formats = FSI_FMTS, 1807 .channels_min = 2, 1808 .channels_max = 2, 1809 }, 1810 .ops = &fsi_dai_ops, 1811 }, 1812}; 1813 1814static const struct snd_soc_component_driver fsi_soc_component = { 1815 .name = "fsi", 1816 .open = fsi_pcm_open, 1817 .pointer = fsi_pointer, 1818 .pcm_construct = fsi_pcm_new, 1819}; 1820 1821/* 1822 * platform function 1823 */ 1824static void fsi_of_parse(char *name, 1825 struct device_node *np, 1826 struct sh_fsi_port_info *info, 1827 struct device *dev) 1828{ 1829 int i; 1830 char prop[128]; 1831 unsigned long flags = 0; 1832 struct { 1833 char *name; 1834 unsigned int val; 1835 } of_parse_property[] = { 1836 { "spdif-connection", SH_FSI_FMT_SPDIF }, 1837 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, 1838 { "use-internal-clock", SH_FSI_CLK_CPG }, 1839 }; 1840 1841 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { 1842 sprintf(prop, "%s,%s", name, of_parse_property[i].name); 1843 if (of_get_property(np, prop, NULL)) 1844 flags |= of_parse_property[i].val; 1845 } 1846 info->flags = flags; 1847 1848 dev_dbg(dev, "%s flags : %lx\n", name, info->flags); 1849} 1850 1851static void fsi_port_info_init(struct fsi_priv *fsi, 1852 struct sh_fsi_port_info *info) 1853{ 1854 if (info->flags & SH_FSI_FMT_SPDIF) 1855 fsi->spdif = 1; 1856 1857 if (info->flags & SH_FSI_CLK_CPG) 1858 fsi->clk_cpg = 1; 1859 1860 if (info->flags & SH_FSI_ENABLE_STREAM_MODE) 1861 fsi->enable_stream = 1; 1862} 1863 1864static void fsi_handler_init(struct fsi_priv *fsi, 1865 struct sh_fsi_port_info *info) 1866{ 1867 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ 1868 fsi->playback.priv = fsi; 1869 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ 1870 fsi->capture.priv = fsi; 1871 1872 if (info->tx_id) { 1873 fsi->playback.dma_id = info->tx_id; 1874 fsi->playback.handler = &fsi_dma_push_handler; 1875 } 1876} 1877 1878static const struct fsi_core fsi1_core = { 1879 .ver = 1, 1880 1881 /* Interrupt */ 1882 .int_st = INT_ST, 1883 .iemsk = IEMSK, 1884 .imsk = IMSK, 1885}; 1886 1887static const struct fsi_core fsi2_core = { 1888 .ver = 2, 1889 1890 /* Interrupt */ 1891 .int_st = CPU_INT_ST, 1892 .iemsk = CPU_IEMSK, 1893 .imsk = CPU_IMSK, 1894 .a_mclk = A_MST_CTLR, 1895 .b_mclk = B_MST_CTLR, 1896}; 1897 1898static const struct of_device_id fsi_of_match[] = { 1899 { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, 1900 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, 1901 {}, 1902}; 1903MODULE_DEVICE_TABLE(of, fsi_of_match); 1904 1905static const struct platform_device_id fsi_id_table[] = { 1906 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 1907 {}, 1908}; 1909MODULE_DEVICE_TABLE(platform, fsi_id_table); 1910 1911static int fsi_probe(struct platform_device *pdev) 1912{ 1913 struct fsi_master *master; 1914 struct device_node *np = pdev->dev.of_node; 1915 struct sh_fsi_platform_info info; 1916 const struct fsi_core *core; 1917 struct fsi_priv *fsi; 1918 struct resource *res; 1919 unsigned int irq; 1920 int ret; 1921 1922 memset(&info, 0, sizeof(info)); 1923 1924 core = NULL; 1925 if (np) { 1926 core = of_device_get_match_data(&pdev->dev); 1927 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); 1928 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); 1929 } else { 1930 const struct platform_device_id *id_entry = pdev->id_entry; 1931 if (id_entry) 1932 core = (struct fsi_core *)id_entry->driver_data; 1933 1934 if (pdev->dev.platform_data) 1935 memcpy(&info, pdev->dev.platform_data, sizeof(info)); 1936 } 1937 1938 if (!core) { 1939 dev_err(&pdev->dev, "unknown fsi device\n"); 1940 return -ENODEV; 1941 } 1942 1943 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1944 irq = platform_get_irq(pdev, 0); 1945 if (!res || (int)irq <= 0) { 1946 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 1947 return -ENODEV; 1948 } 1949 1950 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1951 if (!master) 1952 return -ENOMEM; 1953 1954 master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1955 if (!master->base) { 1956 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 1957 return -ENXIO; 1958 } 1959 1960 /* master setting */ 1961 master->core = core; 1962 spin_lock_init(&master->lock); 1963 1964 /* FSI A setting */ 1965 fsi = &master->fsia; 1966 fsi->base = master->base; 1967 fsi->phys = res->start; 1968 fsi->master = master; 1969 fsi_port_info_init(fsi, &info.port_a); 1970 fsi_handler_init(fsi, &info.port_a); 1971 ret = fsi_stream_probe(fsi, &pdev->dev); 1972 if (ret < 0) { 1973 dev_err(&pdev->dev, "FSIA stream probe failed\n"); 1974 return ret; 1975 } 1976 1977 /* FSI B setting */ 1978 fsi = &master->fsib; 1979 fsi->base = master->base + 0x40; 1980 fsi->phys = res->start + 0x40; 1981 fsi->master = master; 1982 fsi_port_info_init(fsi, &info.port_b); 1983 fsi_handler_init(fsi, &info.port_b); 1984 ret = fsi_stream_probe(fsi, &pdev->dev); 1985 if (ret < 0) { 1986 dev_err(&pdev->dev, "FSIB stream probe failed\n"); 1987 goto exit_fsia; 1988 } 1989 1990 pm_runtime_enable(&pdev->dev); 1991 dev_set_drvdata(&pdev->dev, master); 1992 1993 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, 1994 dev_name(&pdev->dev), master); 1995 if (ret) { 1996 dev_err(&pdev->dev, "irq request err\n"); 1997 goto exit_fsib; 1998 } 1999 2000 ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component, 2001 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 2002 if (ret < 0) { 2003 dev_err(&pdev->dev, "cannot snd component register\n"); 2004 goto exit_fsib; 2005 } 2006 2007 return ret; 2008 2009exit_fsib: 2010 pm_runtime_disable(&pdev->dev); 2011 fsi_stream_remove(&master->fsib); 2012exit_fsia: 2013 fsi_stream_remove(&master->fsia); 2014 2015 return ret; 2016} 2017 2018static int fsi_remove(struct platform_device *pdev) 2019{ 2020 struct fsi_master *master; 2021 2022 master = dev_get_drvdata(&pdev->dev); 2023 2024 pm_runtime_disable(&pdev->dev); 2025 2026 fsi_stream_remove(&master->fsia); 2027 fsi_stream_remove(&master->fsib); 2028 2029 return 0; 2030} 2031 2032static void __fsi_suspend(struct fsi_priv *fsi, 2033 struct fsi_stream *io, 2034 struct device *dev) 2035{ 2036 if (!fsi_stream_is_working(fsi, io)) 2037 return; 2038 2039 fsi_stream_stop(fsi, io); 2040 fsi_hw_shutdown(fsi, dev); 2041} 2042 2043static void __fsi_resume(struct fsi_priv *fsi, 2044 struct fsi_stream *io, 2045 struct device *dev) 2046{ 2047 if (!fsi_stream_is_working(fsi, io)) 2048 return; 2049 2050 fsi_hw_startup(fsi, io, dev); 2051 fsi_stream_start(fsi, io); 2052} 2053 2054static int fsi_suspend(struct device *dev) 2055{ 2056 struct fsi_master *master = dev_get_drvdata(dev); 2057 struct fsi_priv *fsia = &master->fsia; 2058 struct fsi_priv *fsib = &master->fsib; 2059 2060 __fsi_suspend(fsia, &fsia->playback, dev); 2061 __fsi_suspend(fsia, &fsia->capture, dev); 2062 2063 __fsi_suspend(fsib, &fsib->playback, dev); 2064 __fsi_suspend(fsib, &fsib->capture, dev); 2065 2066 return 0; 2067} 2068 2069static int fsi_resume(struct device *dev) 2070{ 2071 struct fsi_master *master = dev_get_drvdata(dev); 2072 struct fsi_priv *fsia = &master->fsia; 2073 struct fsi_priv *fsib = &master->fsib; 2074 2075 __fsi_resume(fsia, &fsia->playback, dev); 2076 __fsi_resume(fsia, &fsia->capture, dev); 2077 2078 __fsi_resume(fsib, &fsib->playback, dev); 2079 __fsi_resume(fsib, &fsib->capture, dev); 2080 2081 return 0; 2082} 2083 2084static const struct dev_pm_ops fsi_pm_ops = { 2085 .suspend = fsi_suspend, 2086 .resume = fsi_resume, 2087}; 2088 2089static struct platform_driver fsi_driver = { 2090 .driver = { 2091 .name = "fsi-pcm-audio", 2092 .pm = &fsi_pm_ops, 2093 .of_match_table = fsi_of_match, 2094 }, 2095 .probe = fsi_probe, 2096 .remove = fsi_remove, 2097 .id_table = fsi_id_table, 2098}; 2099 2100module_platform_driver(fsi_driver); 2101 2102MODULE_LICENSE("GPL v2"); 2103MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 2104MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 2105MODULE_ALIAS("platform:fsi-pcm-audio"); 2106