1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Copyright (c) 2018 BayLibre, SAS. 4// Author: Jerome Brunet <jbrunet@baylibre.com> 5 6#include <linux/clk.h> 7#include <linux/module.h> 8#include <linux/of_irq.h> 9#include <linux/of_platform.h> 10#include <linux/regmap.h> 11#include <sound/soc.h> 12#include <sound/soc-dai.h> 13#include <sound/pcm_params.h> 14 15#define PDM_CTRL 0x00 16#define PDM_CTRL_EN BIT(31) 17#define PDM_CTRL_OUT_MODE BIT(29) 18#define PDM_CTRL_BYPASS_MODE BIT(28) 19#define PDM_CTRL_RST_FIFO BIT(16) 20#define PDM_CTRL_CHAN_RSTN_MASK GENMASK(15, 8) 21#define PDM_CTRL_CHAN_RSTN(x) ((x) << 8) 22#define PDM_CTRL_CHAN_EN_MASK GENMASK(7, 0) 23#define PDM_CTRL_CHAN_EN(x) ((x) << 0) 24#define PDM_HCIC_CTRL1 0x04 25#define PDM_FILTER_EN BIT(31) 26#define PDM_HCIC_CTRL1_GAIN_SFT_MASK GENMASK(29, 24) 27#define PDM_HCIC_CTRL1_GAIN_SFT(x) ((x) << 24) 28#define PDM_HCIC_CTRL1_GAIN_MULT_MASK GENMASK(23, 16) 29#define PDM_HCIC_CTRL1_GAIN_MULT(x) ((x) << 16) 30#define PDM_HCIC_CTRL1_DSR_MASK GENMASK(8, 4) 31#define PDM_HCIC_CTRL1_DSR(x) ((x) << 4) 32#define PDM_HCIC_CTRL1_STAGE_NUM_MASK GENMASK(3, 0) 33#define PDM_HCIC_CTRL1_STAGE_NUM(x) ((x) << 0) 34#define PDM_HCIC_CTRL2 0x08 35#define PDM_F1_CTRL 0x0c 36#define PDM_LPF_ROUND_MODE_MASK GENMASK(17, 16) 37#define PDM_LPF_ROUND_MODE(x) ((x) << 16) 38#define PDM_LPF_DSR_MASK GENMASK(15, 12) 39#define PDM_LPF_DSR(x) ((x) << 12) 40#define PDM_LPF_STAGE_NUM_MASK GENMASK(8, 0) 41#define PDM_LPF_STAGE_NUM(x) ((x) << 0) 42#define PDM_LPF_MAX_STAGE 336 43#define PDM_LPF_NUM 3 44#define PDM_F2_CTRL 0x10 45#define PDM_F3_CTRL 0x14 46#define PDM_HPF_CTRL 0x18 47#define PDM_HPF_SFT_STEPS_MASK GENMASK(20, 16) 48#define PDM_HPF_SFT_STEPS(x) ((x) << 16) 49#define PDM_HPF_OUT_FACTOR_MASK GENMASK(15, 0) 50#define PDM_HPF_OUT_FACTOR(x) ((x) << 0) 51#define PDM_CHAN_CTRL 0x1c 52#define PDM_CHAN_CTRL_POINTER_WIDTH 8 53#define PDM_CHAN_CTRL_POINTER_MAX ((1 << PDM_CHAN_CTRL_POINTER_WIDTH) - 1) 54#define PDM_CHAN_CTRL_NUM 4 55#define PDM_CHAN_CTRL1 0x20 56#define PDM_COEFF_ADDR 0x24 57#define PDM_COEFF_DATA 0x28 58#define PDM_CLKG_CTRL 0x2c 59#define PDM_STS 0x30 60 61struct axg_pdm_lpf { 62 unsigned int ds; 63 unsigned int round_mode; 64 const unsigned int *tap; 65 unsigned int tap_num; 66}; 67 68struct axg_pdm_hcic { 69 unsigned int shift; 70 unsigned int mult; 71 unsigned int steps; 72 unsigned int ds; 73}; 74 75struct axg_pdm_hpf { 76 unsigned int out_factor; 77 unsigned int steps; 78}; 79 80struct axg_pdm_filters { 81 struct axg_pdm_hcic hcic; 82 struct axg_pdm_hpf hpf; 83 struct axg_pdm_lpf lpf[PDM_LPF_NUM]; 84}; 85 86struct axg_pdm_cfg { 87 const struct axg_pdm_filters *filters; 88 unsigned int sys_rate; 89}; 90 91struct axg_pdm { 92 const struct axg_pdm_cfg *cfg; 93 struct regmap *map; 94 struct clk *dclk; 95 struct clk *sysclk; 96 struct clk *pclk; 97}; 98 99static void axg_pdm_enable(struct regmap *map) 100{ 101 /* Reset AFIFO */ 102 regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, PDM_CTRL_RST_FIFO); 103 regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, 0); 104 105 /* Enable PDM */ 106 regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, PDM_CTRL_EN); 107} 108 109static void axg_pdm_disable(struct regmap *map) 110{ 111 regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, 0); 112} 113 114static void axg_pdm_filters_enable(struct regmap *map, bool enable) 115{ 116 unsigned int val = enable ? PDM_FILTER_EN : 0; 117 118 regmap_update_bits(map, PDM_HCIC_CTRL1, PDM_FILTER_EN, val); 119 regmap_update_bits(map, PDM_F1_CTRL, PDM_FILTER_EN, val); 120 regmap_update_bits(map, PDM_F2_CTRL, PDM_FILTER_EN, val); 121 regmap_update_bits(map, PDM_F3_CTRL, PDM_FILTER_EN, val); 122 regmap_update_bits(map, PDM_HPF_CTRL, PDM_FILTER_EN, val); 123} 124 125static int axg_pdm_trigger(struct snd_pcm_substream *substream, int cmd, 126 struct snd_soc_dai *dai) 127{ 128 struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); 129 130 switch (cmd) { 131 case SNDRV_PCM_TRIGGER_START: 132 case SNDRV_PCM_TRIGGER_RESUME: 133 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 134 axg_pdm_enable(priv->map); 135 return 0; 136 137 case SNDRV_PCM_TRIGGER_STOP: 138 case SNDRV_PCM_TRIGGER_SUSPEND: 139 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 140 axg_pdm_disable(priv->map); 141 return 0; 142 143 default: 144 return -EINVAL; 145 } 146} 147 148static unsigned int axg_pdm_get_os(struct axg_pdm *priv) 149{ 150 const struct axg_pdm_filters *filters = priv->cfg->filters; 151 unsigned int os = filters->hcic.ds; 152 int i; 153 154 /* 155 * The global oversampling factor is defined by the down sampling 156 * factor applied by each filter (HCIC and LPFs) 157 */ 158 159 for (i = 0; i < PDM_LPF_NUM; i++) 160 os *= filters->lpf[i].ds; 161 162 return os; 163} 164 165static int axg_pdm_set_sysclk(struct axg_pdm *priv, unsigned int os, 166 unsigned int rate) 167{ 168 unsigned int sys_rate = os * 2 * rate * PDM_CHAN_CTRL_POINTER_MAX; 169 170 /* 171 * Set the default system clock rate unless it is too fast for 172 * for the requested sample rate. In this case, the sample pointer 173 * counter could overflow so set a lower system clock rate 174 */ 175 if (sys_rate < priv->cfg->sys_rate) 176 return clk_set_rate(priv->sysclk, sys_rate); 177 178 return clk_set_rate(priv->sysclk, priv->cfg->sys_rate); 179} 180 181static int axg_pdm_set_sample_pointer(struct axg_pdm *priv) 182{ 183 unsigned int spmax, sp, val; 184 int i; 185 186 /* Max sample counter value per half period of dclk */ 187 spmax = DIV_ROUND_UP_ULL((u64)clk_get_rate(priv->sysclk), 188 clk_get_rate(priv->dclk) * 2); 189 190 /* Check if sysclk is not too fast - should not happen */ 191 if (WARN_ON(spmax > PDM_CHAN_CTRL_POINTER_MAX)) 192 return -EINVAL; 193 194 /* Capture the data when we are at 75% of the half period */ 195 sp = spmax * 3 / 4; 196 197 for (i = 0, val = 0; i < PDM_CHAN_CTRL_NUM; i++) 198 val |= sp << (PDM_CHAN_CTRL_POINTER_WIDTH * i); 199 200 regmap_write(priv->map, PDM_CHAN_CTRL, val); 201 regmap_write(priv->map, PDM_CHAN_CTRL1, val); 202 203 return 0; 204} 205 206static void axg_pdm_set_channel_mask(struct axg_pdm *priv, 207 unsigned int channels) 208{ 209 unsigned int mask = GENMASK(channels - 1, 0); 210 211 /* Put all channel in reset */ 212 regmap_update_bits(priv->map, PDM_CTRL, 213 PDM_CTRL_CHAN_RSTN_MASK, 0); 214 215 /* Take the necessary channels out of reset and enable them */ 216 regmap_update_bits(priv->map, PDM_CTRL, 217 PDM_CTRL_CHAN_RSTN_MASK | 218 PDM_CTRL_CHAN_EN_MASK, 219 PDM_CTRL_CHAN_RSTN(mask) | 220 PDM_CTRL_CHAN_EN(mask)); 221} 222 223static int axg_pdm_hw_params(struct snd_pcm_substream *substream, 224 struct snd_pcm_hw_params *params, 225 struct snd_soc_dai *dai) 226{ 227 struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); 228 unsigned int os = axg_pdm_get_os(priv); 229 unsigned int rate = params_rate(params); 230 unsigned int val; 231 int ret; 232 233 switch (params_width(params)) { 234 case 24: 235 val = PDM_CTRL_OUT_MODE; 236 break; 237 case 32: 238 val = 0; 239 break; 240 default: 241 dev_err(dai->dev, "unsupported sample width\n"); 242 return -EINVAL; 243 } 244 245 regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_OUT_MODE, val); 246 247 ret = axg_pdm_set_sysclk(priv, os, rate); 248 if (ret) { 249 dev_err(dai->dev, "failed to set system clock\n"); 250 return ret; 251 } 252 253 ret = clk_set_rate(priv->dclk, rate * os); 254 if (ret) { 255 dev_err(dai->dev, "failed to set dclk\n"); 256 return ret; 257 } 258 259 ret = axg_pdm_set_sample_pointer(priv); 260 if (ret) { 261 dev_err(dai->dev, "invalid clock setting\n"); 262 return ret; 263 } 264 265 axg_pdm_set_channel_mask(priv, params_channels(params)); 266 267 return 0; 268} 269 270static int axg_pdm_startup(struct snd_pcm_substream *substream, 271 struct snd_soc_dai *dai) 272{ 273 struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); 274 int ret; 275 276 ret = clk_prepare_enable(priv->dclk); 277 if (ret) { 278 dev_err(dai->dev, "enabling dclk failed\n"); 279 return ret; 280 } 281 282 /* Enable the filters */ 283 axg_pdm_filters_enable(priv->map, true); 284 285 return ret; 286} 287 288static void axg_pdm_shutdown(struct snd_pcm_substream *substream, 289 struct snd_soc_dai *dai) 290{ 291 struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); 292 293 axg_pdm_filters_enable(priv->map, false); 294 clk_disable_unprepare(priv->dclk); 295} 296 297static const struct snd_soc_dai_ops axg_pdm_dai_ops = { 298 .trigger = axg_pdm_trigger, 299 .hw_params = axg_pdm_hw_params, 300 .startup = axg_pdm_startup, 301 .shutdown = axg_pdm_shutdown, 302}; 303 304static void axg_pdm_set_hcic_ctrl(struct axg_pdm *priv) 305{ 306 const struct axg_pdm_hcic *hcic = &priv->cfg->filters->hcic; 307 unsigned int val; 308 309 val = PDM_HCIC_CTRL1_STAGE_NUM(hcic->steps); 310 val |= PDM_HCIC_CTRL1_DSR(hcic->ds); 311 val |= PDM_HCIC_CTRL1_GAIN_MULT(hcic->mult); 312 val |= PDM_HCIC_CTRL1_GAIN_SFT(hcic->shift); 313 314 regmap_update_bits(priv->map, PDM_HCIC_CTRL1, 315 PDM_HCIC_CTRL1_STAGE_NUM_MASK | 316 PDM_HCIC_CTRL1_DSR_MASK | 317 PDM_HCIC_CTRL1_GAIN_MULT_MASK | 318 PDM_HCIC_CTRL1_GAIN_SFT_MASK, 319 val); 320} 321 322static void axg_pdm_set_lpf_ctrl(struct axg_pdm *priv, unsigned int index) 323{ 324 const struct axg_pdm_lpf *lpf = &priv->cfg->filters->lpf[index]; 325 unsigned int offset = index * regmap_get_reg_stride(priv->map) 326 + PDM_F1_CTRL; 327 unsigned int val; 328 329 val = PDM_LPF_STAGE_NUM(lpf->tap_num); 330 val |= PDM_LPF_DSR(lpf->ds); 331 val |= PDM_LPF_ROUND_MODE(lpf->round_mode); 332 333 regmap_update_bits(priv->map, offset, 334 PDM_LPF_STAGE_NUM_MASK | 335 PDM_LPF_DSR_MASK | 336 PDM_LPF_ROUND_MODE_MASK, 337 val); 338} 339 340static void axg_pdm_set_hpf_ctrl(struct axg_pdm *priv) 341{ 342 const struct axg_pdm_hpf *hpf = &priv->cfg->filters->hpf; 343 unsigned int val; 344 345 val = PDM_HPF_OUT_FACTOR(hpf->out_factor); 346 val |= PDM_HPF_SFT_STEPS(hpf->steps); 347 348 regmap_update_bits(priv->map, PDM_HPF_CTRL, 349 PDM_HPF_OUT_FACTOR_MASK | 350 PDM_HPF_SFT_STEPS_MASK, 351 val); 352} 353 354static int axg_pdm_set_lpf_filters(struct axg_pdm *priv) 355{ 356 const struct axg_pdm_lpf *lpf = priv->cfg->filters->lpf; 357 unsigned int count = 0; 358 int i, j; 359 360 for (i = 0; i < PDM_LPF_NUM; i++) 361 count += lpf[i].tap_num; 362 363 /* Make sure the coeffs fit in the memory */ 364 if (count >= PDM_LPF_MAX_STAGE) 365 return -EINVAL; 366 367 /* Set the initial APB bus register address */ 368 regmap_write(priv->map, PDM_COEFF_ADDR, 0); 369 370 /* Set the tap filter values of all 3 filters */ 371 for (i = 0; i < PDM_LPF_NUM; i++) { 372 axg_pdm_set_lpf_ctrl(priv, i); 373 374 for (j = 0; j < lpf[i].tap_num; j++) 375 regmap_write(priv->map, PDM_COEFF_DATA, lpf[i].tap[j]); 376 } 377 378 return 0; 379} 380 381static int axg_pdm_dai_probe(struct snd_soc_dai *dai) 382{ 383 struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); 384 int ret; 385 386 ret = clk_prepare_enable(priv->pclk); 387 if (ret) { 388 dev_err(dai->dev, "enabling pclk failed\n"); 389 return ret; 390 } 391 392 /* 393 * sysclk must be set and enabled as well to access the pdm registers 394 * Accessing the register w/o it will give a bus error. 395 */ 396 ret = clk_set_rate(priv->sysclk, priv->cfg->sys_rate); 397 if (ret) { 398 dev_err(dai->dev, "setting sysclk failed\n"); 399 goto err_pclk; 400 } 401 402 ret = clk_prepare_enable(priv->sysclk); 403 if (ret) { 404 dev_err(dai->dev, "enabling sysclk failed\n"); 405 goto err_pclk; 406 } 407 408 /* Make sure the device is initially disabled */ 409 axg_pdm_disable(priv->map); 410 411 /* Make sure filter bypass is disabled */ 412 regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_BYPASS_MODE, 0); 413 414 /* Load filter settings */ 415 axg_pdm_set_hcic_ctrl(priv); 416 axg_pdm_set_hpf_ctrl(priv); 417 418 ret = axg_pdm_set_lpf_filters(priv); 419 if (ret) { 420 dev_err(dai->dev, "invalid filter configuration\n"); 421 goto err_sysclk; 422 } 423 424 return 0; 425 426err_sysclk: 427 clk_disable_unprepare(priv->sysclk); 428err_pclk: 429 clk_disable_unprepare(priv->pclk); 430 return ret; 431} 432 433static int axg_pdm_dai_remove(struct snd_soc_dai *dai) 434{ 435 struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai); 436 437 clk_disable_unprepare(priv->sysclk); 438 clk_disable_unprepare(priv->pclk); 439 440 return 0; 441} 442 443static struct snd_soc_dai_driver axg_pdm_dai_drv = { 444 .name = "PDM", 445 .capture = { 446 .stream_name = "Capture", 447 .channels_min = 1, 448 .channels_max = 8, 449 .rates = SNDRV_PCM_RATE_CONTINUOUS, 450 .rate_min = 5512, 451 .rate_max = 48000, 452 .formats = (SNDRV_PCM_FMTBIT_S24_LE | 453 SNDRV_PCM_FMTBIT_S32_LE), 454 }, 455 .ops = &axg_pdm_dai_ops, 456 .probe = axg_pdm_dai_probe, 457 .remove = axg_pdm_dai_remove, 458}; 459 460static const struct snd_soc_component_driver axg_pdm_component_drv = {}; 461 462static const struct regmap_config axg_pdm_regmap_cfg = { 463 .reg_bits = 32, 464 .val_bits = 32, 465 .reg_stride = 4, 466 .max_register = PDM_STS, 467}; 468 469static const unsigned int lpf1_default_tap[] = { 470 0x000014, 0xffffb2, 0xfffed9, 0xfffdce, 0xfffd45, 471 0xfffe32, 0x000147, 0x000645, 0x000b86, 0x000e21, 472 0x000ae3, 0x000000, 0xffeece, 0xffdca8, 0xffd212, 473 0xffd7d1, 0xfff2a7, 0x001f4c, 0x0050c2, 0x0072aa, 474 0x006ff1, 0x003c32, 0xffdc4e, 0xff6a18, 0xff0fef, 475 0xfefbaf, 0xff4c40, 0x000000, 0x00ebc8, 0x01c077, 476 0x02209e, 0x01c1a4, 0x008e60, 0xfebe52, 0xfcd690, 477 0xfb8fa5, 0xfba498, 0xfd9812, 0x0181ce, 0x06f5f3, 478 0x0d112f, 0x12a958, 0x169686, 0x18000e, 0x169686, 479 0x12a958, 0x0d112f, 0x06f5f3, 0x0181ce, 0xfd9812, 480 0xfba498, 0xfb8fa5, 0xfcd690, 0xfebe52, 0x008e60, 481 0x01c1a4, 0x02209e, 0x01c077, 0x00ebc8, 0x000000, 482 0xff4c40, 0xfefbaf, 0xff0fef, 0xff6a18, 0xffdc4e, 483 0x003c32, 0x006ff1, 0x0072aa, 0x0050c2, 0x001f4c, 484 0xfff2a7, 0xffd7d1, 0xffd212, 0xffdca8, 0xffeece, 485 0x000000, 0x000ae3, 0x000e21, 0x000b86, 0x000645, 486 0x000147, 0xfffe32, 0xfffd45, 0xfffdce, 0xfffed9, 487 0xffffb2, 0x000014, 488}; 489 490static const unsigned int lpf2_default_tap[] = { 491 0x00050a, 0xfff004, 0x0002c1, 0x003c12, 0xffa818, 492 0xffc87d, 0x010aef, 0xff5223, 0xfebd93, 0x028f41, 493 0xff5c0e, 0xfc63f8, 0x055f81, 0x000000, 0xf478a0, 494 0x11c5e3, 0x2ea74d, 0x11c5e3, 0xf478a0, 0x000000, 495 0x055f81, 0xfc63f8, 0xff5c0e, 0x028f41, 0xfebd93, 496 0xff5223, 0x010aef, 0xffc87d, 0xffa818, 0x003c12, 497 0x0002c1, 0xfff004, 0x00050a, 498}; 499 500static const unsigned int lpf3_default_tap[] = { 501 0x000000, 0x000081, 0x000000, 0xfffedb, 0x000000, 502 0x00022d, 0x000000, 0xfffc46, 0x000000, 0x0005f7, 503 0x000000, 0xfff6eb, 0x000000, 0x000d4e, 0x000000, 504 0xffed1e, 0x000000, 0x001a1c, 0x000000, 0xffdcb0, 505 0x000000, 0x002ede, 0x000000, 0xffc2d1, 0x000000, 506 0x004ebe, 0x000000, 0xff9beb, 0x000000, 0x007dd7, 507 0x000000, 0xff633a, 0x000000, 0x00c1d2, 0x000000, 508 0xff11d5, 0x000000, 0x012368, 0x000000, 0xfe9c45, 509 0x000000, 0x01b252, 0x000000, 0xfdebf6, 0x000000, 510 0x0290b8, 0x000000, 0xfcca0d, 0x000000, 0x041d7c, 511 0x000000, 0xfa8152, 0x000000, 0x07e9c6, 0x000000, 512 0xf28fb5, 0x000000, 0x28b216, 0x3fffde, 0x28b216, 513 0x000000, 0xf28fb5, 0x000000, 0x07e9c6, 0x000000, 514 0xfa8152, 0x000000, 0x041d7c, 0x000000, 0xfcca0d, 515 0x000000, 0x0290b8, 0x000000, 0xfdebf6, 0x000000, 516 0x01b252, 0x000000, 0xfe9c45, 0x000000, 0x012368, 517 0x000000, 0xff11d5, 0x000000, 0x00c1d2, 0x000000, 518 0xff633a, 0x000000, 0x007dd7, 0x000000, 0xff9beb, 519 0x000000, 0x004ebe, 0x000000, 0xffc2d1, 0x000000, 520 0x002ede, 0x000000, 0xffdcb0, 0x000000, 0x001a1c, 521 0x000000, 0xffed1e, 0x000000, 0x000d4e, 0x000000, 522 0xfff6eb, 0x000000, 0x0005f7, 0x000000, 0xfffc46, 523 0x000000, 0x00022d, 0x000000, 0xfffedb, 0x000000, 524 0x000081, 0x000000, 525}; 526 527/* 528 * These values are sane defaults for the axg platform: 529 * - OS = 64 530 * - Latency = 38700 (?) 531 * 532 * TODO: There is a lot of different HCIC, LPFs and HPF configurations possible. 533 * the configuration may depend on the dmic used by the platform, the 534 * expected tradeoff between latency and quality, etc ... If/When other 535 * settings are required, we should add a fw interface to this driver to 536 * load new filter settings. 537 */ 538static const struct axg_pdm_filters axg_default_filters = { 539 .hcic = { 540 .shift = 0x15, 541 .mult = 0x80, 542 .steps = 7, 543 .ds = 8, 544 }, 545 .hpf = { 546 .out_factor = 0x8000, 547 .steps = 13, 548 }, 549 .lpf = { 550 [0] = { 551 .ds = 2, 552 .round_mode = 1, 553 .tap = lpf1_default_tap, 554 .tap_num = ARRAY_SIZE(lpf1_default_tap), 555 }, 556 [1] = { 557 .ds = 2, 558 .round_mode = 0, 559 .tap = lpf2_default_tap, 560 .tap_num = ARRAY_SIZE(lpf2_default_tap), 561 }, 562 [2] = { 563 .ds = 2, 564 .round_mode = 1, 565 .tap = lpf3_default_tap, 566 .tap_num = ARRAY_SIZE(lpf3_default_tap) 567 }, 568 }, 569}; 570 571static const struct axg_pdm_cfg axg_pdm_config = { 572 .filters = &axg_default_filters, 573 .sys_rate = 250000000, 574}; 575 576static const struct of_device_id axg_pdm_of_match[] = { 577 { 578 .compatible = "amlogic,axg-pdm", 579 .data = &axg_pdm_config, 580 }, {} 581}; 582MODULE_DEVICE_TABLE(of, axg_pdm_of_match); 583 584static int axg_pdm_probe(struct platform_device *pdev) 585{ 586 struct device *dev = &pdev->dev; 587 struct axg_pdm *priv; 588 void __iomem *regs; 589 int ret; 590 591 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 592 if (!priv) 593 return -ENOMEM; 594 platform_set_drvdata(pdev, priv); 595 596 priv->cfg = of_device_get_match_data(dev); 597 if (!priv->cfg) { 598 dev_err(dev, "failed to match device\n"); 599 return -ENODEV; 600 } 601 602 regs = devm_platform_ioremap_resource(pdev, 0); 603 if (IS_ERR(regs)) 604 return PTR_ERR(regs); 605 606 priv->map = devm_regmap_init_mmio(dev, regs, &axg_pdm_regmap_cfg); 607 if (IS_ERR(priv->map)) { 608 dev_err(dev, "failed to init regmap: %ld\n", 609 PTR_ERR(priv->map)); 610 return PTR_ERR(priv->map); 611 } 612 613 priv->pclk = devm_clk_get(dev, "pclk"); 614 if (IS_ERR(priv->pclk)) { 615 ret = PTR_ERR(priv->pclk); 616 if (ret != -EPROBE_DEFER) 617 dev_err(dev, "failed to get pclk: %d\n", ret); 618 return ret; 619 } 620 621 priv->dclk = devm_clk_get(dev, "dclk"); 622 if (IS_ERR(priv->dclk)) { 623 ret = PTR_ERR(priv->dclk); 624 if (ret != -EPROBE_DEFER) 625 dev_err(dev, "failed to get dclk: %d\n", ret); 626 return ret; 627 } 628 629 priv->sysclk = devm_clk_get(dev, "sysclk"); 630 if (IS_ERR(priv->sysclk)) { 631 ret = PTR_ERR(priv->sysclk); 632 if (ret != -EPROBE_DEFER) 633 dev_err(dev, "failed to get dclk: %d\n", ret); 634 return ret; 635 } 636 637 return devm_snd_soc_register_component(dev, &axg_pdm_component_drv, 638 &axg_pdm_dai_drv, 1); 639} 640 641static struct platform_driver axg_pdm_pdrv = { 642 .probe = axg_pdm_probe, 643 .driver = { 644 .name = "axg-pdm", 645 .of_match_table = axg_pdm_of_match, 646 }, 647}; 648module_platform_driver(axg_pdm_pdrv); 649 650MODULE_DESCRIPTION("Amlogic AXG PDM Input driver"); 651MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 652MODULE_LICENSE("GPL v2"); 653