1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
6
7#ifndef _MESON_AXG_FIFO_H
8#define _MESON_AXG_FIFO_H
9
10struct clk;
11struct platform_device;
12struct reg_field;
13struct regmap;
14struct regmap_field;
15struct reset_control;
16
17struct snd_soc_component_driver;
18struct snd_soc_dai;
19struct snd_soc_dai_driver;
20
21struct snd_soc_pcm_runtime;
22
23#define AXG_FIFO_CH_MAX			128
24#define AXG_FIFO_RATES			(SNDRV_PCM_RATE_5512 |		\
25					 SNDRV_PCM_RATE_8000_192000)
26#define AXG_FIFO_FORMATS		(SNDRV_PCM_FMTBIT_S8 |		\
27					 SNDRV_PCM_FMTBIT_S16_LE |	\
28					 SNDRV_PCM_FMTBIT_S20_LE |	\
29					 SNDRV_PCM_FMTBIT_S24_LE |	\
30					 SNDRV_PCM_FMTBIT_S32_LE |	\
31					 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
32
33#define AXG_FIFO_BURST			8
34
35#define FIFO_INT_ADDR_FINISH		BIT(0)
36#define FIFO_INT_ADDR_INT		BIT(1)
37#define FIFO_INT_COUNT_REPEAT		BIT(2)
38#define FIFO_INT_COUNT_ONCE		BIT(3)
39#define FIFO_INT_FIFO_ZERO		BIT(4)
40#define FIFO_INT_FIFO_DEPTH		BIT(5)
41#define FIFO_INT_MASK			GENMASK(7, 0)
42
43#define FIFO_CTRL0			0x00
44#define  CTRL0_DMA_EN			BIT(31)
45#define  CTRL0_INT_EN(x)		((x) << 16)
46#define  CTRL0_SEL_MASK			GENMASK(2, 0)
47#define  CTRL0_SEL_SHIFT		0
48#define FIFO_CTRL1			0x04
49#define  CTRL1_INT_CLR(x)		((x) << 0)
50#define  CTRL1_STATUS2_SEL_MASK		GENMASK(11, 8)
51#define  CTRL1_STATUS2_SEL(x)		((x) << 8)
52#define   STATUS2_SEL_DDR_READ		0
53#define  CTRL1_FRDDR_DEPTH_MASK		GENMASK(31, 24)
54#define  CTRL1_FRDDR_DEPTH(x)		((x) << 24)
55#define FIFO_START_ADDR			0x08
56#define FIFO_FINISH_ADDR		0x0c
57#define FIFO_INT_ADDR			0x10
58#define FIFO_STATUS1			0x14
59#define  STATUS1_INT_STS(x)		((x) << 0)
60#define FIFO_STATUS2			0x18
61#define FIFO_INIT_ADDR			0x24
62#define FIFO_CTRL2			0x28
63
64struct axg_fifo {
65	struct regmap *map;
66	struct clk *pclk;
67	struct reset_control *arb;
68	struct regmap_field *field_threshold;
69	unsigned int depth;
70	int irq;
71};
72
73struct axg_fifo_match_data {
74	const struct snd_soc_component_driver *component_drv;
75	struct snd_soc_dai_driver *dai_drv;
76	struct reg_field field_threshold;
77};
78
79int axg_fifo_pcm_open(struct snd_soc_component *component,
80		      struct snd_pcm_substream *ss);
81int axg_fifo_pcm_close(struct snd_soc_component *component,
82		       struct snd_pcm_substream *ss);
83int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
84			   struct snd_pcm_substream *ss,
85			   struct snd_pcm_hw_params *params);
86int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,
87			    struct snd_pcm_substream *ss,
88			    struct snd_pcm_hw_params *params);
89int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
90			 struct snd_pcm_substream *ss);
91snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,
92				       struct snd_pcm_substream *ss);
93int axg_fifo_pcm_trigger(struct snd_soc_component *component,
94			 struct snd_pcm_substream *ss, int cmd);
95
96int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type);
97int axg_fifo_probe(struct platform_device *pdev);
98
99#endif /* _MESON_AXG_FIFO_H */
100