1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * mt2701-reg.h -- Mediatek 2701 audio driver reg definition 4 * 5 * Copyright (c) 2016 MediaTek Inc. 6 * Author: Garlic Tseng <garlic.tseng@mediatek.com> 7 */ 8 9#ifndef _MT2701_REG_H_ 10#define _MT2701_REG_H_ 11 12#define AUDIO_TOP_CON0 0x0000 13#define AUDIO_TOP_CON4 0x0010 14#define AUDIO_TOP_CON5 0x0014 15#define AFE_DAIBT_CON0 0x001c 16#define AFE_MRGIF_CON 0x003c 17#define ASMI_TIMING_CON1 0x0100 18#define ASMO_TIMING_CON1 0x0104 19#define PWR1_ASM_CON1 0x0108 20#define ASYS_TOP_CON 0x0600 21#define ASYS_I2SIN1_CON 0x0604 22#define ASYS_I2SIN2_CON 0x0608 23#define ASYS_I2SIN3_CON 0x060c 24#define ASYS_I2SIN4_CON 0x0610 25#define ASYS_I2SIN5_CON 0x0614 26#define ASYS_I2SO1_CON 0x061C 27#define ASYS_I2SO2_CON 0x0620 28#define ASYS_I2SO3_CON 0x0624 29#define ASYS_I2SO4_CON 0x0628 30#define ASYS_I2SO5_CON 0x062c 31#define PWR2_TOP_CON 0x0634 32#define AFE_CONN0 0x06c0 33#define AFE_CONN1 0x06c4 34#define AFE_CONN2 0x06c8 35#define AFE_CONN3 0x06cc 36#define AFE_CONN14 0x06f8 37#define AFE_CONN15 0x06fc 38#define AFE_CONN16 0x0700 39#define AFE_CONN17 0x0704 40#define AFE_CONN18 0x0708 41#define AFE_CONN19 0x070c 42#define AFE_CONN20 0x0710 43#define AFE_CONN21 0x0714 44#define AFE_CONN22 0x0718 45#define AFE_CONN23 0x071c 46#define AFE_CONN24 0x0720 47#define AFE_CONN41 0x0764 48#define ASYS_IRQ1_CON 0x0780 49#define ASYS_IRQ2_CON 0x0784 50#define ASYS_IRQ3_CON 0x0788 51#define ASYS_IRQ_CLR 0x07c0 52#define ASYS_IRQ_STATUS 0x07c4 53#define PWR2_ASM_CON1 0x1070 54#define AFE_DAC_CON0 0x1200 55#define AFE_DAC_CON1 0x1204 56#define AFE_DAC_CON2 0x1208 57#define AFE_DAC_CON3 0x120c 58#define AFE_DAC_CON4 0x1210 59#define AFE_MEMIF_HD_CON1 0x121c 60#define AFE_MEMIF_PBUF_SIZE 0x1238 61#define AFE_MEMIF_HD_CON0 0x123c 62#define AFE_DL1_BASE 0x1240 63#define AFE_DL1_CUR 0x1244 64#define AFE_DL2_BASE 0x1250 65#define AFE_DL2_CUR 0x1254 66#define AFE_DL3_BASE 0x1260 67#define AFE_DL3_CUR 0x1264 68#define AFE_DL4_BASE 0x1270 69#define AFE_DL4_CUR 0x1274 70#define AFE_DL5_BASE 0x1280 71#define AFE_DL5_CUR 0x1284 72#define AFE_DLMCH_BASE 0x12a0 73#define AFE_DLMCH_CUR 0x12a4 74#define AFE_ARB1_BASE 0x12b0 75#define AFE_ARB1_CUR 0x12b4 76#define AFE_VUL_BASE 0x1300 77#define AFE_VUL_CUR 0x130c 78#define AFE_UL2_BASE 0x1310 79#define AFE_UL2_END 0x1318 80#define AFE_UL2_CUR 0x131c 81#define AFE_UL3_BASE 0x1320 82#define AFE_UL3_END 0x1328 83#define AFE_UL3_CUR 0x132c 84#define AFE_UL4_BASE 0x1330 85#define AFE_UL4_END 0x1338 86#define AFE_UL4_CUR 0x133c 87#define AFE_UL5_BASE 0x1340 88#define AFE_UL5_END 0x1348 89#define AFE_UL5_CUR 0x134c 90#define AFE_DAI_BASE 0x1370 91#define AFE_DAI_CUR 0x137c 92 93/* AFE_DAIBT_CON0 (0x001c) */ 94#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) 95#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) 96#define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3) 97#define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9) 98#define AFE_DAIBT_CON0_MRG_USE (0x1 << 12) 99 100/* PWR1_ASM_CON1 (0x0108) */ 101#define PWR1_ASM_CON1_INIT_VAL (0x492) 102 103/* AFE_MRGIF_CON (0x003c) */ 104#define AFE_MRGIF_CON_MRG_EN (0x1 << 0) 105#define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16) 106#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) 107#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) 108 109/* ASYS_TOP_CON (0x0600) */ 110#define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0) 111 112/* PWR2_ASM_CON1 (0x1070) */ 113#define PWR2_ASM_CON1_INIT_VAL (0x492492) 114 115/* AFE_DAC_CON0 (0x1200) */ 116#define AFE_DAC_CON0_AFE_ON (0x1 << 0) 117 118/* AFE_MEMIF_PBUF_SIZE (0x1238) */ 119#define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29) 120#define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29) 121#define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29) 122#define DLMCH_BIT_WIDTH_MASK (0x1 << 28) 123#define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK (0xf << 24) 124#define AFE_MEMIF_PBUF_SIZE_DLM_CH(x) ((x) << 24) 125#define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12) 126#define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12) 127 128/* I2S in/out register bit control */ 129#define ASYS_I2S_CON_FS (0x1f << 8) 130#define ASYS_I2S_CON_FS_SET(x) ((x) << 8) 131#define ASYS_I2S_CON_RESET (0x1 << 30) 132#define ASYS_I2S_CON_I2S_EN (0x1 << 0) 133#define ASYS_I2S_CON_ONE_HEART_MODE (0x1 << 16) 134#define ASYS_I2S_CON_I2S_COUPLE_MODE (0x1 << 17) 135/* 0:EIAJ 1:I2S */ 136#define ASYS_I2S_CON_I2S_MODE (0x1 << 3) 137#define ASYS_I2S_CON_WIDE_MODE (0x1 << 1) 138#define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) 139#define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) 140 141#endif 142