18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * mt2701-afe-clock-ctrl.h -- Mediatek 2701 afe clock ctrl definition 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (c) 2016 MediaTek Inc. 68c2ecf20Sopenharmony_ci * Author: Garlic Tseng <garlic.tseng@mediatek.com> 78c2ecf20Sopenharmony_ci * Ryder Lee <ryder.lee@mediatek.com> 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#ifndef _MT2701_AFE_CLOCK_CTRL_H_ 118c2ecf20Sopenharmony_ci#define _MT2701_AFE_CLOCK_CTRL_H_ 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_cistruct mtk_base_afe; 148c2ecf20Sopenharmony_cistruct mt2701_i2s_path; 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciint mt2701_init_clock(struct mtk_base_afe *afe); 178c2ecf20Sopenharmony_ciint mt2701_afe_enable_clock(struct mtk_base_afe *afe); 188c2ecf20Sopenharmony_ciint mt2701_afe_disable_clock(struct mtk_base_afe *afe); 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciint mt2701_afe_enable_i2s(struct mtk_base_afe *afe, 218c2ecf20Sopenharmony_ci struct mt2701_i2s_path *path, 228c2ecf20Sopenharmony_ci int dir); 238c2ecf20Sopenharmony_civoid mt2701_afe_disable_i2s(struct mtk_base_afe *afe, 248c2ecf20Sopenharmony_ci struct mt2701_i2s_path *path, 258c2ecf20Sopenharmony_ci int dir); 268c2ecf20Sopenharmony_ciint mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id); 278c2ecf20Sopenharmony_civoid mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id); 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ciint mt2701_enable_btmrg_clk(struct mtk_base_afe *afe); 308c2ecf20Sopenharmony_civoid mt2701_disable_btmrg_clk(struct mtk_base_afe *afe); 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ciint mt2701_mclk_configuration(struct mtk_base_afe *afe, int id); 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci#endif 35