18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci *  skl-ssp-clk.h - Skylake ssp clock information and ipc structure
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci *  Copyright (C) 2017 Intel Corp
68c2ecf20Sopenharmony_ci *  Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
78c2ecf20Sopenharmony_ci *  Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
88c2ecf20Sopenharmony_ci *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
98c2ecf20Sopenharmony_ci *
108c2ecf20Sopenharmony_ci * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
118c2ecf20Sopenharmony_ci */
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci#ifndef SOUND_SOC_SKL_SSP_CLK_H
148c2ecf20Sopenharmony_ci#define SOUND_SOC_SKL_SSP_CLK_H
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci#define SKL_MAX_SSP		6
178c2ecf20Sopenharmony_ci/* xtal/cardinal/pll, parent of ssp clocks and mclk */
188c2ecf20Sopenharmony_ci#define SKL_MAX_CLK_SRC		3
198c2ecf20Sopenharmony_ci#define SKL_MAX_SSP_CLK_TYPES	3 /* mclk, sclk, sclkfs */
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci#define SKL_MAX_CLK_CNT		(SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES)
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci/* Max number of configurations supported for each clock */
248c2ecf20Sopenharmony_ci#define SKL_MAX_CLK_RATES	10
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci#define SKL_SCLK_OFS		SKL_MAX_SSP
278c2ecf20Sopenharmony_ci#define SKL_SCLKFS_OFS		(SKL_SCLK_OFS + SKL_MAX_SSP)
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_cienum skl_clk_type {
308c2ecf20Sopenharmony_ci	SKL_MCLK,
318c2ecf20Sopenharmony_ci	SKL_SCLK,
328c2ecf20Sopenharmony_ci	SKL_SCLK_FS,
338c2ecf20Sopenharmony_ci};
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_cienum skl_clk_src_type {
368c2ecf20Sopenharmony_ci	SKL_XTAL,
378c2ecf20Sopenharmony_ci	SKL_CARDINAL,
388c2ecf20Sopenharmony_ci	SKL_PLL,
398c2ecf20Sopenharmony_ci};
408c2ecf20Sopenharmony_ci
418c2ecf20Sopenharmony_cistruct skl_clk_parent_src {
428c2ecf20Sopenharmony_ci	u8 clk_id;
438c2ecf20Sopenharmony_ci	const char *name;
448c2ecf20Sopenharmony_ci	unsigned long rate;
458c2ecf20Sopenharmony_ci	const char *parent_name;
468c2ecf20Sopenharmony_ci};
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_cistruct skl_tlv_hdr {
498c2ecf20Sopenharmony_ci	u32 type;
508c2ecf20Sopenharmony_ci	u32 size;
518c2ecf20Sopenharmony_ci};
528c2ecf20Sopenharmony_ci
538c2ecf20Sopenharmony_cistruct skl_dmactrl_mclk_cfg {
548c2ecf20Sopenharmony_ci	struct skl_tlv_hdr hdr;
558c2ecf20Sopenharmony_ci	/* DMA Clk TLV params */
568c2ecf20Sopenharmony_ci	u32 clk_warm_up:16;
578c2ecf20Sopenharmony_ci	u32 mclk:1;
588c2ecf20Sopenharmony_ci	u32 warm_up_over:1;
598c2ecf20Sopenharmony_ci	u32 rsvd0:14;
608c2ecf20Sopenharmony_ci	u32 clk_stop_delay:16;
618c2ecf20Sopenharmony_ci	u32 keep_running:1;
628c2ecf20Sopenharmony_ci	u32 clk_stop_over:1;
638c2ecf20Sopenharmony_ci	u32 rsvd1:14;
648c2ecf20Sopenharmony_ci};
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_cistruct skl_dmactrl_sclkfs_cfg {
678c2ecf20Sopenharmony_ci	struct skl_tlv_hdr hdr;
688c2ecf20Sopenharmony_ci	/* DMA SClk&FS  TLV params */
698c2ecf20Sopenharmony_ci	u32 sampling_frequency;
708c2ecf20Sopenharmony_ci	u32 bit_depth;
718c2ecf20Sopenharmony_ci	u32 channel_map;
728c2ecf20Sopenharmony_ci	u32 channel_config;
738c2ecf20Sopenharmony_ci	u32 interleaving_style;
748c2ecf20Sopenharmony_ci	u32 number_of_channels : 8;
758c2ecf20Sopenharmony_ci	u32 valid_bit_depth : 8;
768c2ecf20Sopenharmony_ci	u32 sample_type : 8;
778c2ecf20Sopenharmony_ci	u32 reserved : 8;
788c2ecf20Sopenharmony_ci};
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_ciunion skl_clk_ctrl_ipc {
818c2ecf20Sopenharmony_ci	struct skl_dmactrl_mclk_cfg mclk;
828c2ecf20Sopenharmony_ci	struct skl_dmactrl_sclkfs_cfg sclk_fs;
838c2ecf20Sopenharmony_ci};
848c2ecf20Sopenharmony_ci
858c2ecf20Sopenharmony_cistruct skl_clk_rate_cfg_table {
868c2ecf20Sopenharmony_ci	unsigned long rate;
878c2ecf20Sopenharmony_ci	union skl_clk_ctrl_ipc dma_ctl_ipc;
888c2ecf20Sopenharmony_ci	void *config;
898c2ecf20Sopenharmony_ci};
908c2ecf20Sopenharmony_ci
918c2ecf20Sopenharmony_ci/*
928c2ecf20Sopenharmony_ci * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
938c2ecf20Sopenharmony_ci * all possible clocks ssp can generate for that platform.
948c2ecf20Sopenharmony_ci */
958c2ecf20Sopenharmony_cistruct skl_ssp_clk {
968c2ecf20Sopenharmony_ci	const char *name;
978c2ecf20Sopenharmony_ci	const char *parent_name;
988c2ecf20Sopenharmony_ci	struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES];
998c2ecf20Sopenharmony_ci};
1008c2ecf20Sopenharmony_ci
1018c2ecf20Sopenharmony_cistruct skl_clk_pdata {
1028c2ecf20Sopenharmony_ci	struct skl_clk_parent_src *parent_clks;
1038c2ecf20Sopenharmony_ci	int num_clks;
1048c2ecf20Sopenharmony_ci	struct skl_ssp_clk *ssp_clks;
1058c2ecf20Sopenharmony_ci	void *pvt_data;
1068c2ecf20Sopenharmony_ci};
1078c2ecf20Sopenharmony_ci
1088c2ecf20Sopenharmony_ci#endif /* SOUND_SOC_SKL_SSP_CLK_H */
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