1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * skl-message.c - HDA DSP interface for FW registration, Pipe and Module 4 * configurations 5 * 6 * Copyright (C) 2015 Intel Corp 7 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 8 * Jeeja KP <jeeja.kp@intel.com> 9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10 */ 11 12#include <linux/slab.h> 13#include <linux/pci.h> 14#include <sound/core.h> 15#include <sound/pcm.h> 16#include <uapi/sound/skl-tplg-interface.h> 17#include "skl-sst-dsp.h" 18#include "cnl-sst-dsp.h" 19#include "skl-sst-ipc.h" 20#include "skl.h" 21#include "../common/sst-dsp.h" 22#include "../common/sst-dsp-priv.h" 23#include "skl-topology.h" 24 25static int skl_alloc_dma_buf(struct device *dev, 26 struct snd_dma_buffer *dmab, size_t size) 27{ 28 return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dev, size, dmab); 29} 30 31static int skl_free_dma_buf(struct device *dev, struct snd_dma_buffer *dmab) 32{ 33 snd_dma_free_pages(dmab); 34 return 0; 35} 36 37#define SKL_ASTATE_PARAM_ID 4 38 39void skl_dsp_set_astate_cfg(struct skl_dev *skl, u32 cnt, void *data) 40{ 41 struct skl_ipc_large_config_msg msg = {0}; 42 43 msg.large_param_id = SKL_ASTATE_PARAM_ID; 44 msg.param_data_size = (cnt * sizeof(struct skl_astate_param) + 45 sizeof(cnt)); 46 47 skl_ipc_set_large_config(&skl->ipc, &msg, data); 48} 49 50static int skl_dsp_setup_spib(struct device *dev, unsigned int size, 51 int stream_tag, int enable) 52{ 53 struct hdac_bus *bus = dev_get_drvdata(dev); 54 struct hdac_stream *stream = snd_hdac_get_stream(bus, 55 SNDRV_PCM_STREAM_PLAYBACK, stream_tag); 56 struct hdac_ext_stream *estream; 57 58 if (!stream) 59 return -EINVAL; 60 61 estream = stream_to_hdac_ext_stream(stream); 62 /* enable/disable SPIB for this hdac stream */ 63 snd_hdac_ext_stream_spbcap_enable(bus, enable, stream->index); 64 65 /* set the spib value */ 66 snd_hdac_ext_stream_set_spib(bus, estream, size); 67 68 return 0; 69} 70 71static int skl_dsp_prepare(struct device *dev, unsigned int format, 72 unsigned int size, struct snd_dma_buffer *dmab) 73{ 74 struct hdac_bus *bus = dev_get_drvdata(dev); 75 struct hdac_ext_stream *estream; 76 struct hdac_stream *stream; 77 struct snd_pcm_substream substream; 78 int ret; 79 80 if (!bus) 81 return -ENODEV; 82 83 memset(&substream, 0, sizeof(substream)); 84 substream.stream = SNDRV_PCM_STREAM_PLAYBACK; 85 86 estream = snd_hdac_ext_stream_assign(bus, &substream, 87 HDAC_EXT_STREAM_TYPE_HOST); 88 if (!estream) 89 return -ENODEV; 90 91 stream = hdac_stream(estream); 92 93 /* assign decouple host dma channel */ 94 ret = snd_hdac_dsp_prepare(stream, format, size, dmab); 95 if (ret < 0) 96 return ret; 97 98 skl_dsp_setup_spib(dev, size, stream->stream_tag, true); 99 100 return stream->stream_tag; 101} 102 103static int skl_dsp_trigger(struct device *dev, bool start, int stream_tag) 104{ 105 struct hdac_bus *bus = dev_get_drvdata(dev); 106 struct hdac_stream *stream; 107 108 if (!bus) 109 return -ENODEV; 110 111 stream = snd_hdac_get_stream(bus, 112 SNDRV_PCM_STREAM_PLAYBACK, stream_tag); 113 if (!stream) 114 return -EINVAL; 115 116 snd_hdac_dsp_trigger(stream, start); 117 118 return 0; 119} 120 121static int skl_dsp_cleanup(struct device *dev, 122 struct snd_dma_buffer *dmab, int stream_tag) 123{ 124 struct hdac_bus *bus = dev_get_drvdata(dev); 125 struct hdac_stream *stream; 126 struct hdac_ext_stream *estream; 127 128 if (!bus) 129 return -ENODEV; 130 131 stream = snd_hdac_get_stream(bus, 132 SNDRV_PCM_STREAM_PLAYBACK, stream_tag); 133 if (!stream) 134 return -EINVAL; 135 136 estream = stream_to_hdac_ext_stream(stream); 137 skl_dsp_setup_spib(dev, 0, stream_tag, false); 138 snd_hdac_ext_stream_release(estream, HDAC_EXT_STREAM_TYPE_HOST); 139 140 snd_hdac_dsp_cleanup(stream, dmab); 141 142 return 0; 143} 144 145static struct skl_dsp_loader_ops skl_get_loader_ops(void) 146{ 147 struct skl_dsp_loader_ops loader_ops; 148 149 memset(&loader_ops, 0, sizeof(struct skl_dsp_loader_ops)); 150 151 loader_ops.alloc_dma_buf = skl_alloc_dma_buf; 152 loader_ops.free_dma_buf = skl_free_dma_buf; 153 154 return loader_ops; 155}; 156 157static struct skl_dsp_loader_ops bxt_get_loader_ops(void) 158{ 159 struct skl_dsp_loader_ops loader_ops; 160 161 memset(&loader_ops, 0, sizeof(loader_ops)); 162 163 loader_ops.alloc_dma_buf = skl_alloc_dma_buf; 164 loader_ops.free_dma_buf = skl_free_dma_buf; 165 loader_ops.prepare = skl_dsp_prepare; 166 loader_ops.trigger = skl_dsp_trigger; 167 loader_ops.cleanup = skl_dsp_cleanup; 168 169 return loader_ops; 170}; 171 172static const struct skl_dsp_ops dsp_ops[] = { 173 { 174 .id = 0x9d70, 175 .num_cores = 2, 176 .loader_ops = skl_get_loader_ops, 177 .init = skl_sst_dsp_init, 178 .init_fw = skl_sst_init_fw, 179 .cleanup = skl_sst_dsp_cleanup 180 }, 181 { 182 .id = 0x9d71, 183 .num_cores = 2, 184 .loader_ops = skl_get_loader_ops, 185 .init = skl_sst_dsp_init, 186 .init_fw = skl_sst_init_fw, 187 .cleanup = skl_sst_dsp_cleanup 188 }, 189 { 190 .id = 0x5a98, 191 .num_cores = 2, 192 .loader_ops = bxt_get_loader_ops, 193 .init = bxt_sst_dsp_init, 194 .init_fw = bxt_sst_init_fw, 195 .cleanup = bxt_sst_dsp_cleanup 196 }, 197 { 198 .id = 0x3198, 199 .num_cores = 2, 200 .loader_ops = bxt_get_loader_ops, 201 .init = bxt_sst_dsp_init, 202 .init_fw = bxt_sst_init_fw, 203 .cleanup = bxt_sst_dsp_cleanup 204 }, 205 { 206 .id = 0x9dc8, 207 .num_cores = 4, 208 .loader_ops = bxt_get_loader_ops, 209 .init = cnl_sst_dsp_init, 210 .init_fw = cnl_sst_init_fw, 211 .cleanup = cnl_sst_dsp_cleanup 212 }, 213 { 214 .id = 0xa348, 215 .num_cores = 4, 216 .loader_ops = bxt_get_loader_ops, 217 .init = cnl_sst_dsp_init, 218 .init_fw = cnl_sst_init_fw, 219 .cleanup = cnl_sst_dsp_cleanup 220 }, 221 { 222 .id = 0x02c8, 223 .num_cores = 4, 224 .loader_ops = bxt_get_loader_ops, 225 .init = cnl_sst_dsp_init, 226 .init_fw = cnl_sst_init_fw, 227 .cleanup = cnl_sst_dsp_cleanup 228 }, 229 { 230 .id = 0x06c8, 231 .num_cores = 4, 232 .loader_ops = bxt_get_loader_ops, 233 .init = cnl_sst_dsp_init, 234 .init_fw = cnl_sst_init_fw, 235 .cleanup = cnl_sst_dsp_cleanup 236 }, 237}; 238 239const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id) 240{ 241 int i; 242 243 for (i = 0; i < ARRAY_SIZE(dsp_ops); i++) { 244 if (dsp_ops[i].id == pci_id) 245 return &dsp_ops[i]; 246 } 247 248 return NULL; 249} 250 251int skl_init_dsp(struct skl_dev *skl) 252{ 253 void __iomem *mmio_base; 254 struct hdac_bus *bus = skl_to_bus(skl); 255 struct skl_dsp_loader_ops loader_ops; 256 int irq = bus->irq; 257 const struct skl_dsp_ops *ops; 258 struct skl_dsp_cores *cores; 259 int ret; 260 261 /* enable ppcap interrupt */ 262 snd_hdac_ext_bus_ppcap_enable(bus, true); 263 snd_hdac_ext_bus_ppcap_int_enable(bus, true); 264 265 /* read the BAR of the ADSP MMIO */ 266 mmio_base = pci_ioremap_bar(skl->pci, 4); 267 if (mmio_base == NULL) { 268 dev_err(bus->dev, "ioremap error\n"); 269 return -ENXIO; 270 } 271 272 ops = skl_get_dsp_ops(skl->pci->device); 273 if (!ops) { 274 ret = -EIO; 275 goto unmap_mmio; 276 } 277 278 loader_ops = ops->loader_ops(); 279 ret = ops->init(bus->dev, mmio_base, irq, 280 skl->fw_name, loader_ops, 281 &skl); 282 283 if (ret < 0) 284 goto unmap_mmio; 285 286 skl->dsp_ops = ops; 287 cores = &skl->cores; 288 cores->count = ops->num_cores; 289 290 cores->state = kcalloc(cores->count, sizeof(*cores->state), GFP_KERNEL); 291 if (!cores->state) { 292 ret = -ENOMEM; 293 goto unmap_mmio; 294 } 295 296 cores->usage_count = kcalloc(cores->count, sizeof(*cores->usage_count), 297 GFP_KERNEL); 298 if (!cores->usage_count) { 299 ret = -ENOMEM; 300 goto free_core_state; 301 } 302 303 dev_dbg(bus->dev, "dsp registration status=%d\n", ret); 304 305 return 0; 306 307free_core_state: 308 kfree(cores->state); 309 310unmap_mmio: 311 iounmap(mmio_base); 312 313 return ret; 314} 315 316int skl_free_dsp(struct skl_dev *skl) 317{ 318 struct hdac_bus *bus = skl_to_bus(skl); 319 320 /* disable ppcap interrupt */ 321 snd_hdac_ext_bus_ppcap_int_enable(bus, false); 322 323 skl->dsp_ops->cleanup(bus->dev, skl); 324 325 kfree(skl->cores.state); 326 kfree(skl->cores.usage_count); 327 328 if (skl->dsp->addr.lpe) 329 iounmap(skl->dsp->addr.lpe); 330 331 return 0; 332} 333 334/* 335 * In the case of "suspend_active" i.e, the Audio IP being active 336 * during system suspend, immediately excecute any pending D0i3 work 337 * before suspending. This is needed for the IP to work in low power 338 * mode during system suspend. In the case of normal suspend, cancel 339 * any pending D0i3 work. 340 */ 341int skl_suspend_late_dsp(struct skl_dev *skl) 342{ 343 struct delayed_work *dwork; 344 345 if (!skl) 346 return 0; 347 348 dwork = &skl->d0i3.work; 349 350 if (dwork->work.func) { 351 if (skl->supend_active) 352 flush_delayed_work(dwork); 353 else 354 cancel_delayed_work_sync(dwork); 355 } 356 357 return 0; 358} 359 360int skl_suspend_dsp(struct skl_dev *skl) 361{ 362 struct hdac_bus *bus = skl_to_bus(skl); 363 int ret; 364 365 /* if ppcap is not supported return 0 */ 366 if (!bus->ppcap) 367 return 0; 368 369 ret = skl_dsp_sleep(skl->dsp); 370 if (ret < 0) 371 return ret; 372 373 /* disable ppcap interrupt */ 374 snd_hdac_ext_bus_ppcap_int_enable(bus, false); 375 snd_hdac_ext_bus_ppcap_enable(bus, false); 376 377 return 0; 378} 379 380int skl_resume_dsp(struct skl_dev *skl) 381{ 382 struct hdac_bus *bus = skl_to_bus(skl); 383 int ret; 384 385 /* if ppcap is not supported return 0 */ 386 if (!bus->ppcap) 387 return 0; 388 389 /* enable ppcap interrupt */ 390 snd_hdac_ext_bus_ppcap_enable(bus, true); 391 snd_hdac_ext_bus_ppcap_int_enable(bus, true); 392 393 /* check if DSP 1st boot is done */ 394 if (skl->is_first_boot) 395 return 0; 396 397 /* 398 * Disable dynamic clock and power gating during firmware 399 * and library download 400 */ 401 skl->enable_miscbdcge(skl->dev, false); 402 skl->clock_power_gating(skl->dev, false); 403 404 ret = skl_dsp_wake(skl->dsp); 405 skl->enable_miscbdcge(skl->dev, true); 406 skl->clock_power_gating(skl->dev, true); 407 if (ret < 0) 408 return ret; 409 410 if (skl->cfg.astate_cfg != NULL) { 411 skl_dsp_set_astate_cfg(skl, skl->cfg.astate_cfg->count, 412 skl->cfg.astate_cfg); 413 } 414 return ret; 415} 416 417enum skl_bitdepth skl_get_bit_depth(int params) 418{ 419 switch (params) { 420 case 8: 421 return SKL_DEPTH_8BIT; 422 423 case 16: 424 return SKL_DEPTH_16BIT; 425 426 case 24: 427 return SKL_DEPTH_24BIT; 428 429 case 32: 430 return SKL_DEPTH_32BIT; 431 432 default: 433 return SKL_DEPTH_INVALID; 434 435 } 436} 437 438/* 439 * Each module in DSP expects a base module configuration, which consists of 440 * PCM format information, which we calculate in driver and resource values 441 * which are read from widget information passed through topology binary 442 * This is send when we create a module with INIT_INSTANCE IPC msg 443 */ 444static void skl_set_base_module_format(struct skl_dev *skl, 445 struct skl_module_cfg *mconfig, 446 struct skl_base_cfg *base_cfg) 447{ 448 struct skl_module *module = mconfig->module; 449 struct skl_module_res *res = &module->resources[mconfig->res_idx]; 450 struct skl_module_iface *fmt = &module->formats[mconfig->fmt_idx]; 451 struct skl_module_fmt *format = &fmt->inputs[0].fmt; 452 453 base_cfg->audio_fmt.number_of_channels = format->channels; 454 455 base_cfg->audio_fmt.s_freq = format->s_freq; 456 base_cfg->audio_fmt.bit_depth = format->bit_depth; 457 base_cfg->audio_fmt.valid_bit_depth = format->valid_bit_depth; 458 base_cfg->audio_fmt.ch_cfg = format->ch_cfg; 459 base_cfg->audio_fmt.sample_type = format->sample_type; 460 461 dev_dbg(skl->dev, "bit_depth=%x valid_bd=%x ch_config=%x\n", 462 format->bit_depth, format->valid_bit_depth, 463 format->ch_cfg); 464 465 base_cfg->audio_fmt.channel_map = format->ch_map; 466 467 base_cfg->audio_fmt.interleaving = format->interleaving_style; 468 469 base_cfg->cpc = res->cpc; 470 base_cfg->ibs = res->ibs; 471 base_cfg->obs = res->obs; 472 base_cfg->is_pages = res->is_pages; 473} 474 475/* 476 * Copies copier capabilities into copier module and updates copier module 477 * config size. 478 */ 479static void skl_copy_copier_caps(struct skl_module_cfg *mconfig, 480 struct skl_cpr_cfg *cpr_mconfig) 481{ 482 if (mconfig->formats_config.caps_size == 0) 483 return; 484 485 memcpy(cpr_mconfig->gtw_cfg.config_data, 486 mconfig->formats_config.caps, 487 mconfig->formats_config.caps_size); 488 489 cpr_mconfig->gtw_cfg.config_length = 490 (mconfig->formats_config.caps_size) / 4; 491} 492 493#define SKL_NON_GATEWAY_CPR_NODE_ID 0xFFFFFFFF 494/* 495 * Calculate the gatewat settings required for copier module, type of 496 * gateway and index of gateway to use 497 */ 498static u32 skl_get_node_id(struct skl_dev *skl, 499 struct skl_module_cfg *mconfig) 500{ 501 union skl_connector_node_id node_id = {0}; 502 union skl_ssp_dma_node ssp_node = {0}; 503 struct skl_pipe_params *params = mconfig->pipe->p_params; 504 505 switch (mconfig->dev_type) { 506 case SKL_DEVICE_BT: 507 node_id.node.dma_type = 508 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ? 509 SKL_DMA_I2S_LINK_OUTPUT_CLASS : 510 SKL_DMA_I2S_LINK_INPUT_CLASS; 511 node_id.node.vindex = params->host_dma_id + 512 (mconfig->vbus_id << 3); 513 break; 514 515 case SKL_DEVICE_I2S: 516 node_id.node.dma_type = 517 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ? 518 SKL_DMA_I2S_LINK_OUTPUT_CLASS : 519 SKL_DMA_I2S_LINK_INPUT_CLASS; 520 ssp_node.dma_node.time_slot_index = mconfig->time_slot; 521 ssp_node.dma_node.i2s_instance = mconfig->vbus_id; 522 node_id.node.vindex = ssp_node.val; 523 break; 524 525 case SKL_DEVICE_DMIC: 526 node_id.node.dma_type = SKL_DMA_DMIC_LINK_INPUT_CLASS; 527 node_id.node.vindex = mconfig->vbus_id + 528 (mconfig->time_slot); 529 break; 530 531 case SKL_DEVICE_HDALINK: 532 node_id.node.dma_type = 533 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ? 534 SKL_DMA_HDA_LINK_OUTPUT_CLASS : 535 SKL_DMA_HDA_LINK_INPUT_CLASS; 536 node_id.node.vindex = params->link_dma_id; 537 break; 538 539 case SKL_DEVICE_HDAHOST: 540 node_id.node.dma_type = 541 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ? 542 SKL_DMA_HDA_HOST_OUTPUT_CLASS : 543 SKL_DMA_HDA_HOST_INPUT_CLASS; 544 node_id.node.vindex = params->host_dma_id; 545 break; 546 547 default: 548 node_id.val = 0xFFFFFFFF; 549 break; 550 } 551 552 return node_id.val; 553} 554 555static void skl_setup_cpr_gateway_cfg(struct skl_dev *skl, 556 struct skl_module_cfg *mconfig, 557 struct skl_cpr_cfg *cpr_mconfig) 558{ 559 u32 dma_io_buf; 560 struct skl_module_res *res; 561 int res_idx = mconfig->res_idx; 562 563 cpr_mconfig->gtw_cfg.node_id = skl_get_node_id(skl, mconfig); 564 565 if (cpr_mconfig->gtw_cfg.node_id == SKL_NON_GATEWAY_CPR_NODE_ID) { 566 cpr_mconfig->cpr_feature_mask = 0; 567 return; 568 } 569 570 if (skl->nr_modules) { 571 res = &mconfig->module->resources[mconfig->res_idx]; 572 cpr_mconfig->gtw_cfg.dma_buffer_size = res->dma_buffer_size; 573 goto skip_buf_size_calc; 574 } else { 575 res = &mconfig->module->resources[res_idx]; 576 } 577 578 switch (mconfig->hw_conn_type) { 579 case SKL_CONN_SOURCE: 580 if (mconfig->dev_type == SKL_DEVICE_HDAHOST) 581 dma_io_buf = res->ibs; 582 else 583 dma_io_buf = res->obs; 584 break; 585 586 case SKL_CONN_SINK: 587 if (mconfig->dev_type == SKL_DEVICE_HDAHOST) 588 dma_io_buf = res->obs; 589 else 590 dma_io_buf = res->ibs; 591 break; 592 593 default: 594 dev_warn(skl->dev, "wrong connection type: %d\n", 595 mconfig->hw_conn_type); 596 return; 597 } 598 599 cpr_mconfig->gtw_cfg.dma_buffer_size = 600 mconfig->dma_buffer_size * dma_io_buf; 601 602 /* fallback to 2ms default value */ 603 if (!cpr_mconfig->gtw_cfg.dma_buffer_size) { 604 if (mconfig->hw_conn_type == SKL_CONN_SOURCE) 605 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * res->obs; 606 else 607 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * res->ibs; 608 } 609 610skip_buf_size_calc: 611 cpr_mconfig->cpr_feature_mask = 0; 612 cpr_mconfig->gtw_cfg.config_length = 0; 613 614 skl_copy_copier_caps(mconfig, cpr_mconfig); 615} 616 617#define DMA_CONTROL_ID 5 618#define DMA_I2S_BLOB_SIZE 21 619 620int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps, 621 u32 caps_size, u32 node_id) 622{ 623 struct skl_dma_control *dma_ctrl; 624 struct skl_ipc_large_config_msg msg = {0}; 625 int err = 0; 626 627 628 /* 629 * if blob size zero, then return 630 */ 631 if (caps_size == 0) 632 return 0; 633 634 msg.large_param_id = DMA_CONTROL_ID; 635 msg.param_data_size = sizeof(struct skl_dma_control) + caps_size; 636 637 dma_ctrl = kzalloc(msg.param_data_size, GFP_KERNEL); 638 if (dma_ctrl == NULL) 639 return -ENOMEM; 640 641 dma_ctrl->node_id = node_id; 642 643 /* 644 * NHLT blob may contain additional configs along with i2s blob. 645 * firmware expects only the i2s blob size as the config_length. 646 * So fix to i2s blob size. 647 * size in dwords. 648 */ 649 dma_ctrl->config_length = DMA_I2S_BLOB_SIZE; 650 651 memcpy(dma_ctrl->config_data, caps, caps_size); 652 653 err = skl_ipc_set_large_config(&skl->ipc, &msg, (u32 *)dma_ctrl); 654 655 kfree(dma_ctrl); 656 return err; 657} 658EXPORT_SYMBOL_GPL(skl_dsp_set_dma_control); 659 660static void skl_setup_out_format(struct skl_dev *skl, 661 struct skl_module_cfg *mconfig, 662 struct skl_audio_data_format *out_fmt) 663{ 664 struct skl_module *module = mconfig->module; 665 struct skl_module_iface *fmt = &module->formats[mconfig->fmt_idx]; 666 struct skl_module_fmt *format = &fmt->outputs[0].fmt; 667 668 out_fmt->number_of_channels = (u8)format->channels; 669 out_fmt->s_freq = format->s_freq; 670 out_fmt->bit_depth = format->bit_depth; 671 out_fmt->valid_bit_depth = format->valid_bit_depth; 672 out_fmt->ch_cfg = format->ch_cfg; 673 674 out_fmt->channel_map = format->ch_map; 675 out_fmt->interleaving = format->interleaving_style; 676 out_fmt->sample_type = format->sample_type; 677 678 dev_dbg(skl->dev, "copier out format chan=%d fre=%d bitdepth=%d\n", 679 out_fmt->number_of_channels, format->s_freq, format->bit_depth); 680} 681 682/* 683 * DSP needs SRC module for frequency conversion, SRC takes base module 684 * configuration and the target frequency as extra parameter passed as src 685 * config 686 */ 687static void skl_set_src_format(struct skl_dev *skl, 688 struct skl_module_cfg *mconfig, 689 struct skl_src_module_cfg *src_mconfig) 690{ 691 struct skl_module *module = mconfig->module; 692 struct skl_module_iface *iface = &module->formats[mconfig->fmt_idx]; 693 struct skl_module_fmt *fmt = &iface->outputs[0].fmt; 694 695 skl_set_base_module_format(skl, mconfig, 696 (struct skl_base_cfg *)src_mconfig); 697 698 src_mconfig->src_cfg = fmt->s_freq; 699} 700 701/* 702 * DSP needs updown module to do channel conversion. updown module take base 703 * module configuration and channel configuration 704 * It also take coefficients and now we have defaults applied here 705 */ 706static void skl_set_updown_mixer_format(struct skl_dev *skl, 707 struct skl_module_cfg *mconfig, 708 struct skl_up_down_mixer_cfg *mixer_mconfig) 709{ 710 struct skl_module *module = mconfig->module; 711 struct skl_module_iface *iface = &module->formats[mconfig->fmt_idx]; 712 struct skl_module_fmt *fmt = &iface->outputs[0].fmt; 713 714 skl_set_base_module_format(skl, mconfig, 715 (struct skl_base_cfg *)mixer_mconfig); 716 mixer_mconfig->out_ch_cfg = fmt->ch_cfg; 717 mixer_mconfig->ch_map = fmt->ch_map; 718} 719 720/* 721 * 'copier' is DSP internal module which copies data from Host DMA (HDA host 722 * dma) or link (hda link, SSP, PDM) 723 * Here we calculate the copier module parameters, like PCM format, output 724 * format, gateway settings 725 * copier_module_config is sent as input buffer with INIT_INSTANCE IPC msg 726 */ 727static void skl_set_copier_format(struct skl_dev *skl, 728 struct skl_module_cfg *mconfig, 729 struct skl_cpr_cfg *cpr_mconfig) 730{ 731 struct skl_audio_data_format *out_fmt = &cpr_mconfig->out_fmt; 732 struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)cpr_mconfig; 733 734 skl_set_base_module_format(skl, mconfig, base_cfg); 735 736 skl_setup_out_format(skl, mconfig, out_fmt); 737 skl_setup_cpr_gateway_cfg(skl, mconfig, cpr_mconfig); 738} 739 740/* 741 * Algo module are DSP pre processing modules. Algo module take base module 742 * configuration and params 743 */ 744 745static void skl_set_algo_format(struct skl_dev *skl, 746 struct skl_module_cfg *mconfig, 747 struct skl_algo_cfg *algo_mcfg) 748{ 749 struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)algo_mcfg; 750 751 skl_set_base_module_format(skl, mconfig, base_cfg); 752 753 if (mconfig->formats_config.caps_size == 0) 754 return; 755 756 memcpy(algo_mcfg->params, 757 mconfig->formats_config.caps, 758 mconfig->formats_config.caps_size); 759 760} 761 762/* 763 * Mic select module allows selecting one or many input channels, thus 764 * acting as a demux. 765 * 766 * Mic select module take base module configuration and out-format 767 * configuration 768 */ 769static void skl_set_base_outfmt_format(struct skl_dev *skl, 770 struct skl_module_cfg *mconfig, 771 struct skl_base_outfmt_cfg *base_outfmt_mcfg) 772{ 773 struct skl_audio_data_format *out_fmt = &base_outfmt_mcfg->out_fmt; 774 struct skl_base_cfg *base_cfg = 775 (struct skl_base_cfg *)base_outfmt_mcfg; 776 777 skl_set_base_module_format(skl, mconfig, base_cfg); 778 skl_setup_out_format(skl, mconfig, out_fmt); 779} 780 781static u16 skl_get_module_param_size(struct skl_dev *skl, 782 struct skl_module_cfg *mconfig) 783{ 784 u16 param_size; 785 786 switch (mconfig->m_type) { 787 case SKL_MODULE_TYPE_COPIER: 788 param_size = sizeof(struct skl_cpr_cfg); 789 param_size += mconfig->formats_config.caps_size; 790 return param_size; 791 792 case SKL_MODULE_TYPE_SRCINT: 793 return sizeof(struct skl_src_module_cfg); 794 795 case SKL_MODULE_TYPE_UPDWMIX: 796 return sizeof(struct skl_up_down_mixer_cfg); 797 798 case SKL_MODULE_TYPE_ALGO: 799 param_size = sizeof(struct skl_base_cfg); 800 param_size += mconfig->formats_config.caps_size; 801 return param_size; 802 803 case SKL_MODULE_TYPE_BASE_OUTFMT: 804 case SKL_MODULE_TYPE_MIC_SELECT: 805 return sizeof(struct skl_base_outfmt_cfg); 806 807 case SKL_MODULE_TYPE_MIXER: 808 case SKL_MODULE_TYPE_KPB: 809 return sizeof(struct skl_base_cfg); 810 811 default: 812 /* 813 * return only base cfg when no specific module type is 814 * specified 815 */ 816 return sizeof(struct skl_base_cfg); 817 } 818 819 return 0; 820} 821 822/* 823 * DSP firmware supports various modules like copier, SRC, updown etc. 824 * These modules required various parameters to be calculated and sent for 825 * the module initialization to DSP. By default a generic module needs only 826 * base module format configuration 827 */ 828 829static int skl_set_module_format(struct skl_dev *skl, 830 struct skl_module_cfg *module_config, 831 u16 *module_config_size, 832 void **param_data) 833{ 834 u16 param_size; 835 836 param_size = skl_get_module_param_size(skl, module_config); 837 838 *param_data = kzalloc(param_size, GFP_KERNEL); 839 if (NULL == *param_data) 840 return -ENOMEM; 841 842 *module_config_size = param_size; 843 844 switch (module_config->m_type) { 845 case SKL_MODULE_TYPE_COPIER: 846 skl_set_copier_format(skl, module_config, *param_data); 847 break; 848 849 case SKL_MODULE_TYPE_SRCINT: 850 skl_set_src_format(skl, module_config, *param_data); 851 break; 852 853 case SKL_MODULE_TYPE_UPDWMIX: 854 skl_set_updown_mixer_format(skl, module_config, *param_data); 855 break; 856 857 case SKL_MODULE_TYPE_ALGO: 858 skl_set_algo_format(skl, module_config, *param_data); 859 break; 860 861 case SKL_MODULE_TYPE_BASE_OUTFMT: 862 case SKL_MODULE_TYPE_MIC_SELECT: 863 skl_set_base_outfmt_format(skl, module_config, *param_data); 864 break; 865 866 case SKL_MODULE_TYPE_MIXER: 867 case SKL_MODULE_TYPE_KPB: 868 skl_set_base_module_format(skl, module_config, *param_data); 869 break; 870 871 default: 872 skl_set_base_module_format(skl, module_config, *param_data); 873 break; 874 875 } 876 877 dev_dbg(skl->dev, "Module type=%d id=%d config size: %d bytes\n", 878 module_config->m_type, module_config->id.module_id, 879 param_size); 880 print_hex_dump_debug("Module params:", DUMP_PREFIX_OFFSET, 8, 4, 881 *param_data, param_size, false); 882 return 0; 883} 884 885static int skl_get_queue_index(struct skl_module_pin *mpin, 886 struct skl_module_inst_id id, int max) 887{ 888 int i; 889 890 for (i = 0; i < max; i++) { 891 if (mpin[i].id.module_id == id.module_id && 892 mpin[i].id.instance_id == id.instance_id) 893 return i; 894 } 895 896 return -EINVAL; 897} 898 899/* 900 * Allocates queue for each module. 901 * if dynamic, the pin_index is allocated 0 to max_pin. 902 * In static, the pin_index is fixed based on module_id and instance id 903 */ 904static int skl_alloc_queue(struct skl_module_pin *mpin, 905 struct skl_module_cfg *tgt_cfg, int max) 906{ 907 int i; 908 struct skl_module_inst_id id = tgt_cfg->id; 909 /* 910 * if pin in dynamic, find first free pin 911 * otherwise find match module and instance id pin as topology will 912 * ensure a unique pin is assigned to this so no need to 913 * allocate/free 914 */ 915 for (i = 0; i < max; i++) { 916 if (mpin[i].is_dynamic) { 917 if (!mpin[i].in_use && 918 mpin[i].pin_state == SKL_PIN_UNBIND) { 919 920 mpin[i].in_use = true; 921 mpin[i].id.module_id = id.module_id; 922 mpin[i].id.instance_id = id.instance_id; 923 mpin[i].id.pvt_id = id.pvt_id; 924 mpin[i].tgt_mcfg = tgt_cfg; 925 return i; 926 } 927 } else { 928 if (mpin[i].id.module_id == id.module_id && 929 mpin[i].id.instance_id == id.instance_id && 930 mpin[i].pin_state == SKL_PIN_UNBIND) { 931 932 mpin[i].tgt_mcfg = tgt_cfg; 933 return i; 934 } 935 } 936 } 937 938 return -EINVAL; 939} 940 941static void skl_free_queue(struct skl_module_pin *mpin, int q_index) 942{ 943 if (mpin[q_index].is_dynamic) { 944 mpin[q_index].in_use = false; 945 mpin[q_index].id.module_id = 0; 946 mpin[q_index].id.instance_id = 0; 947 mpin[q_index].id.pvt_id = 0; 948 } 949 mpin[q_index].pin_state = SKL_PIN_UNBIND; 950 mpin[q_index].tgt_mcfg = NULL; 951} 952 953/* Module state will be set to unint, if all the out pin state is UNBIND */ 954 955static void skl_clear_module_state(struct skl_module_pin *mpin, int max, 956 struct skl_module_cfg *mcfg) 957{ 958 int i; 959 bool found = false; 960 961 for (i = 0; i < max; i++) { 962 if (mpin[i].pin_state == SKL_PIN_UNBIND) 963 continue; 964 found = true; 965 break; 966 } 967 968 if (!found) 969 mcfg->m_state = SKL_MODULE_INIT_DONE; 970 return; 971} 972 973/* 974 * A module needs to be instanataited in DSP. A mdoule is present in a 975 * collection of module referred as a PIPE. 976 * We first calculate the module format, based on module type and then 977 * invoke the DSP by sending IPC INIT_INSTANCE using ipc helper 978 */ 979int skl_init_module(struct skl_dev *skl, 980 struct skl_module_cfg *mconfig) 981{ 982 u16 module_config_size = 0; 983 void *param_data = NULL; 984 int ret; 985 struct skl_ipc_init_instance_msg msg; 986 987 dev_dbg(skl->dev, "%s: module_id = %d instance=%d\n", __func__, 988 mconfig->id.module_id, mconfig->id.pvt_id); 989 990 if (mconfig->pipe->state != SKL_PIPE_CREATED) { 991 dev_err(skl->dev, "Pipe not created state= %d pipe_id= %d\n", 992 mconfig->pipe->state, mconfig->pipe->ppl_id); 993 return -EIO; 994 } 995 996 ret = skl_set_module_format(skl, mconfig, 997 &module_config_size, ¶m_data); 998 if (ret < 0) { 999 dev_err(skl->dev, "Failed to set module format ret=%d\n", ret); 1000 return ret; 1001 } 1002 1003 msg.module_id = mconfig->id.module_id; 1004 msg.instance_id = mconfig->id.pvt_id; 1005 msg.ppl_instance_id = mconfig->pipe->ppl_id; 1006 msg.param_data_size = module_config_size; 1007 msg.core_id = mconfig->core_id; 1008 msg.domain = mconfig->domain; 1009 1010 ret = skl_ipc_init_instance(&skl->ipc, &msg, param_data); 1011 if (ret < 0) { 1012 dev_err(skl->dev, "Failed to init instance ret=%d\n", ret); 1013 kfree(param_data); 1014 return ret; 1015 } 1016 mconfig->m_state = SKL_MODULE_INIT_DONE; 1017 kfree(param_data); 1018 return ret; 1019} 1020 1021static void skl_dump_bind_info(struct skl_dev *skl, struct skl_module_cfg 1022 *src_module, struct skl_module_cfg *dst_module) 1023{ 1024 dev_dbg(skl->dev, "%s: src module_id = %d src_instance=%d\n", 1025 __func__, src_module->id.module_id, src_module->id.pvt_id); 1026 dev_dbg(skl->dev, "%s: dst_module=%d dst_instance=%d\n", __func__, 1027 dst_module->id.module_id, dst_module->id.pvt_id); 1028 1029 dev_dbg(skl->dev, "src_module state = %d dst module state = %d\n", 1030 src_module->m_state, dst_module->m_state); 1031} 1032 1033/* 1034 * On module freeup, we need to unbind the module with modules 1035 * it is already bind. 1036 * Find the pin allocated and unbind then using bind_unbind IPC 1037 */ 1038int skl_unbind_modules(struct skl_dev *skl, 1039 struct skl_module_cfg *src_mcfg, 1040 struct skl_module_cfg *dst_mcfg) 1041{ 1042 int ret; 1043 struct skl_ipc_bind_unbind_msg msg; 1044 struct skl_module_inst_id src_id = src_mcfg->id; 1045 struct skl_module_inst_id dst_id = dst_mcfg->id; 1046 int in_max = dst_mcfg->module->max_input_pins; 1047 int out_max = src_mcfg->module->max_output_pins; 1048 int src_index, dst_index, src_pin_state, dst_pin_state; 1049 1050 skl_dump_bind_info(skl, src_mcfg, dst_mcfg); 1051 1052 /* get src queue index */ 1053 src_index = skl_get_queue_index(src_mcfg->m_out_pin, dst_id, out_max); 1054 if (src_index < 0) 1055 return 0; 1056 1057 msg.src_queue = src_index; 1058 1059 /* get dst queue index */ 1060 dst_index = skl_get_queue_index(dst_mcfg->m_in_pin, src_id, in_max); 1061 if (dst_index < 0) 1062 return 0; 1063 1064 msg.dst_queue = dst_index; 1065 1066 src_pin_state = src_mcfg->m_out_pin[src_index].pin_state; 1067 dst_pin_state = dst_mcfg->m_in_pin[dst_index].pin_state; 1068 1069 if (src_pin_state != SKL_PIN_BIND_DONE || 1070 dst_pin_state != SKL_PIN_BIND_DONE) 1071 return 0; 1072 1073 msg.module_id = src_mcfg->id.module_id; 1074 msg.instance_id = src_mcfg->id.pvt_id; 1075 msg.dst_module_id = dst_mcfg->id.module_id; 1076 msg.dst_instance_id = dst_mcfg->id.pvt_id; 1077 msg.bind = false; 1078 1079 ret = skl_ipc_bind_unbind(&skl->ipc, &msg); 1080 if (!ret) { 1081 /* free queue only if unbind is success */ 1082 skl_free_queue(src_mcfg->m_out_pin, src_index); 1083 skl_free_queue(dst_mcfg->m_in_pin, dst_index); 1084 1085 /* 1086 * check only if src module bind state, bind is 1087 * always from src -> sink 1088 */ 1089 skl_clear_module_state(src_mcfg->m_out_pin, out_max, src_mcfg); 1090 } 1091 1092 return ret; 1093} 1094 1095static void fill_pin_params(struct skl_audio_data_format *pin_fmt, 1096 struct skl_module_fmt *format) 1097{ 1098 pin_fmt->number_of_channels = format->channels; 1099 pin_fmt->s_freq = format->s_freq; 1100 pin_fmt->bit_depth = format->bit_depth; 1101 pin_fmt->valid_bit_depth = format->valid_bit_depth; 1102 pin_fmt->ch_cfg = format->ch_cfg; 1103 pin_fmt->sample_type = format->sample_type; 1104 pin_fmt->channel_map = format->ch_map; 1105 pin_fmt->interleaving = format->interleaving_style; 1106} 1107 1108#define CPR_SINK_FMT_PARAM_ID 2 1109 1110/* 1111 * Once a module is instantiated it need to be 'bind' with other modules in 1112 * the pipeline. For binding we need to find the module pins which are bind 1113 * together 1114 * This function finds the pins and then sends bund_unbind IPC message to 1115 * DSP using IPC helper 1116 */ 1117int skl_bind_modules(struct skl_dev *skl, 1118 struct skl_module_cfg *src_mcfg, 1119 struct skl_module_cfg *dst_mcfg) 1120{ 1121 int ret = 0; 1122 struct skl_ipc_bind_unbind_msg msg; 1123 int in_max = dst_mcfg->module->max_input_pins; 1124 int out_max = src_mcfg->module->max_output_pins; 1125 int src_index, dst_index; 1126 struct skl_module_fmt *format; 1127 struct skl_cpr_pin_fmt pin_fmt; 1128 struct skl_module *module; 1129 struct skl_module_iface *fmt; 1130 1131 skl_dump_bind_info(skl, src_mcfg, dst_mcfg); 1132 1133 if (src_mcfg->m_state < SKL_MODULE_INIT_DONE || 1134 dst_mcfg->m_state < SKL_MODULE_INIT_DONE) 1135 return 0; 1136 1137 src_index = skl_alloc_queue(src_mcfg->m_out_pin, dst_mcfg, out_max); 1138 if (src_index < 0) 1139 return -EINVAL; 1140 1141 msg.src_queue = src_index; 1142 dst_index = skl_alloc_queue(dst_mcfg->m_in_pin, src_mcfg, in_max); 1143 if (dst_index < 0) { 1144 skl_free_queue(src_mcfg->m_out_pin, src_index); 1145 return -EINVAL; 1146 } 1147 1148 /* 1149 * Copier module requires the separate large_config_set_ipc to 1150 * configure the pins other than 0 1151 */ 1152 if (src_mcfg->m_type == SKL_MODULE_TYPE_COPIER && src_index > 0) { 1153 pin_fmt.sink_id = src_index; 1154 module = src_mcfg->module; 1155 fmt = &module->formats[src_mcfg->fmt_idx]; 1156 1157 /* Input fmt is same as that of src module input cfg */ 1158 format = &fmt->inputs[0].fmt; 1159 fill_pin_params(&(pin_fmt.src_fmt), format); 1160 1161 format = &fmt->outputs[src_index].fmt; 1162 fill_pin_params(&(pin_fmt.dst_fmt), format); 1163 ret = skl_set_module_params(skl, (void *)&pin_fmt, 1164 sizeof(struct skl_cpr_pin_fmt), 1165 CPR_SINK_FMT_PARAM_ID, src_mcfg); 1166 1167 if (ret < 0) 1168 goto out; 1169 } 1170 1171 msg.dst_queue = dst_index; 1172 1173 dev_dbg(skl->dev, "src queue = %d dst queue =%d\n", 1174 msg.src_queue, msg.dst_queue); 1175 1176 msg.module_id = src_mcfg->id.module_id; 1177 msg.instance_id = src_mcfg->id.pvt_id; 1178 msg.dst_module_id = dst_mcfg->id.module_id; 1179 msg.dst_instance_id = dst_mcfg->id.pvt_id; 1180 msg.bind = true; 1181 1182 ret = skl_ipc_bind_unbind(&skl->ipc, &msg); 1183 1184 if (!ret) { 1185 src_mcfg->m_state = SKL_MODULE_BIND_DONE; 1186 src_mcfg->m_out_pin[src_index].pin_state = SKL_PIN_BIND_DONE; 1187 dst_mcfg->m_in_pin[dst_index].pin_state = SKL_PIN_BIND_DONE; 1188 return ret; 1189 } 1190out: 1191 /* error case , if IPC fails, clear the queue index */ 1192 skl_free_queue(src_mcfg->m_out_pin, src_index); 1193 skl_free_queue(dst_mcfg->m_in_pin, dst_index); 1194 1195 return ret; 1196} 1197 1198static int skl_set_pipe_state(struct skl_dev *skl, struct skl_pipe *pipe, 1199 enum skl_ipc_pipeline_state state) 1200{ 1201 dev_dbg(skl->dev, "%s: pipe_state = %d\n", __func__, state); 1202 1203 return skl_ipc_set_pipeline_state(&skl->ipc, pipe->ppl_id, state); 1204} 1205 1206/* 1207 * A pipeline is a collection of modules. Before a module in instantiated a 1208 * pipeline needs to be created for it. 1209 * This function creates pipeline, by sending create pipeline IPC messages 1210 * to FW 1211 */ 1212int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe) 1213{ 1214 int ret; 1215 1216 dev_dbg(skl->dev, "%s: pipe_id = %d\n", __func__, pipe->ppl_id); 1217 1218 ret = skl_ipc_create_pipeline(&skl->ipc, pipe->memory_pages, 1219 pipe->pipe_priority, pipe->ppl_id, 1220 pipe->lp_mode); 1221 if (ret < 0) { 1222 dev_err(skl->dev, "Failed to create pipeline\n"); 1223 return ret; 1224 } 1225 1226 pipe->state = SKL_PIPE_CREATED; 1227 1228 return 0; 1229} 1230 1231/* 1232 * A pipeline needs to be deleted on cleanup. If a pipeline is running, 1233 * then pause it first. Before actual deletion, pipeline should enter 1234 * reset state. Finish the procedure by sending delete pipeline IPC. 1235 * DSP will stop the DMA engines and release resources 1236 */ 1237int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe) 1238{ 1239 int ret; 1240 1241 dev_dbg(skl->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id); 1242 1243 /* If pipe was not created in FW, do not try to delete it */ 1244 if (pipe->state < SKL_PIPE_CREATED) 1245 return 0; 1246 1247 /* If pipe is started, do stop the pipe in FW. */ 1248 if (pipe->state >= SKL_PIPE_STARTED) { 1249 ret = skl_set_pipe_state(skl, pipe, PPL_PAUSED); 1250 if (ret < 0) { 1251 dev_err(skl->dev, "Failed to stop pipeline\n"); 1252 return ret; 1253 } 1254 1255 pipe->state = SKL_PIPE_PAUSED; 1256 } 1257 1258 /* reset pipe state before deletion */ 1259 ret = skl_set_pipe_state(skl, pipe, PPL_RESET); 1260 if (ret < 0) { 1261 dev_err(skl->dev, "Failed to reset pipe ret=%d\n", ret); 1262 return ret; 1263 } 1264 1265 pipe->state = SKL_PIPE_RESET; 1266 1267 ret = skl_ipc_delete_pipeline(&skl->ipc, pipe->ppl_id); 1268 if (ret < 0) { 1269 dev_err(skl->dev, "Failed to delete pipeline\n"); 1270 return ret; 1271 } 1272 1273 pipe->state = SKL_PIPE_INVALID; 1274 1275 return ret; 1276} 1277 1278/* 1279 * A pipeline is also a scheduling entity in DSP which can be run, stopped 1280 * For processing data the pipe need to be run by sending IPC set pipe state 1281 * to DSP 1282 */ 1283int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe) 1284{ 1285 int ret; 1286 1287 dev_dbg(skl->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id); 1288 1289 /* If pipe was not created in FW, do not try to pause or delete */ 1290 if (pipe->state < SKL_PIPE_CREATED) 1291 return 0; 1292 1293 /* Pipe has to be paused before it is started */ 1294 ret = skl_set_pipe_state(skl, pipe, PPL_PAUSED); 1295 if (ret < 0) { 1296 dev_err(skl->dev, "Failed to pause pipe\n"); 1297 return ret; 1298 } 1299 1300 pipe->state = SKL_PIPE_PAUSED; 1301 1302 ret = skl_set_pipe_state(skl, pipe, PPL_RUNNING); 1303 if (ret < 0) { 1304 dev_err(skl->dev, "Failed to start pipe\n"); 1305 return ret; 1306 } 1307 1308 pipe->state = SKL_PIPE_STARTED; 1309 1310 return 0; 1311} 1312 1313/* 1314 * Stop the pipeline by sending set pipe state IPC 1315 * DSP doesnt implement stop so we always send pause message 1316 */ 1317int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe) 1318{ 1319 int ret; 1320 1321 dev_dbg(skl->dev, "In %s pipe=%d\n", __func__, pipe->ppl_id); 1322 1323 /* If pipe was not created in FW, do not try to pause or delete */ 1324 if (pipe->state < SKL_PIPE_PAUSED) 1325 return 0; 1326 1327 ret = skl_set_pipe_state(skl, pipe, PPL_PAUSED); 1328 if (ret < 0) { 1329 dev_dbg(skl->dev, "Failed to stop pipe\n"); 1330 return ret; 1331 } 1332 1333 pipe->state = SKL_PIPE_PAUSED; 1334 1335 return 0; 1336} 1337 1338/* 1339 * Reset the pipeline by sending set pipe state IPC this will reset the DMA 1340 * from the DSP side 1341 */ 1342int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe) 1343{ 1344 int ret; 1345 1346 /* If pipe was not created in FW, do not try to pause or delete */ 1347 if (pipe->state < SKL_PIPE_PAUSED) 1348 return 0; 1349 1350 ret = skl_set_pipe_state(skl, pipe, PPL_RESET); 1351 if (ret < 0) { 1352 dev_dbg(skl->dev, "Failed to reset pipe ret=%d\n", ret); 1353 return ret; 1354 } 1355 1356 pipe->state = SKL_PIPE_RESET; 1357 1358 return 0; 1359} 1360 1361/* Algo parameter set helper function */ 1362int skl_set_module_params(struct skl_dev *skl, u32 *params, int size, 1363 u32 param_id, struct skl_module_cfg *mcfg) 1364{ 1365 struct skl_ipc_large_config_msg msg; 1366 1367 msg.module_id = mcfg->id.module_id; 1368 msg.instance_id = mcfg->id.pvt_id; 1369 msg.param_data_size = size; 1370 msg.large_param_id = param_id; 1371 1372 return skl_ipc_set_large_config(&skl->ipc, &msg, params); 1373} 1374 1375int skl_get_module_params(struct skl_dev *skl, u32 *params, int size, 1376 u32 param_id, struct skl_module_cfg *mcfg) 1377{ 1378 struct skl_ipc_large_config_msg msg; 1379 size_t bytes = size; 1380 1381 msg.module_id = mcfg->id.module_id; 1382 msg.instance_id = mcfg->id.pvt_id; 1383 msg.param_data_size = size; 1384 msg.large_param_id = param_id; 1385 1386 return skl_ipc_get_large_config(&skl->ipc, &msg, ¶ms, &bytes); 1387} 1388