1// SPDX-License-Identifier: GPL-2.0 2// 3// Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4// 5// Copyright (C) 2013 Freescale Semiconductor, Inc. 6// 7// Based on stmp3xxx_spdif_dai.c 8// Vladimir Barinov <vbarinov@embeddedalley.com> 9// Copyright 2008 SigmaTel, Inc 10// Copyright 2008 Embedded Alley Solutions, Inc 11 12#include <linux/bitrev.h> 13#include <linux/clk.h> 14#include <linux/module.h> 15#include <linux/of_address.h> 16#include <linux/of_device.h> 17#include <linux/of_irq.h> 18#include <linux/regmap.h> 19#include <linux/pm_runtime.h> 20 21#include <sound/asoundef.h> 22#include <sound/dmaengine_pcm.h> 23#include <sound/soc.h> 24 25#include "fsl_spdif.h" 26#include "imx-pcm.h" 27 28#define FSL_SPDIF_TXFIFO_WML 0x8 29#define FSL_SPDIF_RXFIFO_WML 0x8 30 31#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 32#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 35 INT_LOSS_LOCK | INT_DPLL_LOCKED) 36 37#define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 38 39/* Index list for the values that has if (DPLL Locked) condition */ 40static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 41#define SRPC_NODPLL_START1 0x5 42#define SRPC_NODPLL_START2 0xc 43 44#define DEFAULT_RXCLK_SRC 1 45 46/** 47 * struct fsl_spdif_soc_data: soc specific data 48 * 49 * @imx: for imx platform 50 * @shared_root_clock: flag of sharing a clock source with others; 51 * so the driver shouldn't set root clock rate 52 */ 53struct fsl_spdif_soc_data { 54 bool imx; 55 bool shared_root_clock; 56}; 57 58/* 59 * SPDIF control structure 60 * Defines channel status, subcode and Q sub 61 */ 62struct spdif_mixer_control { 63 /* spinlock to access control data */ 64 spinlock_t ctl_lock; 65 66 /* IEC958 channel tx status bit */ 67 unsigned char ch_status[4]; 68 69 /* User bits */ 70 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 71 72 /* Q subcode part of user bits */ 73 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 74 75 /* Buffer offset for U/Q */ 76 u32 upos; 77 u32 qpos; 78 79 /* Ready buffer index of the two buffers */ 80 u32 ready_buf; 81}; 82 83/** 84 * struct fsl_spdif_priv - Freescale SPDIF private data 85 * @soc: SPDIF soc data 86 * @fsl_spdif_control: SPDIF control data 87 * @cpu_dai_drv: cpu dai driver 88 * @pdev: platform device pointer 89 * @regmap: regmap handler 90 * @dpll_locked: dpll lock flag 91 * @txrate: the best rates for playback 92 * @txclk_df: STC_TXCLK_DF dividers value for playback 93 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 94 * @txclk_src: STC_TXCLK_SRC values for playback 95 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 96 * @txclk: tx clock sources for playback 97 * @rxclk: rx clock sources for capture 98 * @coreclk: core clock for register access via DMA 99 * @sysclk: system clock for rx clock rate measurement 100 * @spbaclk: SPBA clock (optional, depending on SoC design) 101 * @dma_params_tx: DMA parameters for transmit channel 102 * @dma_params_rx: DMA parameters for receive channel 103 * @regcache_srpc: regcache for SRPC 104 */ 105struct fsl_spdif_priv { 106 const struct fsl_spdif_soc_data *soc; 107 struct spdif_mixer_control fsl_spdif_control; 108 struct snd_soc_dai_driver cpu_dai_drv; 109 struct platform_device *pdev; 110 struct regmap *regmap; 111 bool dpll_locked; 112 u32 txrate[SPDIF_TXRATE_MAX]; 113 u8 txclk_df[SPDIF_TXRATE_MAX]; 114 u16 sysclk_df[SPDIF_TXRATE_MAX]; 115 u8 txclk_src[SPDIF_TXRATE_MAX]; 116 u8 rxclk_src; 117 struct clk *txclk[SPDIF_TXRATE_MAX]; 118 struct clk *rxclk; 119 struct clk *coreclk; 120 struct clk *sysclk; 121 struct clk *spbaclk; 122 struct snd_dmaengine_dai_dma_data dma_params_tx; 123 struct snd_dmaengine_dai_dma_data dma_params_rx; 124 /* regcache for SRPC */ 125 u32 regcache_srpc; 126}; 127 128static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 129 .imx = false, 130 .shared_root_clock = false, 131}; 132 133static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 134 .imx = true, 135 .shared_root_clock = false, 136}; 137 138static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 139 .imx = true, 140 .shared_root_clock = true, 141}; 142 143/* Check if clk is a root clock that does not share clock source with others */ 144static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 145{ 146 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 147} 148 149/* DPLL locked and lock loss interrupt handler */ 150static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 151{ 152 struct regmap *regmap = spdif_priv->regmap; 153 struct platform_device *pdev = spdif_priv->pdev; 154 u32 locked; 155 156 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 157 locked &= SRPC_DPLL_LOCKED; 158 159 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 160 locked ? "locked" : "loss lock"); 161 162 spdif_priv->dpll_locked = locked ? true : false; 163} 164 165/* Receiver found illegal symbol interrupt handler */ 166static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 167{ 168 struct regmap *regmap = spdif_priv->regmap; 169 struct platform_device *pdev = spdif_priv->pdev; 170 171 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 172 173 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 174 if (!spdif_priv->dpll_locked) 175 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 176} 177 178/* U/Q Channel receive register full */ 179static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 180{ 181 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 182 struct regmap *regmap = spdif_priv->regmap; 183 struct platform_device *pdev = spdif_priv->pdev; 184 u32 *pos, size, val, reg; 185 186 switch (name) { 187 case 'U': 188 pos = &ctrl->upos; 189 size = SPDIF_UBITS_SIZE; 190 reg = REG_SPDIF_SRU; 191 break; 192 case 'Q': 193 pos = &ctrl->qpos; 194 size = SPDIF_QSUB_SIZE; 195 reg = REG_SPDIF_SRQ; 196 break; 197 default: 198 dev_err(&pdev->dev, "unsupported channel name\n"); 199 return; 200 } 201 202 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 203 204 if (*pos >= size * 2) { 205 *pos = 0; 206 } else if (unlikely((*pos % size) + 3 > size)) { 207 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 208 return; 209 } 210 211 regmap_read(regmap, reg, &val); 212 ctrl->subcode[*pos++] = val >> 16; 213 ctrl->subcode[*pos++] = val >> 8; 214 ctrl->subcode[*pos++] = val; 215} 216 217/* U/Q Channel sync found */ 218static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 219{ 220 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 221 struct platform_device *pdev = spdif_priv->pdev; 222 223 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 224 225 /* U/Q buffer reset */ 226 if (ctrl->qpos == 0) 227 return; 228 229 /* Set ready to this buffer */ 230 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 231} 232 233/* U/Q Channel framing error */ 234static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 235{ 236 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 237 struct regmap *regmap = spdif_priv->regmap; 238 struct platform_device *pdev = spdif_priv->pdev; 239 u32 val; 240 241 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 242 243 /* Read U/Q data to clear the irq and do buffer reset */ 244 regmap_read(regmap, REG_SPDIF_SRU, &val); 245 regmap_read(regmap, REG_SPDIF_SRQ, &val); 246 247 /* Drop this U/Q buffer */ 248 ctrl->ready_buf = 0; 249 ctrl->upos = 0; 250 ctrl->qpos = 0; 251} 252 253/* Get spdif interrupt status and clear the interrupt */ 254static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 255{ 256 struct regmap *regmap = spdif_priv->regmap; 257 u32 val, val2; 258 259 regmap_read(regmap, REG_SPDIF_SIS, &val); 260 regmap_read(regmap, REG_SPDIF_SIE, &val2); 261 262 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 263 264 return val; 265} 266 267static irqreturn_t spdif_isr(int irq, void *devid) 268{ 269 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 270 struct platform_device *pdev = spdif_priv->pdev; 271 u32 sis; 272 273 sis = spdif_intr_status_clear(spdif_priv); 274 275 if (sis & INT_DPLL_LOCKED) 276 spdif_irq_dpll_lock(spdif_priv); 277 278 if (sis & INT_TXFIFO_UNOV) 279 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 280 281 if (sis & INT_TXFIFO_RESYNC) 282 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 283 284 if (sis & INT_CNEW) 285 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 286 287 if (sis & INT_VAL_NOGOOD) 288 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 289 290 if (sis & INT_SYM_ERR) 291 spdif_irq_sym_error(spdif_priv); 292 293 if (sis & INT_BIT_ERR) 294 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 295 296 if (sis & INT_URX_FUL) 297 spdif_irq_uqrx_full(spdif_priv, 'U'); 298 299 if (sis & INT_URX_OV) 300 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 301 302 if (sis & INT_QRX_FUL) 303 spdif_irq_uqrx_full(spdif_priv, 'Q'); 304 305 if (sis & INT_QRX_OV) 306 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 307 308 if (sis & INT_UQ_SYNC) 309 spdif_irq_uq_sync(spdif_priv); 310 311 if (sis & INT_UQ_ERR) 312 spdif_irq_uq_err(spdif_priv); 313 314 if (sis & INT_RXFIFO_UNOV) 315 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 316 317 if (sis & INT_RXFIFO_RESYNC) 318 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 319 320 if (sis & INT_LOSS_LOCK) 321 spdif_irq_dpll_lock(spdif_priv); 322 323 /* FIXME: Write Tx FIFO to clear TxEm */ 324 if (sis & INT_TX_EM) 325 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 326 327 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 328 if (sis & INT_RXFIFO_FUL) 329 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 330 331 return IRQ_HANDLED; 332} 333 334static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 335{ 336 struct regmap *regmap = spdif_priv->regmap; 337 u32 val, cycle = 1000; 338 339 regcache_cache_bypass(regmap, true); 340 341 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 342 343 /* 344 * RESET bit would be cleared after finishing its reset procedure, 345 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 346 */ 347 do { 348 regmap_read(regmap, REG_SPDIF_SCR, &val); 349 } while ((val & SCR_SOFT_RESET) && cycle--); 350 351 regcache_cache_bypass(regmap, false); 352 regcache_mark_dirty(regmap); 353 regcache_sync(regmap); 354 355 if (cycle) 356 return 0; 357 else 358 return -EBUSY; 359} 360 361static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 362 u8 mask, u8 cstatus) 363{ 364 ctrl->ch_status[3] &= ~mask; 365 ctrl->ch_status[3] |= cstatus & mask; 366} 367 368static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 369{ 370 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 371 struct regmap *regmap = spdif_priv->regmap; 372 struct platform_device *pdev = spdif_priv->pdev; 373 u32 ch_status; 374 375 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 376 (bitrev8(ctrl->ch_status[1]) << 8) | 377 bitrev8(ctrl->ch_status[2]); 378 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 379 380 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 381 382 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 383 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 384 385 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 386} 387 388/* Set SPDIF PhaseConfig register for rx clock */ 389static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 390 enum spdif_gainsel gainsel, int dpll_locked) 391{ 392 struct regmap *regmap = spdif_priv->regmap; 393 u8 clksrc = spdif_priv->rxclk_src; 394 395 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 396 return -EINVAL; 397 398 regmap_update_bits(regmap, REG_SPDIF_SRPC, 399 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 400 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 401 402 return 0; 403} 404 405static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 406 int sample_rate) 407{ 408 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 409 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 410 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 411 struct regmap *regmap = spdif_priv->regmap; 412 struct platform_device *pdev = spdif_priv->pdev; 413 unsigned long csfs = 0; 414 u32 stc, mask, rate; 415 u16 sysclk_df; 416 u8 clk, txclk_df; 417 int ret; 418 419 switch (sample_rate) { 420 case 32000: 421 rate = SPDIF_TXRATE_32000; 422 csfs = IEC958_AES3_CON_FS_32000; 423 break; 424 case 44100: 425 rate = SPDIF_TXRATE_44100; 426 csfs = IEC958_AES3_CON_FS_44100; 427 break; 428 case 48000: 429 rate = SPDIF_TXRATE_48000; 430 csfs = IEC958_AES3_CON_FS_48000; 431 break; 432 case 96000: 433 rate = SPDIF_TXRATE_96000; 434 csfs = IEC958_AES3_CON_FS_96000; 435 break; 436 case 192000: 437 rate = SPDIF_TXRATE_192000; 438 csfs = IEC958_AES3_CON_FS_192000; 439 break; 440 default: 441 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 442 return -EINVAL; 443 } 444 445 clk = spdif_priv->txclk_src[rate]; 446 if (clk >= STC_TXCLK_SRC_MAX) { 447 dev_err(&pdev->dev, "tx clock source is out of range\n"); 448 return -EINVAL; 449 } 450 451 txclk_df = spdif_priv->txclk_df[rate]; 452 if (txclk_df == 0) { 453 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 454 return -EINVAL; 455 } 456 457 sysclk_df = spdif_priv->sysclk_df[rate]; 458 459 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 460 goto clk_set_bypass; 461 462 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 463 ret = clk_set_rate(spdif_priv->txclk[rate], 464 64 * sample_rate * txclk_df); 465 if (ret) { 466 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 467 return ret; 468 } 469 470clk_set_bypass: 471 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 472 (64 * sample_rate * txclk_df * sysclk_df)); 473 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 474 clk_get_rate(spdif_priv->txclk[rate])); 475 476 /* set fs field in consumer channel status */ 477 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 478 479 /* select clock source and divisor */ 480 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 481 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 482 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 483 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 484 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 485 486 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 487 spdif_priv->txrate[rate], sample_rate); 488 489 return 0; 490} 491 492static int fsl_spdif_startup(struct snd_pcm_substream *substream, 493 struct snd_soc_dai *cpu_dai) 494{ 495 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 496 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 497 struct platform_device *pdev = spdif_priv->pdev; 498 struct regmap *regmap = spdif_priv->regmap; 499 u32 scr, mask; 500 int ret; 501 502 /* Reset module and interrupts only for first initialization */ 503 if (!snd_soc_dai_active(cpu_dai)) { 504 ret = spdif_softreset(spdif_priv); 505 if (ret) { 506 dev_err(&pdev->dev, "failed to soft reset\n"); 507 return ret; 508 } 509 510 /* Disable all the interrupts */ 511 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 512 } 513 514 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 515 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 516 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 517 SCR_TXFIFO_FSEL_IF8; 518 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 519 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 520 SCR_TXFIFO_FSEL_MASK; 521 } else { 522 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 523 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 524 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 525 } 526 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 527 528 /* Power up SPDIF module */ 529 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 530 531 return 0; 532} 533 534static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 535 struct snd_soc_dai *cpu_dai) 536{ 537 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 538 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 539 struct regmap *regmap = spdif_priv->regmap; 540 u32 scr, mask; 541 542 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 543 scr = 0; 544 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 545 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 546 SCR_TXFIFO_FSEL_MASK; 547 /* Disable TX clock */ 548 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0); 549 } else { 550 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 551 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 552 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 553 } 554 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 555 556 /* Power down SPDIF module only if tx&rx are both inactive */ 557 if (!snd_soc_dai_active(cpu_dai)) { 558 spdif_intr_status_clear(spdif_priv); 559 regmap_update_bits(regmap, REG_SPDIF_SCR, 560 SCR_LOW_POWER, SCR_LOW_POWER); 561 } 562} 563 564static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 565 struct snd_pcm_hw_params *params, 566 struct snd_soc_dai *dai) 567{ 568 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 569 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 570 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 571 struct platform_device *pdev = spdif_priv->pdev; 572 u32 sample_rate = params_rate(params); 573 int ret = 0; 574 575 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 576 ret = spdif_set_sample_rate(substream, sample_rate); 577 if (ret) { 578 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 579 __func__, sample_rate); 580 return ret; 581 } 582 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 583 IEC958_AES3_CON_CLOCK_1000PPM); 584 spdif_write_channel_status(spdif_priv); 585 } else { 586 /* Setup rx clock source */ 587 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 588 } 589 590 return ret; 591} 592 593static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 594 int cmd, struct snd_soc_dai *dai) 595{ 596 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 597 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 598 struct regmap *regmap = spdif_priv->regmap; 599 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 600 u32 intr = SIE_INTR_FOR(tx); 601 u32 dmaen = SCR_DMA_xX_EN(tx); 602 603 switch (cmd) { 604 case SNDRV_PCM_TRIGGER_START: 605 case SNDRV_PCM_TRIGGER_RESUME: 606 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 607 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 608 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 609 break; 610 case SNDRV_PCM_TRIGGER_STOP: 611 case SNDRV_PCM_TRIGGER_SUSPEND: 612 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 613 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 614 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 615 regmap_write(regmap, REG_SPDIF_STL, 0x0); 616 regmap_write(regmap, REG_SPDIF_STR, 0x0); 617 break; 618 default: 619 return -EINVAL; 620 } 621 622 return 0; 623} 624 625static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 626 .startup = fsl_spdif_startup, 627 .hw_params = fsl_spdif_hw_params, 628 .trigger = fsl_spdif_trigger, 629 .shutdown = fsl_spdif_shutdown, 630}; 631 632 633/* 634 * FSL SPDIF IEC958 controller(mixer) functions 635 * 636 * Channel status get/put control 637 * User bit value get/put control 638 * Valid bit value get control 639 * DPLL lock status get control 640 * User bit sync mode selection control 641 */ 642 643static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 644 struct snd_ctl_elem_info *uinfo) 645{ 646 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 647 uinfo->count = 1; 648 649 return 0; 650} 651 652static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 653 struct snd_ctl_elem_value *uvalue) 654{ 655 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 656 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 657 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 658 659 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 660 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 661 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 662 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 663 664 return 0; 665} 666 667static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 668 struct snd_ctl_elem_value *uvalue) 669{ 670 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 671 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 672 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 673 674 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 675 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 676 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 677 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 678 679 spdif_write_channel_status(spdif_priv); 680 681 return 0; 682} 683 684/* Get channel status from SPDIF_RX_CCHAN register */ 685static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 686 struct snd_ctl_elem_value *ucontrol) 687{ 688 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 689 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 690 struct regmap *regmap = spdif_priv->regmap; 691 u32 cstatus, val; 692 693 regmap_read(regmap, REG_SPDIF_SIS, &val); 694 if (!(val & INT_CNEW)) 695 return -EAGAIN; 696 697 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 698 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 699 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 700 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 701 702 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 703 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 704 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 705 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 706 707 /* Clear intr */ 708 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 709 710 return 0; 711} 712 713/* 714 * Get User bits (subcode) from chip value which readed out 715 * in UChannel register. 716 */ 717static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 718 struct snd_ctl_elem_value *ucontrol) 719{ 720 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 721 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 722 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 723 unsigned long flags; 724 int ret = -EAGAIN; 725 726 spin_lock_irqsave(&ctrl->ctl_lock, flags); 727 if (ctrl->ready_buf) { 728 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 729 memcpy(&ucontrol->value.iec958.subcode[0], 730 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 731 ret = 0; 732 } 733 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 734 735 return ret; 736} 737 738/* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 739static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 740 struct snd_ctl_elem_info *uinfo) 741{ 742 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 743 uinfo->count = SPDIF_QSUB_SIZE; 744 745 return 0; 746} 747 748/* Get Q subcode from chip value which readed out in QChannel register */ 749static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 750 struct snd_ctl_elem_value *ucontrol) 751{ 752 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 753 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 754 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 755 unsigned long flags; 756 int ret = -EAGAIN; 757 758 spin_lock_irqsave(&ctrl->ctl_lock, flags); 759 if (ctrl->ready_buf) { 760 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 761 memcpy(&ucontrol->value.bytes.data[0], 762 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 763 ret = 0; 764 } 765 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 766 767 return ret; 768} 769 770/* Valid bit information */ 771static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, 772 struct snd_ctl_elem_info *uinfo) 773{ 774 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 775 uinfo->count = 1; 776 uinfo->value.integer.min = 0; 777 uinfo->value.integer.max = 1; 778 779 return 0; 780} 781 782/* Get valid good bit from interrupt status register */ 783static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 784 struct snd_ctl_elem_value *ucontrol) 785{ 786 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 787 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 788 struct regmap *regmap = spdif_priv->regmap; 789 u32 val; 790 791 regmap_read(regmap, REG_SPDIF_SIS, &val); 792 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 793 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 794 795 return 0; 796} 797 798static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 799 struct snd_ctl_elem_value *ucontrol) 800{ 801 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 802 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 803 struct regmap *regmap = spdif_priv->regmap; 804 u32 val; 805 806 regmap_read(regmap, REG_SPDIF_SCR, &val); 807 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 808 val = 1 - val; 809 ucontrol->value.integer.value[0] = val; 810 811 return 0; 812} 813 814static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 815 struct snd_ctl_elem_value *ucontrol) 816{ 817 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 818 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 819 struct regmap *regmap = spdif_priv->regmap; 820 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 821 822 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 823 824 return 0; 825} 826 827/* DPLL lock information */ 828static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 829 struct snd_ctl_elem_info *uinfo) 830{ 831 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 832 uinfo->count = 1; 833 uinfo->value.integer.min = 16000; 834 uinfo->value.integer.max = 96000; 835 836 return 0; 837} 838 839static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 840 24, 16, 12, 8, 6, 4, 3, 841}; 842 843/* Get RX data clock rate given the SPDIF bus_clk */ 844static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 845 enum spdif_gainsel gainsel) 846{ 847 struct regmap *regmap = spdif_priv->regmap; 848 struct platform_device *pdev = spdif_priv->pdev; 849 u64 tmpval64, busclk_freq = 0; 850 u32 freqmeas, phaseconf; 851 u8 clksrc; 852 853 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 854 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 855 856 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 857 858 /* Get bus clock from system */ 859 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 860 busclk_freq = clk_get_rate(spdif_priv->sysclk); 861 862 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 863 tmpval64 = (u64) busclk_freq * freqmeas; 864 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 865 do_div(tmpval64, 128 * 1024); 866 867 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 868 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 869 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 870 871 return (int)tmpval64; 872} 873 874/* 875 * Get DPLL lock or not info from stable interrupt status register. 876 * User application must use this control to get locked, 877 * then can do next PCM operation 878 */ 879static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 880 struct snd_ctl_elem_value *ucontrol) 881{ 882 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 883 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 884 int rate = 0; 885 886 if (spdif_priv->dpll_locked) 887 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 888 889 ucontrol->value.integer.value[0] = rate; 890 891 return 0; 892} 893 894/* User bit sync mode info */ 895static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol, 896 struct snd_ctl_elem_info *uinfo) 897{ 898 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 899 uinfo->count = 1; 900 uinfo->value.integer.min = 0; 901 uinfo->value.integer.max = 1; 902 903 return 0; 904} 905 906/* 907 * User bit sync mode: 908 * 1 CD User channel subcode 909 * 0 Non-CD data 910 */ 911static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 912 struct snd_ctl_elem_value *ucontrol) 913{ 914 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 915 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 916 struct regmap *regmap = spdif_priv->regmap; 917 u32 val; 918 919 regmap_read(regmap, REG_SPDIF_SRCD, &val); 920 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 921 922 return 0; 923} 924 925/* 926 * User bit sync mode: 927 * 1 CD User channel subcode 928 * 0 Non-CD data 929 */ 930static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 931 struct snd_ctl_elem_value *ucontrol) 932{ 933 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 934 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 935 struct regmap *regmap = spdif_priv->regmap; 936 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 937 938 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 939 940 return 0; 941} 942 943/* FSL SPDIF IEC958 controller defines */ 944static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 945 /* Status cchanel controller */ 946 { 947 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 948 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 949 .access = SNDRV_CTL_ELEM_ACCESS_READ | 950 SNDRV_CTL_ELEM_ACCESS_WRITE | 951 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 952 .info = fsl_spdif_info, 953 .get = fsl_spdif_pb_get, 954 .put = fsl_spdif_pb_put, 955 }, 956 { 957 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 958 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 959 .access = SNDRV_CTL_ELEM_ACCESS_READ | 960 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 961 .info = fsl_spdif_info, 962 .get = fsl_spdif_capture_get, 963 }, 964 /* User bits controller */ 965 { 966 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 967 .name = "IEC958 Subcode Capture Default", 968 .access = SNDRV_CTL_ELEM_ACCESS_READ | 969 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 970 .info = fsl_spdif_info, 971 .get = fsl_spdif_subcode_get, 972 }, 973 { 974 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 975 .name = "IEC958 Q-subcode Capture Default", 976 .access = SNDRV_CTL_ELEM_ACCESS_READ | 977 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 978 .info = fsl_spdif_qinfo, 979 .get = fsl_spdif_qget, 980 }, 981 /* Valid bit error controller */ 982 { 983 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 984 .name = "IEC958 RX V-Bit Errors", 985 .access = SNDRV_CTL_ELEM_ACCESS_READ | 986 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 987 .info = fsl_spdif_vbit_info, 988 .get = fsl_spdif_rx_vbit_get, 989 }, 990 { 991 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 992 .name = "IEC958 TX V-Bit", 993 .access = SNDRV_CTL_ELEM_ACCESS_READ | 994 SNDRV_CTL_ELEM_ACCESS_WRITE | 995 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 996 .info = fsl_spdif_vbit_info, 997 .get = fsl_spdif_tx_vbit_get, 998 .put = fsl_spdif_tx_vbit_put, 999 }, 1000 /* DPLL lock info get controller */ 1001 { 1002 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1003 .name = "RX Sample Rate", 1004 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1005 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1006 .info = fsl_spdif_rxrate_info, 1007 .get = fsl_spdif_rxrate_get, 1008 }, 1009 /* User bit sync mode set/get controller */ 1010 { 1011 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1012 .name = "IEC958 USyncMode CDText", 1013 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1014 SNDRV_CTL_ELEM_ACCESS_WRITE | 1015 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1016 .info = fsl_spdif_usync_info, 1017 .get = fsl_spdif_usync_get, 1018 .put = fsl_spdif_usync_put, 1019 }, 1020}; 1021 1022static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1023{ 1024 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1025 1026 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1027 &spdif_private->dma_params_rx); 1028 1029 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1030 1031 /*Clear the val bit for Tx*/ 1032 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1033 SCR_VAL_MASK, SCR_VAL_CLEAR); 1034 1035 return 0; 1036} 1037 1038static struct snd_soc_dai_driver fsl_spdif_dai = { 1039 .probe = &fsl_spdif_dai_probe, 1040 .playback = { 1041 .stream_name = "CPU-Playback", 1042 .channels_min = 2, 1043 .channels_max = 2, 1044 .rates = FSL_SPDIF_RATES_PLAYBACK, 1045 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1046 }, 1047 .capture = { 1048 .stream_name = "CPU-Capture", 1049 .channels_min = 2, 1050 .channels_max = 2, 1051 .rates = FSL_SPDIF_RATES_CAPTURE, 1052 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1053 }, 1054 .ops = &fsl_spdif_dai_ops, 1055}; 1056 1057static const struct snd_soc_component_driver fsl_spdif_component = { 1058 .name = "fsl-spdif", 1059}; 1060 1061/* FSL SPDIF REGMAP */ 1062static const struct reg_default fsl_spdif_reg_defaults[] = { 1063 {REG_SPDIF_SCR, 0x00000400}, 1064 {REG_SPDIF_SRCD, 0x00000000}, 1065 {REG_SPDIF_SIE, 0x00000000}, 1066 {REG_SPDIF_STL, 0x00000000}, 1067 {REG_SPDIF_STR, 0x00000000}, 1068 {REG_SPDIF_STCSCH, 0x00000000}, 1069 {REG_SPDIF_STCSCL, 0x00000000}, 1070 {REG_SPDIF_STC, 0x00020f00}, 1071}; 1072 1073static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1074{ 1075 switch (reg) { 1076 case REG_SPDIF_SCR: 1077 case REG_SPDIF_SRCD: 1078 case REG_SPDIF_SRPC: 1079 case REG_SPDIF_SIE: 1080 case REG_SPDIF_SIS: 1081 case REG_SPDIF_SRL: 1082 case REG_SPDIF_SRR: 1083 case REG_SPDIF_SRCSH: 1084 case REG_SPDIF_SRCSL: 1085 case REG_SPDIF_SRU: 1086 case REG_SPDIF_SRQ: 1087 case REG_SPDIF_STCSCH: 1088 case REG_SPDIF_STCSCL: 1089 case REG_SPDIF_SRFM: 1090 case REG_SPDIF_STC: 1091 return true; 1092 default: 1093 return false; 1094 } 1095} 1096 1097static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1098{ 1099 switch (reg) { 1100 case REG_SPDIF_SRPC: 1101 case REG_SPDIF_SIS: 1102 case REG_SPDIF_SRL: 1103 case REG_SPDIF_SRR: 1104 case REG_SPDIF_SRCSH: 1105 case REG_SPDIF_SRCSL: 1106 case REG_SPDIF_SRU: 1107 case REG_SPDIF_SRQ: 1108 case REG_SPDIF_SRFM: 1109 return true; 1110 default: 1111 return false; 1112 } 1113} 1114 1115static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1116{ 1117 switch (reg) { 1118 case REG_SPDIF_SCR: 1119 case REG_SPDIF_SRCD: 1120 case REG_SPDIF_SRPC: 1121 case REG_SPDIF_SIE: 1122 case REG_SPDIF_SIC: 1123 case REG_SPDIF_STL: 1124 case REG_SPDIF_STR: 1125 case REG_SPDIF_STCSCH: 1126 case REG_SPDIF_STCSCL: 1127 case REG_SPDIF_STC: 1128 return true; 1129 default: 1130 return false; 1131 } 1132} 1133 1134static const struct regmap_config fsl_spdif_regmap_config = { 1135 .reg_bits = 32, 1136 .reg_stride = 4, 1137 .val_bits = 32, 1138 1139 .max_register = REG_SPDIF_STC, 1140 .reg_defaults = fsl_spdif_reg_defaults, 1141 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1142 .readable_reg = fsl_spdif_readable_reg, 1143 .volatile_reg = fsl_spdif_volatile_reg, 1144 .writeable_reg = fsl_spdif_writeable_reg, 1145 .cache_type = REGCACHE_FLAT, 1146}; 1147 1148static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1149 struct clk *clk, u64 savesub, 1150 enum spdif_txrate index, bool round) 1151{ 1152 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; 1153 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1154 u64 rate_ideal, rate_actual, sub; 1155 u32 arate; 1156 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1157 u8 txclk_df; 1158 1159 /* The sysclk has an extra divisor [2, 512] */ 1160 sysclk_dfmin = is_sysclk ? 2 : 1; 1161 sysclk_dfmax = is_sysclk ? 512 : 1; 1162 1163 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1164 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1165 rate_ideal = rate[index] * txclk_df * 64ULL; 1166 if (round) 1167 rate_actual = clk_round_rate(clk, rate_ideal); 1168 else 1169 rate_actual = clk_get_rate(clk); 1170 1171 arate = rate_actual / 64; 1172 arate /= txclk_df * sysclk_df; 1173 1174 if (arate == rate[index]) { 1175 /* We are lucky */ 1176 savesub = 0; 1177 spdif_priv->txclk_df[index] = txclk_df; 1178 spdif_priv->sysclk_df[index] = sysclk_df; 1179 spdif_priv->txrate[index] = arate; 1180 goto out; 1181 } else if (arate / rate[index] == 1) { 1182 /* A little bigger than expect */ 1183 sub = (u64)(arate - rate[index]) * 100000; 1184 do_div(sub, rate[index]); 1185 if (sub >= savesub) 1186 continue; 1187 savesub = sub; 1188 spdif_priv->txclk_df[index] = txclk_df; 1189 spdif_priv->sysclk_df[index] = sysclk_df; 1190 spdif_priv->txrate[index] = arate; 1191 } else if (rate[index] / arate == 1) { 1192 /* A little smaller than expect */ 1193 sub = (u64)(rate[index] - arate) * 100000; 1194 do_div(sub, rate[index]); 1195 if (sub >= savesub) 1196 continue; 1197 savesub = sub; 1198 spdif_priv->txclk_df[index] = txclk_df; 1199 spdif_priv->sysclk_df[index] = sysclk_df; 1200 spdif_priv->txrate[index] = arate; 1201 } 1202 } 1203 } 1204 1205out: 1206 return savesub; 1207} 1208 1209static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1210 enum spdif_txrate index) 1211{ 1212 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; 1213 struct platform_device *pdev = spdif_priv->pdev; 1214 struct device *dev = &pdev->dev; 1215 u64 savesub = 100000, ret; 1216 struct clk *clk; 1217 char tmp[16]; 1218 int i; 1219 1220 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1221 sprintf(tmp, "rxtx%d", i); 1222 clk = devm_clk_get(&pdev->dev, tmp); 1223 if (IS_ERR(clk)) { 1224 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1225 return PTR_ERR(clk); 1226 } 1227 if (!clk_get_rate(clk)) 1228 continue; 1229 1230 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1231 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1232 if (savesub == ret) 1233 continue; 1234 1235 savesub = ret; 1236 spdif_priv->txclk[index] = clk; 1237 spdif_priv->txclk_src[index] = i; 1238 1239 /* To quick catch a divisor, we allow a 0.1% deviation */ 1240 if (savesub < 100) 1241 break; 1242 } 1243 1244 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1245 spdif_priv->txclk_src[index], rate[index]); 1246 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n", 1247 spdif_priv->txclk_df[index], rate[index]); 1248 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) 1249 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n", 1250 spdif_priv->sysclk_df[index], rate[index]); 1251 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n", 1252 rate[index], spdif_priv->txrate[index]); 1253 1254 return 0; 1255} 1256 1257static int fsl_spdif_probe(struct platform_device *pdev) 1258{ 1259 struct fsl_spdif_priv *spdif_priv; 1260 struct spdif_mixer_control *ctrl; 1261 struct resource *res; 1262 void __iomem *regs; 1263 int irq, ret, i; 1264 1265 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1266 if (!spdif_priv) 1267 return -ENOMEM; 1268 1269 spdif_priv->pdev = pdev; 1270 1271 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1272 if (!spdif_priv->soc) { 1273 dev_err(&pdev->dev, "failed to get soc data\n"); 1274 return -ENODEV; 1275 } 1276 1277 /* Initialize this copy of the CPU DAI driver structure */ 1278 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1279 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1280 1281 /* Get the addresses and IRQ */ 1282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1283 regs = devm_ioremap_resource(&pdev->dev, res); 1284 if (IS_ERR(regs)) 1285 return PTR_ERR(regs); 1286 1287 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1288 "core", regs, &fsl_spdif_regmap_config); 1289 if (IS_ERR(spdif_priv->regmap)) { 1290 dev_err(&pdev->dev, "regmap init failed\n"); 1291 return PTR_ERR(spdif_priv->regmap); 1292 } 1293 1294 irq = platform_get_irq(pdev, 0); 1295 if (irq < 0) 1296 return irq; 1297 1298 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1299 dev_name(&pdev->dev), spdif_priv); 1300 if (ret) { 1301 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1302 return ret; 1303 } 1304 1305 /* Get system clock for rx clock rate calculation */ 1306 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); 1307 if (IS_ERR(spdif_priv->sysclk)) { 1308 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1309 return PTR_ERR(spdif_priv->sysclk); 1310 } 1311 1312 /* Get core clock for data register access via DMA */ 1313 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1314 if (IS_ERR(spdif_priv->coreclk)) { 1315 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1316 return PTR_ERR(spdif_priv->coreclk); 1317 } 1318 1319 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1320 if (IS_ERR(spdif_priv->spbaclk)) 1321 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1322 1323 /* Select clock source for rx/tx clock */ 1324 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); 1325 if (IS_ERR(spdif_priv->rxclk)) { 1326 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1327 return PTR_ERR(spdif_priv->rxclk); 1328 } 1329 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1330 1331 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1332 ret = fsl_spdif_probe_txclk(spdif_priv, i); 1333 if (ret) 1334 return ret; 1335 } 1336 1337 /* Initial spinlock for control data */ 1338 ctrl = &spdif_priv->fsl_spdif_control; 1339 spin_lock_init(&ctrl->ctl_lock); 1340 1341 /* Init tx channel status default value */ 1342 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1343 IEC958_AES0_CON_EMPHASIS_5015; 1344 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1345 ctrl->ch_status[2] = 0x00; 1346 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1347 IEC958_AES3_CON_CLOCK_1000PPM; 1348 1349 spdif_priv->dpll_locked = false; 1350 1351 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML; 1352 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML; 1353 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1354 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1355 1356 /* Register with ASoC */ 1357 dev_set_drvdata(&pdev->dev, spdif_priv); 1358 pm_runtime_enable(&pdev->dev); 1359 regcache_cache_only(spdif_priv->regmap, true); 1360 1361 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1362 &spdif_priv->cpu_dai_drv, 1); 1363 if (ret) { 1364 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1365 goto err_pm_disable; 1366 } 1367 1368 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE); 1369 if (ret) { 1370 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); 1371 goto err_pm_disable; 1372 } 1373 1374 return ret; 1375 1376err_pm_disable: 1377 pm_runtime_disable(&pdev->dev); 1378 return ret; 1379} 1380 1381static int fsl_spdif_remove(struct platform_device *pdev) 1382{ 1383 pm_runtime_disable(&pdev->dev); 1384 1385 return 0; 1386} 1387 1388#ifdef CONFIG_PM 1389static int fsl_spdif_runtime_suspend(struct device *dev) 1390{ 1391 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1392 int i; 1393 1394 /* Disable all the interrupts */ 1395 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); 1396 1397 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1398 &spdif_priv->regcache_srpc); 1399 regcache_cache_only(spdif_priv->regmap, true); 1400 1401 clk_disable_unprepare(spdif_priv->rxclk); 1402 1403 for (i = 0; i < SPDIF_TXRATE_MAX; i++) 1404 clk_disable_unprepare(spdif_priv->txclk[i]); 1405 1406 if (!IS_ERR(spdif_priv->spbaclk)) 1407 clk_disable_unprepare(spdif_priv->spbaclk); 1408 clk_disable_unprepare(spdif_priv->coreclk); 1409 1410 return 0; 1411} 1412 1413static int fsl_spdif_runtime_resume(struct device *dev) 1414{ 1415 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1416 int ret; 1417 int i; 1418 1419 ret = clk_prepare_enable(spdif_priv->coreclk); 1420 if (ret) { 1421 dev_err(dev, "failed to enable core clock\n"); 1422 return ret; 1423 } 1424 1425 if (!IS_ERR(spdif_priv->spbaclk)) { 1426 ret = clk_prepare_enable(spdif_priv->spbaclk); 1427 if (ret) { 1428 dev_err(dev, "failed to enable spba clock\n"); 1429 goto disable_core_clk; 1430 } 1431 } 1432 1433 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1434 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1435 if (ret) 1436 goto disable_tx_clk; 1437 } 1438 1439 ret = clk_prepare_enable(spdif_priv->rxclk); 1440 if (ret) 1441 goto disable_tx_clk; 1442 1443 regcache_cache_only(spdif_priv->regmap, false); 1444 regcache_mark_dirty(spdif_priv->regmap); 1445 1446 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1447 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1448 spdif_priv->regcache_srpc); 1449 1450 ret = regcache_sync(spdif_priv->regmap); 1451 if (ret) 1452 goto disable_rx_clk; 1453 1454 return 0; 1455 1456disable_rx_clk: 1457 clk_disable_unprepare(spdif_priv->rxclk); 1458disable_tx_clk: 1459 for (i--; i >= 0; i--) 1460 clk_disable_unprepare(spdif_priv->txclk[i]); 1461 if (!IS_ERR(spdif_priv->spbaclk)) 1462 clk_disable_unprepare(spdif_priv->spbaclk); 1463disable_core_clk: 1464 clk_disable_unprepare(spdif_priv->coreclk); 1465 1466 return ret; 1467} 1468#endif /* CONFIG_PM */ 1469 1470static const struct dev_pm_ops fsl_spdif_pm = { 1471 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1472 pm_runtime_force_resume) 1473 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1474 NULL) 1475}; 1476 1477static const struct of_device_id fsl_spdif_dt_ids[] = { 1478 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1479 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1480 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1481 {} 1482}; 1483MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1484 1485static struct platform_driver fsl_spdif_driver = { 1486 .driver = { 1487 .name = "fsl-spdif-dai", 1488 .of_match_table = fsl_spdif_dt_ids, 1489 .pm = &fsl_spdif_pm, 1490 }, 1491 .probe = fsl_spdif_probe, 1492 .remove = fsl_spdif_remove, 1493}; 1494 1495module_platform_driver(fsl_spdif_driver); 1496 1497MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1498MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1499MODULE_LICENSE("GPL v2"); 1500MODULE_ALIAS("platform:fsl-spdif-dai"); 1501