1// SPDX-License-Identifier: GPL-2.0 2// 3// ALSA SoC IMX MQS driver 4// 5// Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 6// Copyright 2019 NXP 7 8#include <linux/clk.h> 9#include <linux/module.h> 10#include <linux/moduleparam.h> 11#include <linux/mfd/syscon.h> 12#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 13#include <linux/pm_runtime.h> 14#include <linux/of.h> 15#include <linux/pm.h> 16#include <linux/slab.h> 17#include <sound/soc.h> 18#include <sound/pcm.h> 19#include <sound/initval.h> 20 21#define REG_MQS_CTRL 0x00 22 23#define MQS_EN_MASK (0x1 << 28) 24#define MQS_EN_SHIFT (28) 25#define MQS_SW_RST_MASK (0x1 << 24) 26#define MQS_SW_RST_SHIFT (24) 27#define MQS_OVERSAMPLE_MASK (0x1 << 20) 28#define MQS_OVERSAMPLE_SHIFT (20) 29#define MQS_CLK_DIV_MASK (0xFF << 0) 30#define MQS_CLK_DIV_SHIFT (0) 31 32/* codec private data */ 33struct fsl_mqs { 34 struct regmap *regmap; 35 struct clk *mclk; 36 struct clk *ipg; 37 38 unsigned int reg_iomuxc_gpr2; 39 unsigned int reg_mqs_ctrl; 40 bool use_gpr; 41}; 42 43#define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 44#define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE 45 46static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, 47 struct snd_pcm_hw_params *params, 48 struct snd_soc_dai *dai) 49{ 50 struct snd_soc_component *component = dai->component; 51 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 52 unsigned long mclk_rate; 53 int div, res; 54 int lrclk; 55 56 mclk_rate = clk_get_rate(mqs_priv->mclk); 57 lrclk = params_rate(params); 58 59 /* 60 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate; 61 * if repeat_rate is 8, mqs can achieve better quality. 62 * oversample rate is fix to 32 currently. 63 */ 64 div = mclk_rate / (32 * lrclk * 2 * 8); 65 res = mclk_rate % (32 * lrclk * 2 * 8); 66 67 if (res == 0 && div > 0 && div <= 256) { 68 if (mqs_priv->use_gpr) { 69 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 70 IMX6SX_GPR2_MQS_CLK_DIV_MASK, 71 (div - 1) << IMX6SX_GPR2_MQS_CLK_DIV_SHIFT); 72 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 73 IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 0); 74 } else { 75 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 76 MQS_CLK_DIV_MASK, 77 (div - 1) << MQS_CLK_DIV_SHIFT); 78 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 79 MQS_OVERSAMPLE_MASK, 0); 80 } 81 } else { 82 dev_err(component->dev, "can't get proper divider\n"); 83 } 84 85 return 0; 86} 87 88static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 89{ 90 /* Only LEFT_J & SLAVE mode is supported. */ 91 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 92 case SND_SOC_DAIFMT_LEFT_J: 93 break; 94 default: 95 return -EINVAL; 96 } 97 98 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 99 case SND_SOC_DAIFMT_NB_NF: 100 break; 101 default: 102 return -EINVAL; 103 } 104 105 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 106 case SND_SOC_DAIFMT_CBS_CFS: 107 break; 108 default: 109 return -EINVAL; 110 } 111 112 return 0; 113} 114 115static int fsl_mqs_startup(struct snd_pcm_substream *substream, 116 struct snd_soc_dai *dai) 117{ 118 struct snd_soc_component *component = dai->component; 119 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 120 121 if (mqs_priv->use_gpr) 122 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 123 IMX6SX_GPR2_MQS_EN_MASK, 124 1 << IMX6SX_GPR2_MQS_EN_SHIFT); 125 else 126 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 127 MQS_EN_MASK, 128 1 << MQS_EN_SHIFT); 129 return 0; 130} 131 132static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, 133 struct snd_soc_dai *dai) 134{ 135 struct snd_soc_component *component = dai->component; 136 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 137 138 if (mqs_priv->use_gpr) 139 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 140 IMX6SX_GPR2_MQS_EN_MASK, 0); 141 else 142 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 143 MQS_EN_MASK, 0); 144} 145 146static const struct snd_soc_component_driver soc_codec_fsl_mqs = { 147 .idle_bias_on = 1, 148 .non_legacy_dai_naming = 1, 149}; 150 151static const struct snd_soc_dai_ops fsl_mqs_dai_ops = { 152 .startup = fsl_mqs_startup, 153 .shutdown = fsl_mqs_shutdown, 154 .hw_params = fsl_mqs_hw_params, 155 .set_fmt = fsl_mqs_set_dai_fmt, 156}; 157 158static struct snd_soc_dai_driver fsl_mqs_dai = { 159 .name = "fsl-mqs-dai", 160 .playback = { 161 .stream_name = "Playback", 162 .channels_min = 2, 163 .channels_max = 2, 164 .rates = FSL_MQS_RATES, 165 .formats = FSL_MQS_FORMATS, 166 }, 167 .ops = &fsl_mqs_dai_ops, 168}; 169 170static const struct regmap_config fsl_mqs_regmap_config = { 171 .reg_bits = 32, 172 .reg_stride = 4, 173 .val_bits = 32, 174 .max_register = REG_MQS_CTRL, 175 .cache_type = REGCACHE_NONE, 176}; 177 178static int fsl_mqs_probe(struct platform_device *pdev) 179{ 180 struct device_node *np = pdev->dev.of_node; 181 struct device_node *gpr_np = NULL; 182 struct fsl_mqs *mqs_priv; 183 void __iomem *regs; 184 int ret; 185 186 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL); 187 if (!mqs_priv) 188 return -ENOMEM; 189 190 /* On i.MX6sx the MQS control register is in GPR domain 191 * But in i.MX8QM/i.MX8QXP the control register is moved 192 * to its own domain. 193 */ 194 if (of_device_is_compatible(np, "fsl,imx8qm-mqs")) 195 mqs_priv->use_gpr = false; 196 else 197 mqs_priv->use_gpr = true; 198 199 if (mqs_priv->use_gpr) { 200 gpr_np = of_parse_phandle(np, "gpr", 0); 201 if (!gpr_np) { 202 dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); 203 return -EINVAL; 204 } 205 206 mqs_priv->regmap = syscon_node_to_regmap(gpr_np); 207 of_node_put(gpr_np); 208 if (IS_ERR(mqs_priv->regmap)) { 209 dev_err(&pdev->dev, "failed to get gpr regmap\n"); 210 return PTR_ERR(mqs_priv->regmap); 211 } 212 } else { 213 regs = devm_platform_ioremap_resource(pdev, 0); 214 if (IS_ERR(regs)) 215 return PTR_ERR(regs); 216 217 mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 218 "core", 219 regs, 220 &fsl_mqs_regmap_config); 221 if (IS_ERR(mqs_priv->regmap)) { 222 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 223 PTR_ERR(mqs_priv->regmap)); 224 return PTR_ERR(mqs_priv->regmap); 225 } 226 227 mqs_priv->ipg = devm_clk_get(&pdev->dev, "core"); 228 if (IS_ERR(mqs_priv->ipg)) { 229 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 230 PTR_ERR(mqs_priv->ipg)); 231 return PTR_ERR(mqs_priv->ipg); 232 } 233 } 234 235 mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk"); 236 if (IS_ERR(mqs_priv->mclk)) { 237 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 238 PTR_ERR(mqs_priv->mclk)); 239 return PTR_ERR(mqs_priv->mclk); 240 } 241 242 dev_set_drvdata(&pdev->dev, mqs_priv); 243 pm_runtime_enable(&pdev->dev); 244 245 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs, 246 &fsl_mqs_dai, 1); 247 if (ret) 248 return ret; 249 250 return 0; 251} 252 253static int fsl_mqs_remove(struct platform_device *pdev) 254{ 255 pm_runtime_disable(&pdev->dev); 256 return 0; 257} 258 259#ifdef CONFIG_PM 260static int fsl_mqs_runtime_resume(struct device *dev) 261{ 262 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 263 int ret; 264 265 ret = clk_prepare_enable(mqs_priv->ipg); 266 if (ret) { 267 dev_err(dev, "failed to enable ipg clock\n"); 268 return ret; 269 } 270 271 ret = clk_prepare_enable(mqs_priv->mclk); 272 if (ret) { 273 dev_err(dev, "failed to enable mclk clock\n"); 274 clk_disable_unprepare(mqs_priv->ipg); 275 return ret; 276 } 277 278 if (mqs_priv->use_gpr) 279 regmap_write(mqs_priv->regmap, IOMUXC_GPR2, 280 mqs_priv->reg_iomuxc_gpr2); 281 else 282 regmap_write(mqs_priv->regmap, REG_MQS_CTRL, 283 mqs_priv->reg_mqs_ctrl); 284 return 0; 285} 286 287static int fsl_mqs_runtime_suspend(struct device *dev) 288{ 289 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 290 291 if (mqs_priv->use_gpr) 292 regmap_read(mqs_priv->regmap, IOMUXC_GPR2, 293 &mqs_priv->reg_iomuxc_gpr2); 294 else 295 regmap_read(mqs_priv->regmap, REG_MQS_CTRL, 296 &mqs_priv->reg_mqs_ctrl); 297 298 clk_disable_unprepare(mqs_priv->mclk); 299 clk_disable_unprepare(mqs_priv->ipg); 300 301 return 0; 302} 303#endif 304 305static const struct dev_pm_ops fsl_mqs_pm_ops = { 306 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend, 307 fsl_mqs_runtime_resume, 308 NULL) 309 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 310 pm_runtime_force_resume) 311}; 312 313static const struct of_device_id fsl_mqs_dt_ids[] = { 314 { .compatible = "fsl,imx8qm-mqs", }, 315 { .compatible = "fsl,imx6sx-mqs", }, 316 {} 317}; 318MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); 319 320static struct platform_driver fsl_mqs_driver = { 321 .probe = fsl_mqs_probe, 322 .remove = fsl_mqs_remove, 323 .driver = { 324 .name = "fsl-mqs", 325 .of_match_table = fsl_mqs_dt_ids, 326 .pm = &fsl_mqs_pm_ops, 327 }, 328}; 329 330module_platform_driver(fsl_mqs_driver); 331 332MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>"); 333MODULE_DESCRIPTION("MQS codec driver"); 334MODULE_LICENSE("GPL v2"); 335MODULE_ALIAS("platform:fsl-mqs"); 336