1// SPDX-License-Identifier: GPL-2.0 2// 3// Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver 4// 5// Copyright (C) 2014 Freescale Semiconductor, Inc. 6 7#include <linux/clk.h> 8#include <linux/dmaengine.h> 9#include <linux/module.h> 10#include <linux/of_irq.h> 11#include <linux/of_platform.h> 12#include <linux/pm_runtime.h> 13#include <sound/dmaengine_pcm.h> 14#include <sound/pcm_params.h> 15 16#include "fsl_esai.h" 17#include "imx-pcm.h" 18 19#define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 20 SNDRV_PCM_FMTBIT_S16_LE | \ 21 SNDRV_PCM_FMTBIT_S20_3LE | \ 22 SNDRV_PCM_FMTBIT_S24_LE) 23 24/** 25 * struct fsl_esai_soc_data - soc specific data 26 * @imx: for imx platform 27 * @reset_at_xrun: flags for enable reset operaton 28 */ 29struct fsl_esai_soc_data { 30 bool imx; 31 bool reset_at_xrun; 32}; 33 34/** 35 * struct fsl_esai - ESAI private data 36 * @dma_params_rx: DMA parameters for receive channel 37 * @dma_params_tx: DMA parameters for transmit channel 38 * @pdev: platform device pointer 39 * @regmap: regmap handler 40 * @coreclk: clock source to access register 41 * @extalclk: esai clock source to derive HCK, SCK and FS 42 * @fsysclk: system clock source to derive HCK, SCK and FS 43 * @spbaclk: SPBA clock (optional, depending on SoC design) 44 * @work: work to handle the reset operation 45 * @soc: soc specific data 46 * @lock: spin lock between hw_reset() and trigger() 47 * @fifo_depth: depth of tx/rx FIFO 48 * @slot_width: width of each DAI slot 49 * @slots: number of slots 50 * @tx_mask: slot mask for TX 51 * @rx_mask: slot mask for RX 52 * @channels: channel num for tx or rx 53 * @hck_rate: clock rate of desired HCKx clock 54 * @sck_rate: clock rate of desired SCKx clock 55 * @hck_dir: the direction of HCKx pads 56 * @sck_div: if using PSR/PM dividers for SCKx clock 57 * @slave_mode: if fully using DAI slave mode 58 * @synchronous: if using tx/rx synchronous mode 59 * @name: driver name 60 */ 61struct fsl_esai { 62 struct snd_dmaengine_dai_dma_data dma_params_rx; 63 struct snd_dmaengine_dai_dma_data dma_params_tx; 64 struct platform_device *pdev; 65 struct regmap *regmap; 66 struct clk *coreclk; 67 struct clk *extalclk; 68 struct clk *fsysclk; 69 struct clk *spbaclk; 70 struct work_struct work; 71 const struct fsl_esai_soc_data *soc; 72 spinlock_t lock; /* Protect hw_reset and trigger */ 73 u32 fifo_depth; 74 u32 slot_width; 75 u32 slots; 76 u32 tx_mask; 77 u32 rx_mask; 78 u32 channels[2]; 79 u32 hck_rate[2]; 80 u32 sck_rate[2]; 81 bool hck_dir[2]; 82 bool sck_div[2]; 83 bool slave_mode; 84 bool synchronous; 85 char name[32]; 86}; 87 88static struct fsl_esai_soc_data fsl_esai_vf610 = { 89 .imx = false, 90 .reset_at_xrun = true, 91}; 92 93static struct fsl_esai_soc_data fsl_esai_imx35 = { 94 .imx = true, 95 .reset_at_xrun = true, 96}; 97 98static struct fsl_esai_soc_data fsl_esai_imx6ull = { 99 .imx = true, 100 .reset_at_xrun = false, 101}; 102 103static irqreturn_t esai_isr(int irq, void *devid) 104{ 105 struct fsl_esai *esai_priv = (struct fsl_esai *)devid; 106 struct platform_device *pdev = esai_priv->pdev; 107 u32 esr; 108 u32 saisr; 109 110 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr); 111 regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr); 112 113 if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) && 114 esai_priv->soc->reset_at_xrun) { 115 dev_dbg(&pdev->dev, "reset module for xrun\n"); 116 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 117 ESAI_xCR_xEIE_MASK, 0); 118 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 119 ESAI_xCR_xEIE_MASK, 0); 120 schedule_work(&esai_priv->work); 121 } 122 123 if (esr & ESAI_ESR_TINIT_MASK) 124 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n"); 125 126 if (esr & ESAI_ESR_RFF_MASK) 127 dev_warn(&pdev->dev, "isr: Receiving overrun\n"); 128 129 if (esr & ESAI_ESR_TFE_MASK) 130 dev_warn(&pdev->dev, "isr: Transmission underrun\n"); 131 132 if (esr & ESAI_ESR_TLS_MASK) 133 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n"); 134 135 if (esr & ESAI_ESR_TDE_MASK) 136 dev_dbg(&pdev->dev, "isr: Transmission data exception\n"); 137 138 if (esr & ESAI_ESR_TED_MASK) 139 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n"); 140 141 if (esr & ESAI_ESR_TD_MASK) 142 dev_dbg(&pdev->dev, "isr: Transmitting data\n"); 143 144 if (esr & ESAI_ESR_RLS_MASK) 145 dev_dbg(&pdev->dev, "isr: Just received the last slot\n"); 146 147 if (esr & ESAI_ESR_RDE_MASK) 148 dev_dbg(&pdev->dev, "isr: Receiving data exception\n"); 149 150 if (esr & ESAI_ESR_RED_MASK) 151 dev_dbg(&pdev->dev, "isr: Receiving even slots\n"); 152 153 if (esr & ESAI_ESR_RD_MASK) 154 dev_dbg(&pdev->dev, "isr: Receiving data\n"); 155 156 return IRQ_HANDLED; 157} 158 159/** 160 * fsl_esai_divisor_cal - This function is used to calculate the 161 * divisors of psr, pm, fp and it is supposed to be called in 162 * set_dai_sysclk() and set_bclk(). 163 * 164 * @dai: pointer to DAI 165 * @tx: current setting is for playback or capture 166 * @ratio: desired overall ratio for the paticipating dividers 167 * @usefp: for HCK setting, there is no need to set fp divider 168 * @fp: bypass other dividers by setting fp directly if fp != 0 169 */ 170static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio, 171 bool usefp, u32 fp) 172{ 173 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 174 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j; 175 176 maxfp = usefp ? 16 : 1; 177 178 if (usefp && fp) 179 goto out_fp; 180 181 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) { 182 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n", 183 2 * 8 * 256 * maxfp); 184 return -EINVAL; 185 } else if (ratio % 2) { 186 dev_err(dai->dev, "the raio must be even if using upper divider\n"); 187 return -EINVAL; 188 } 189 190 ratio /= 2; 191 192 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8; 193 194 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */ 195 if (ratio <= 256) { 196 pm = ratio; 197 fp = 1; 198 goto out; 199 } 200 201 /* Set the max fluctuation -- 0.1% of the max devisor */ 202 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000; 203 204 /* Find the best value for PM */ 205 for (i = 1; i <= 256; i++) { 206 for (j = 1; j <= maxfp; j++) { 207 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */ 208 prod = (psr ? 1 : 8) * i * j; 209 210 if (prod == ratio) 211 sub = 0; 212 else if (prod / ratio == 1) 213 sub = prod - ratio; 214 else if (ratio / prod == 1) 215 sub = ratio - prod; 216 else 217 continue; 218 219 /* Calculate the fraction */ 220 sub = sub * 1000 / ratio; 221 if (sub < savesub) { 222 savesub = sub; 223 pm = i; 224 fp = j; 225 } 226 227 /* We are lucky */ 228 if (savesub == 0) 229 goto out; 230 } 231 } 232 233 if (pm == 999) { 234 dev_err(dai->dev, "failed to calculate proper divisors\n"); 235 return -EINVAL; 236 } 237 238out: 239 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 240 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK, 241 psr | ESAI_xCCR_xPM(pm)); 242 243out_fp: 244 /* Bypass fp if not being required */ 245 if (maxfp <= 1) 246 return 0; 247 248 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 249 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp)); 250 251 return 0; 252} 253 254/** 255 * fsl_esai_set_dai_sysclk - configure the clock frequency of MCLK (HCKT/HCKR) 256 * @dai: pointer to DAI 257 * @clk_id: The clock source of HCKT/HCKR 258 * (Input from outside; output from inside, FSYS or EXTAL) 259 * @freq: The required clock rate of HCKT/HCKR 260 * @dir: The clock direction of HCKT/HCKR 261 * 262 * Note: If the direction is input, we do not care about clk_id. 263 */ 264static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 265 unsigned int freq, int dir) 266{ 267 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 268 struct clk *clksrc = esai_priv->extalclk; 269 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous); 270 bool in = dir == SND_SOC_CLOCK_IN; 271 u32 ratio, ecr = 0; 272 unsigned long clk_rate; 273 int ret; 274 275 if (freq == 0) { 276 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n", 277 in ? "in" : "out", tx ? 'T' : 'R'); 278 return -EINVAL; 279 } 280 281 /* Bypass divider settings if the requirement doesn't change */ 282 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx]) 283 return 0; 284 285 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */ 286 esai_priv->sck_div[tx] = true; 287 288 /* Set the direction of HCKT/HCKR pins */ 289 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 290 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD); 291 292 if (in) 293 goto out; 294 295 switch (clk_id) { 296 case ESAI_HCKT_FSYS: 297 case ESAI_HCKR_FSYS: 298 clksrc = esai_priv->fsysclk; 299 break; 300 case ESAI_HCKT_EXTAL: 301 ecr |= ESAI_ECR_ETI; 302 break; 303 case ESAI_HCKR_EXTAL: 304 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI; 305 break; 306 default: 307 return -EINVAL; 308 } 309 310 if (IS_ERR(clksrc)) { 311 dev_err(dai->dev, "no assigned %s clock\n", 312 clk_id % 2 ? "extal" : "fsys"); 313 return PTR_ERR(clksrc); 314 } 315 clk_rate = clk_get_rate(clksrc); 316 317 ratio = clk_rate / freq; 318 if (ratio * freq > clk_rate) 319 ret = ratio * freq - clk_rate; 320 else if (ratio * freq < clk_rate) 321 ret = clk_rate - ratio * freq; 322 else 323 ret = 0; 324 325 /* Block if clock source can not be divided into the required rate */ 326 if (ret != 0 && clk_rate / ret < 1000) { 327 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 328 tx ? 'T' : 'R'); 329 return -EINVAL; 330 } 331 332 /* Only EXTAL source can be output directly without using PSR and PM */ 333 if (ratio == 1 && clksrc == esai_priv->extalclk) { 334 /* Bypass all the dividers if not being needed */ 335 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO; 336 goto out; 337 } else if (ratio < 2) { 338 /* The ratio should be no less than 2 if using other sources */ 339 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 340 tx ? 'T' : 'R'); 341 return -EINVAL; 342 } 343 344 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0); 345 if (ret) 346 return ret; 347 348 esai_priv->sck_div[tx] = false; 349 350out: 351 esai_priv->hck_dir[tx] = dir; 352 esai_priv->hck_rate[tx] = freq; 353 354 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 355 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO : 356 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr); 357 358 return 0; 359} 360 361/** 362 * fsl_esai_set_bclk - configure the related dividers according to the bclk rate 363 * @dai: pointer to DAI 364 * @tx: direction boolean 365 * @freq: bclk freq 366 */ 367static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 368{ 369 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 370 u32 hck_rate = esai_priv->hck_rate[tx]; 371 u32 sub, ratio = hck_rate / freq; 372 int ret; 373 374 /* Don't apply for fully slave mode or unchanged bclk */ 375 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq) 376 return 0; 377 378 if (ratio * freq > hck_rate) 379 sub = ratio * freq - hck_rate; 380 else if (ratio * freq < hck_rate) 381 sub = hck_rate - ratio * freq; 382 else 383 sub = 0; 384 385 /* Block if clock source can not be divided into the required rate */ 386 if (sub != 0 && hck_rate / sub < 1000) { 387 dev_err(dai->dev, "failed to derive required SCK%c rate\n", 388 tx ? 'T' : 'R'); 389 return -EINVAL; 390 } 391 392 /* The ratio should be contented by FP alone if bypassing PM and PSR */ 393 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) { 394 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n"); 395 return -EINVAL; 396 } 397 398 ret = fsl_esai_divisor_cal(dai, tx, ratio, true, 399 esai_priv->sck_div[tx] ? 0 : ratio); 400 if (ret) 401 return ret; 402 403 /* Save current bclk rate */ 404 esai_priv->sck_rate[tx] = freq; 405 406 return 0; 407} 408 409static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 410 u32 rx_mask, int slots, int slot_width) 411{ 412 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 413 414 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 415 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 416 417 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 418 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 419 420 esai_priv->slot_width = slot_width; 421 esai_priv->slots = slots; 422 esai_priv->tx_mask = tx_mask; 423 esai_priv->rx_mask = rx_mask; 424 425 return 0; 426} 427 428static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 429{ 430 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 431 u32 xcr = 0, xccr = 0, mask; 432 433 /* DAI mode */ 434 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 435 case SND_SOC_DAIFMT_I2S: 436 /* Data on rising edge of bclk, frame low, 1clk before data */ 437 xcr |= ESAI_xCR_xFSR; 438 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 439 break; 440 case SND_SOC_DAIFMT_LEFT_J: 441 /* Data on rising edge of bclk, frame high */ 442 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 443 break; 444 case SND_SOC_DAIFMT_RIGHT_J: 445 /* Data on rising edge of bclk, frame high, right aligned */ 446 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 447 xcr |= ESAI_xCR_xWA; 448 break; 449 case SND_SOC_DAIFMT_DSP_A: 450 /* Data on rising edge of bclk, frame high, 1clk before data */ 451 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR; 452 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 453 break; 454 case SND_SOC_DAIFMT_DSP_B: 455 /* Data on rising edge of bclk, frame high */ 456 xcr |= ESAI_xCR_xFSL; 457 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 458 break; 459 default: 460 return -EINVAL; 461 } 462 463 /* DAI clock inversion */ 464 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 465 case SND_SOC_DAIFMT_NB_NF: 466 /* Nothing to do for both normal cases */ 467 break; 468 case SND_SOC_DAIFMT_IB_NF: 469 /* Invert bit clock */ 470 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 471 break; 472 case SND_SOC_DAIFMT_NB_IF: 473 /* Invert frame clock */ 474 xccr ^= ESAI_xCCR_xFSP; 475 break; 476 case SND_SOC_DAIFMT_IB_IF: 477 /* Invert both clocks */ 478 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP; 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 esai_priv->slave_mode = false; 485 486 /* DAI clock master masks */ 487 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 488 case SND_SOC_DAIFMT_CBM_CFM: 489 esai_priv->slave_mode = true; 490 break; 491 case SND_SOC_DAIFMT_CBS_CFM: 492 xccr |= ESAI_xCCR_xCKD; 493 break; 494 case SND_SOC_DAIFMT_CBM_CFS: 495 xccr |= ESAI_xCCR_xFSD; 496 break; 497 case SND_SOC_DAIFMT_CBS_CFS: 498 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 499 break; 500 default: 501 return -EINVAL; 502 } 503 504 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA; 505 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr); 506 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr); 507 508 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | 509 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 510 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr); 511 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr); 512 513 return 0; 514} 515 516static int fsl_esai_startup(struct snd_pcm_substream *substream, 517 struct snd_soc_dai *dai) 518{ 519 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 520 521 if (!snd_soc_dai_active(dai)) { 522 /* Set synchronous mode */ 523 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR, 524 ESAI_SAICR_SYNC, esai_priv->synchronous ? 525 ESAI_SAICR_SYNC : 0); 526 527 /* Set slots count */ 528 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 529 ESAI_xCCR_xDC_MASK, 530 ESAI_xCCR_xDC(esai_priv->slots)); 531 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 532 ESAI_xCCR_xDC_MASK, 533 ESAI_xCCR_xDC(esai_priv->slots)); 534 } 535 536 return 0; 537 538} 539 540static int fsl_esai_hw_params(struct snd_pcm_substream *substream, 541 struct snd_pcm_hw_params *params, 542 struct snd_soc_dai *dai) 543{ 544 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 545 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 546 u32 width = params_width(params); 547 u32 channels = params_channels(params); 548 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 549 u32 slot_width = width; 550 u32 bclk, mask, val; 551 int ret; 552 553 /* Override slot_width if being specifically set */ 554 if (esai_priv->slot_width) 555 slot_width = esai_priv->slot_width; 556 557 bclk = params_rate(params) * slot_width * esai_priv->slots; 558 559 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk); 560 if (ret) 561 return ret; 562 563 mask = ESAI_xCR_xSWS_MASK; 564 val = ESAI_xCR_xSWS(slot_width, width); 565 566 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); 567 /* Recording in synchronous mode needs to set TCR also */ 568 if (!tx && esai_priv->synchronous) 569 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val); 570 571 /* Use Normal mode to support monaural audio */ 572 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 573 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ? 574 ESAI_xCR_xMOD_NETWORK : 0); 575 576 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 577 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR); 578 579 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | 580 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); 581 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | 582 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins)); 583 584 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); 585 586 if (tx) 587 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 588 ESAI_xCR_PADC, ESAI_xCR_PADC); 589 590 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */ 591 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 592 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 593 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 594 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 595 return 0; 596} 597 598static int fsl_esai_hw_init(struct fsl_esai *esai_priv) 599{ 600 struct platform_device *pdev = esai_priv->pdev; 601 int ret; 602 603 /* Reset ESAI unit */ 604 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 605 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK, 606 ESAI_ECR_ESAIEN | ESAI_ECR_ERST); 607 if (ret) { 608 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret); 609 return ret; 610 } 611 612 /* 613 * We need to enable ESAI so as to access some of its registers. 614 * Otherwise, we would fail to dump regmap from user space. 615 */ 616 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 617 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK, 618 ESAI_ECR_ESAIEN); 619 if (ret) { 620 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret); 621 return ret; 622 } 623 624 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 625 ESAI_PRRC_PDC_MASK, 0); 626 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 627 ESAI_PCRC_PC_MASK, 0); 628 629 return 0; 630} 631 632static int fsl_esai_register_restore(struct fsl_esai *esai_priv) 633{ 634 int ret; 635 636 /* FIFO reset for safety */ 637 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, 638 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 639 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, 640 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 641 642 regcache_mark_dirty(esai_priv->regmap); 643 ret = regcache_sync(esai_priv->regmap); 644 if (ret) 645 return ret; 646 647 /* FIFO reset done */ 648 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0); 649 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0); 650 651 return 0; 652} 653 654static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx) 655{ 656 u8 i, channels = esai_priv->channels[tx]; 657 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 658 u32 mask; 659 660 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 661 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN); 662 663 /* Write initial words reqiured by ESAI as normal procedure */ 664 for (i = 0; tx && i < channels; i++) 665 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0); 666 667 /* 668 * When set the TE/RE in the end of enablement flow, there 669 * will be channel swap issue for multi data line case. 670 * In order to workaround this issue, we switch the bit 671 * enablement sequence to below sequence 672 * 1) clear the xSMB & xSMA: which is done in probe and 673 * stop state. 674 * 2) set TE/RE 675 * 3) set xSMB 676 * 4) set xSMA: xSMA is the last one in this flow, which 677 * will trigger esai to start. 678 */ 679 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 680 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 681 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins)); 682 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask; 683 684 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 685 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask)); 686 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 687 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask)); 688 689 /* Enable Exception interrupt */ 690 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 691 ESAI_xCR_xEIE_MASK, ESAI_xCR_xEIE); 692} 693 694static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx) 695{ 696 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 697 ESAI_xCR_xEIE_MASK, 0); 698 699 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 700 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0); 701 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 702 ESAI_xSMA_xS_MASK, 0); 703 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 704 ESAI_xSMB_xS_MASK, 0); 705 706 /* Disable and reset FIFO */ 707 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 708 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR); 709 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 710 ESAI_xFCR_xFR, 0); 711} 712 713static void fsl_esai_hw_reset(struct work_struct *work) 714{ 715 struct fsl_esai *esai_priv = container_of(work, struct fsl_esai, work); 716 bool tx = true, rx = false, enabled[2]; 717 unsigned long lock_flags; 718 u32 tfcr, rfcr; 719 720 spin_lock_irqsave(&esai_priv->lock, lock_flags); 721 /* Save the registers */ 722 regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr); 723 regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr); 724 enabled[tx] = tfcr & ESAI_xFCR_xFEN; 725 enabled[rx] = rfcr & ESAI_xFCR_xFEN; 726 727 /* Stop the tx & rx */ 728 fsl_esai_trigger_stop(esai_priv, tx); 729 fsl_esai_trigger_stop(esai_priv, rx); 730 731 /* Reset the esai, and ignore return value */ 732 fsl_esai_hw_init(esai_priv); 733 734 /* Enforce ESAI personal resets for both TX and RX */ 735 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 736 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR); 737 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 738 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR); 739 740 /* Restore registers by regcache_sync, and ignore return value */ 741 fsl_esai_register_restore(esai_priv); 742 743 /* Remove ESAI personal resets by configuring PCRC and PRRC also */ 744 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 745 ESAI_xCR_xPR_MASK, 0); 746 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 747 ESAI_xCR_xPR_MASK, 0); 748 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 749 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 750 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 751 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 752 753 /* Restart tx / rx, if they already enabled */ 754 if (enabled[tx]) 755 fsl_esai_trigger_start(esai_priv, tx); 756 if (enabled[rx]) 757 fsl_esai_trigger_start(esai_priv, rx); 758 759 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 760} 761 762static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, 763 struct snd_soc_dai *dai) 764{ 765 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 766 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 767 unsigned long lock_flags; 768 769 esai_priv->channels[tx] = substream->runtime->channels; 770 771 switch (cmd) { 772 case SNDRV_PCM_TRIGGER_START: 773 case SNDRV_PCM_TRIGGER_RESUME: 774 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 775 spin_lock_irqsave(&esai_priv->lock, lock_flags); 776 fsl_esai_trigger_start(esai_priv, tx); 777 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 778 break; 779 case SNDRV_PCM_TRIGGER_SUSPEND: 780 case SNDRV_PCM_TRIGGER_STOP: 781 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 782 spin_lock_irqsave(&esai_priv->lock, lock_flags); 783 fsl_esai_trigger_stop(esai_priv, tx); 784 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 785 break; 786 default: 787 return -EINVAL; 788 } 789 790 return 0; 791} 792 793static const struct snd_soc_dai_ops fsl_esai_dai_ops = { 794 .startup = fsl_esai_startup, 795 .trigger = fsl_esai_trigger, 796 .hw_params = fsl_esai_hw_params, 797 .set_sysclk = fsl_esai_set_dai_sysclk, 798 .set_fmt = fsl_esai_set_dai_fmt, 799 .set_tdm_slot = fsl_esai_set_dai_tdm_slot, 800}; 801 802static int fsl_esai_dai_probe(struct snd_soc_dai *dai) 803{ 804 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 805 806 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx, 807 &esai_priv->dma_params_rx); 808 809 return 0; 810} 811 812static struct snd_soc_dai_driver fsl_esai_dai = { 813 .probe = fsl_esai_dai_probe, 814 .playback = { 815 .stream_name = "CPU-Playback", 816 .channels_min = 1, 817 .channels_max = 12, 818 .rates = SNDRV_PCM_RATE_8000_192000, 819 .formats = FSL_ESAI_FORMATS, 820 }, 821 .capture = { 822 .stream_name = "CPU-Capture", 823 .channels_min = 1, 824 .channels_max = 8, 825 .rates = SNDRV_PCM_RATE_8000_192000, 826 .formats = FSL_ESAI_FORMATS, 827 }, 828 .ops = &fsl_esai_dai_ops, 829}; 830 831static const struct snd_soc_component_driver fsl_esai_component = { 832 .name = "fsl-esai", 833}; 834 835static const struct reg_default fsl_esai_reg_defaults[] = { 836 {REG_ESAI_ETDR, 0x00000000}, 837 {REG_ESAI_ECR, 0x00000000}, 838 {REG_ESAI_TFCR, 0x00000000}, 839 {REG_ESAI_RFCR, 0x00000000}, 840 {REG_ESAI_TX0, 0x00000000}, 841 {REG_ESAI_TX1, 0x00000000}, 842 {REG_ESAI_TX2, 0x00000000}, 843 {REG_ESAI_TX3, 0x00000000}, 844 {REG_ESAI_TX4, 0x00000000}, 845 {REG_ESAI_TX5, 0x00000000}, 846 {REG_ESAI_TSR, 0x00000000}, 847 {REG_ESAI_SAICR, 0x00000000}, 848 {REG_ESAI_TCR, 0x00000000}, 849 {REG_ESAI_TCCR, 0x00000000}, 850 {REG_ESAI_RCR, 0x00000000}, 851 {REG_ESAI_RCCR, 0x00000000}, 852 {REG_ESAI_TSMA, 0x0000ffff}, 853 {REG_ESAI_TSMB, 0x0000ffff}, 854 {REG_ESAI_RSMA, 0x0000ffff}, 855 {REG_ESAI_RSMB, 0x0000ffff}, 856 {REG_ESAI_PRRC, 0x00000000}, 857 {REG_ESAI_PCRC, 0x00000000}, 858}; 859 860static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg) 861{ 862 switch (reg) { 863 case REG_ESAI_ERDR: 864 case REG_ESAI_ECR: 865 case REG_ESAI_ESR: 866 case REG_ESAI_TFCR: 867 case REG_ESAI_TFSR: 868 case REG_ESAI_RFCR: 869 case REG_ESAI_RFSR: 870 case REG_ESAI_RX0: 871 case REG_ESAI_RX1: 872 case REG_ESAI_RX2: 873 case REG_ESAI_RX3: 874 case REG_ESAI_SAISR: 875 case REG_ESAI_SAICR: 876 case REG_ESAI_TCR: 877 case REG_ESAI_TCCR: 878 case REG_ESAI_RCR: 879 case REG_ESAI_RCCR: 880 case REG_ESAI_TSMA: 881 case REG_ESAI_TSMB: 882 case REG_ESAI_RSMA: 883 case REG_ESAI_RSMB: 884 case REG_ESAI_PRRC: 885 case REG_ESAI_PCRC: 886 return true; 887 default: 888 return false; 889 } 890} 891 892static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg) 893{ 894 switch (reg) { 895 case REG_ESAI_ERDR: 896 case REG_ESAI_ESR: 897 case REG_ESAI_TFSR: 898 case REG_ESAI_RFSR: 899 case REG_ESAI_RX0: 900 case REG_ESAI_RX1: 901 case REG_ESAI_RX2: 902 case REG_ESAI_RX3: 903 case REG_ESAI_SAISR: 904 return true; 905 default: 906 return false; 907 } 908} 909 910static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) 911{ 912 switch (reg) { 913 case REG_ESAI_ETDR: 914 case REG_ESAI_ECR: 915 case REG_ESAI_TFCR: 916 case REG_ESAI_RFCR: 917 case REG_ESAI_TX0: 918 case REG_ESAI_TX1: 919 case REG_ESAI_TX2: 920 case REG_ESAI_TX3: 921 case REG_ESAI_TX4: 922 case REG_ESAI_TX5: 923 case REG_ESAI_TSR: 924 case REG_ESAI_SAICR: 925 case REG_ESAI_TCR: 926 case REG_ESAI_TCCR: 927 case REG_ESAI_RCR: 928 case REG_ESAI_RCCR: 929 case REG_ESAI_TSMA: 930 case REG_ESAI_TSMB: 931 case REG_ESAI_RSMA: 932 case REG_ESAI_RSMB: 933 case REG_ESAI_PRRC: 934 case REG_ESAI_PCRC: 935 return true; 936 default: 937 return false; 938 } 939} 940 941static const struct regmap_config fsl_esai_regmap_config = { 942 .reg_bits = 32, 943 .reg_stride = 4, 944 .val_bits = 32, 945 946 .max_register = REG_ESAI_PCRC, 947 .reg_defaults = fsl_esai_reg_defaults, 948 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults), 949 .readable_reg = fsl_esai_readable_reg, 950 .volatile_reg = fsl_esai_volatile_reg, 951 .writeable_reg = fsl_esai_writeable_reg, 952 .cache_type = REGCACHE_FLAT, 953}; 954 955static int fsl_esai_probe(struct platform_device *pdev) 956{ 957 struct device_node *np = pdev->dev.of_node; 958 struct fsl_esai *esai_priv; 959 struct resource *res; 960 const __be32 *iprop; 961 void __iomem *regs; 962 int irq, ret; 963 964 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL); 965 if (!esai_priv) 966 return -ENOMEM; 967 968 esai_priv->pdev = pdev; 969 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np); 970 971 esai_priv->soc = of_device_get_match_data(&pdev->dev); 972 if (!esai_priv->soc) { 973 dev_err(&pdev->dev, "failed to get soc data\n"); 974 return -ENODEV; 975 } 976 977 /* Get the addresses and IRQ */ 978 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 979 regs = devm_ioremap_resource(&pdev->dev, res); 980 if (IS_ERR(regs)) 981 return PTR_ERR(regs); 982 983 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 984 "core", regs, &fsl_esai_regmap_config); 985 if (IS_ERR(esai_priv->regmap)) { 986 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 987 PTR_ERR(esai_priv->regmap)); 988 return PTR_ERR(esai_priv->regmap); 989 } 990 991 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 992 if (IS_ERR(esai_priv->coreclk)) { 993 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 994 PTR_ERR(esai_priv->coreclk)); 995 return PTR_ERR(esai_priv->coreclk); 996 } 997 998 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal"); 999 if (IS_ERR(esai_priv->extalclk)) 1000 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n", 1001 PTR_ERR(esai_priv->extalclk)); 1002 1003 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys"); 1004 if (IS_ERR(esai_priv->fsysclk)) 1005 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n", 1006 PTR_ERR(esai_priv->fsysclk)); 1007 1008 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1009 if (IS_ERR(esai_priv->spbaclk)) 1010 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n", 1011 PTR_ERR(esai_priv->spbaclk)); 1012 1013 irq = platform_get_irq(pdev, 0); 1014 if (irq < 0) 1015 return irq; 1016 1017 ret = devm_request_irq(&pdev->dev, irq, esai_isr, IRQF_SHARED, 1018 esai_priv->name, esai_priv); 1019 if (ret) { 1020 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 1021 return ret; 1022 } 1023 1024 /* Set a default slot number */ 1025 esai_priv->slots = 2; 1026 1027 /* Set a default master/slave state */ 1028 esai_priv->slave_mode = true; 1029 1030 /* Determine the FIFO depth */ 1031 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1032 if (iprop) 1033 esai_priv->fifo_depth = be32_to_cpup(iprop); 1034 else 1035 esai_priv->fifo_depth = 64; 1036 1037 esai_priv->dma_params_tx.maxburst = 16; 1038 esai_priv->dma_params_rx.maxburst = 16; 1039 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR; 1040 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR; 1041 1042 esai_priv->synchronous = 1043 of_property_read_bool(np, "fsl,esai-synchronous"); 1044 1045 /* Implement full symmetry for synchronous mode */ 1046 if (esai_priv->synchronous) { 1047 fsl_esai_dai.symmetric_rates = 1; 1048 fsl_esai_dai.symmetric_channels = 1; 1049 fsl_esai_dai.symmetric_samplebits = 1; 1050 } 1051 1052 dev_set_drvdata(&pdev->dev, esai_priv); 1053 1054 spin_lock_init(&esai_priv->lock); 1055 ret = fsl_esai_hw_init(esai_priv); 1056 if (ret) 1057 return ret; 1058 1059 esai_priv->tx_mask = 0xFFFFFFFF; 1060 esai_priv->rx_mask = 0xFFFFFFFF; 1061 1062 /* Clear the TSMA, TSMB, RSMA, RSMB */ 1063 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0); 1064 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0); 1065 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0); 1066 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0); 1067 1068 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component, 1069 &fsl_esai_dai, 1); 1070 if (ret) { 1071 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1072 return ret; 1073 } 1074 1075 INIT_WORK(&esai_priv->work, fsl_esai_hw_reset); 1076 1077 pm_runtime_enable(&pdev->dev); 1078 1079 regcache_cache_only(esai_priv->regmap, true); 1080 1081 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE); 1082 if (ret) 1083 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret); 1084 1085 return ret; 1086} 1087 1088static int fsl_esai_remove(struct platform_device *pdev) 1089{ 1090 struct fsl_esai *esai_priv = platform_get_drvdata(pdev); 1091 1092 pm_runtime_disable(&pdev->dev); 1093 cancel_work_sync(&esai_priv->work); 1094 1095 return 0; 1096} 1097 1098static const struct of_device_id fsl_esai_dt_ids[] = { 1099 { .compatible = "fsl,imx35-esai", .data = &fsl_esai_imx35 }, 1100 { .compatible = "fsl,vf610-esai", .data = &fsl_esai_vf610 }, 1101 { .compatible = "fsl,imx6ull-esai", .data = &fsl_esai_imx6ull }, 1102 {} 1103}; 1104MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids); 1105 1106#ifdef CONFIG_PM 1107static int fsl_esai_runtime_resume(struct device *dev) 1108{ 1109 struct fsl_esai *esai = dev_get_drvdata(dev); 1110 int ret; 1111 1112 /* 1113 * Some platforms might use the same bit to gate all three or two of 1114 * clocks, so keep all clocks open/close at the same time for safety 1115 */ 1116 ret = clk_prepare_enable(esai->coreclk); 1117 if (ret) 1118 return ret; 1119 if (!IS_ERR(esai->spbaclk)) { 1120 ret = clk_prepare_enable(esai->spbaclk); 1121 if (ret) 1122 goto err_spbaclk; 1123 } 1124 if (!IS_ERR(esai->extalclk)) { 1125 ret = clk_prepare_enable(esai->extalclk); 1126 if (ret) 1127 goto err_extalclk; 1128 } 1129 if (!IS_ERR(esai->fsysclk)) { 1130 ret = clk_prepare_enable(esai->fsysclk); 1131 if (ret) 1132 goto err_fsysclk; 1133 } 1134 1135 regcache_cache_only(esai->regmap, false); 1136 1137 ret = fsl_esai_register_restore(esai); 1138 if (ret) 1139 goto err_regcache_sync; 1140 1141 return 0; 1142 1143err_regcache_sync: 1144 if (!IS_ERR(esai->fsysclk)) 1145 clk_disable_unprepare(esai->fsysclk); 1146err_fsysclk: 1147 if (!IS_ERR(esai->extalclk)) 1148 clk_disable_unprepare(esai->extalclk); 1149err_extalclk: 1150 if (!IS_ERR(esai->spbaclk)) 1151 clk_disable_unprepare(esai->spbaclk); 1152err_spbaclk: 1153 clk_disable_unprepare(esai->coreclk); 1154 1155 return ret; 1156} 1157 1158static int fsl_esai_runtime_suspend(struct device *dev) 1159{ 1160 struct fsl_esai *esai = dev_get_drvdata(dev); 1161 1162 regcache_cache_only(esai->regmap, true); 1163 1164 if (!IS_ERR(esai->fsysclk)) 1165 clk_disable_unprepare(esai->fsysclk); 1166 if (!IS_ERR(esai->extalclk)) 1167 clk_disable_unprepare(esai->extalclk); 1168 if (!IS_ERR(esai->spbaclk)) 1169 clk_disable_unprepare(esai->spbaclk); 1170 clk_disable_unprepare(esai->coreclk); 1171 1172 return 0; 1173} 1174#endif /* CONFIG_PM */ 1175 1176static const struct dev_pm_ops fsl_esai_pm_ops = { 1177 SET_RUNTIME_PM_OPS(fsl_esai_runtime_suspend, 1178 fsl_esai_runtime_resume, 1179 NULL) 1180 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1181 pm_runtime_force_resume) 1182}; 1183 1184static struct platform_driver fsl_esai_driver = { 1185 .probe = fsl_esai_probe, 1186 .remove = fsl_esai_remove, 1187 .driver = { 1188 .name = "fsl-esai-dai", 1189 .pm = &fsl_esai_pm_ops, 1190 .of_match_table = fsl_esai_dt_ids, 1191 }, 1192}; 1193 1194module_platform_driver(fsl_esai_driver); 1195 1196MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1197MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver"); 1198MODULE_LICENSE("GPL v2"); 1199MODULE_ALIAS("platform:fsl-esai-dai"); 1200