1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * wm8903.c -- WM8903 ALSA SoC Audio driver 4 * 5 * Copyright 2008-12 Wolfson Microelectronics 6 * Copyright 2011-2012 NVIDIA, Inc. 7 * 8 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 9 * 10 * TODO: 11 * - TDM mode configuration. 12 * - Digital microphone support. 13 */ 14 15#include <linux/module.h> 16#include <linux/moduleparam.h> 17#include <linux/init.h> 18#include <linux/completion.h> 19#include <linux/delay.h> 20#include <linux/gpio/driver.h> 21#include <linux/pm.h> 22#include <linux/i2c.h> 23#include <linux/regmap.h> 24#include <linux/regulator/consumer.h> 25#include <linux/slab.h> 26#include <linux/irq.h> 27#include <linux/mutex.h> 28#include <sound/core.h> 29#include <sound/jack.h> 30#include <sound/pcm.h> 31#include <sound/pcm_params.h> 32#include <sound/tlv.h> 33#include <sound/soc.h> 34#include <sound/initval.h> 35#include <sound/wm8903.h> 36#include <trace/events/asoc.h> 37 38#include "wm8903.h" 39 40/* Register defaults at reset */ 41static const struct reg_default wm8903_reg_defaults[] = { 42 { 4, 0x0018 }, /* R4 - Bias Control 0 */ 43 { 5, 0x0000 }, /* R5 - VMID Control 0 */ 44 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ 45 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ 46 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ 47 { 12, 0x0000 }, /* R12 - Power Management 0 */ 48 { 13, 0x0000 }, /* R13 - Power Management 1 */ 49 { 14, 0x0000 }, /* R14 - Power Management 2 */ 50 { 15, 0x0000 }, /* R15 - Power Management 3 */ 51 { 16, 0x0000 }, /* R16 - Power Management 4 */ 52 { 17, 0x0000 }, /* R17 - Power Management 5 */ 53 { 18, 0x0000 }, /* R18 - Power Management 6 */ 54 { 20, 0x0400 }, /* R20 - Clock Rates 0 */ 55 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */ 56 { 22, 0x0000 }, /* R22 - Clock Rates 2 */ 57 { 24, 0x0050 }, /* R24 - Audio Interface 0 */ 58 { 25, 0x0242 }, /* R25 - Audio Interface 1 */ 59 { 26, 0x0008 }, /* R26 - Audio Interface 2 */ 60 { 27, 0x0022 }, /* R27 - Audio Interface 3 */ 61 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ 62 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ 63 { 32, 0x0000 }, /* R32 - DAC Digital 0 */ 64 { 33, 0x0000 }, /* R33 - DAC Digital 1 */ 65 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ 66 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ 67 { 38, 0x0000 }, /* R38 - ADC Digital 0 */ 68 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */ 69 { 40, 0x09BF }, /* R40 - DRC 0 */ 70 { 41, 0x3241 }, /* R41 - DRC 1 */ 71 { 42, 0x0020 }, /* R42 - DRC 2 */ 72 { 43, 0x0000 }, /* R43 - DRC 3 */ 73 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ 74 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ 75 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ 76 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ 77 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */ 78 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */ 79 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */ 80 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */ 81 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */ 82 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */ 83 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ 84 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ 85 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ 86 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ 87 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */ 88 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */ 89 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */ 90 { 67, 0x0010 }, /* R67 - DC Servo 0 */ 91 { 69, 0x00A4 }, /* R69 - DC Servo 2 */ 92 { 90, 0x0000 }, /* R90 - Analogue HP 0 */ 93 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ 94 { 98, 0x0000 }, /* R98 - Charge Pump 0 */ 95 { 104, 0x0000 }, /* R104 - Class W 0 */ 96 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ 97 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ 98 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ 99 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ 100 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ 101 { 114, 0x0000 }, /* R114 - Control Interface */ 102 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */ 103 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */ 104 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */ 105 { 119, 0x0220 }, /* R119 - GPIO Control 4 */ 106 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */ 107 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */ 108 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */ 109 { 126, 0x0000 }, /* R126 - Interrupt Control */ 110 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */ 111 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */ 112 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */ 113 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */ 114}; 115 116#define WM8903_NUM_SUPPLIES 4 117static const char *wm8903_supply_names[WM8903_NUM_SUPPLIES] = { 118 "AVDD", 119 "CPVDD", 120 "DBVDD", 121 "DCVDD", 122}; 123 124struct wm8903_priv { 125 struct wm8903_platform_data *pdata; 126 struct device *dev; 127 struct regmap *regmap; 128 struct regulator_bulk_data supplies[WM8903_NUM_SUPPLIES]; 129 130 int sysclk; 131 int irq; 132 133 struct mutex lock; 134 int fs; 135 int deemph; 136 137 int dcs_pending; 138 int dcs_cache[4]; 139 140 /* Reference count */ 141 int class_w_users; 142 143 struct snd_soc_jack *mic_jack; 144 int mic_det; 145 int mic_short; 146 int mic_last_report; 147 int mic_delay; 148 149#ifdef CONFIG_GPIOLIB 150 struct gpio_chip gpio_chip; 151#endif 152}; 153 154static bool wm8903_readable_register(struct device *dev, unsigned int reg) 155{ 156 switch (reg) { 157 case WM8903_SW_RESET_AND_ID: 158 case WM8903_REVISION_NUMBER: 159 case WM8903_BIAS_CONTROL_0: 160 case WM8903_VMID_CONTROL_0: 161 case WM8903_MIC_BIAS_CONTROL_0: 162 case WM8903_ANALOGUE_DAC_0: 163 case WM8903_ANALOGUE_ADC_0: 164 case WM8903_POWER_MANAGEMENT_0: 165 case WM8903_POWER_MANAGEMENT_1: 166 case WM8903_POWER_MANAGEMENT_2: 167 case WM8903_POWER_MANAGEMENT_3: 168 case WM8903_POWER_MANAGEMENT_4: 169 case WM8903_POWER_MANAGEMENT_5: 170 case WM8903_POWER_MANAGEMENT_6: 171 case WM8903_CLOCK_RATES_0: 172 case WM8903_CLOCK_RATES_1: 173 case WM8903_CLOCK_RATES_2: 174 case WM8903_AUDIO_INTERFACE_0: 175 case WM8903_AUDIO_INTERFACE_1: 176 case WM8903_AUDIO_INTERFACE_2: 177 case WM8903_AUDIO_INTERFACE_3: 178 case WM8903_DAC_DIGITAL_VOLUME_LEFT: 179 case WM8903_DAC_DIGITAL_VOLUME_RIGHT: 180 case WM8903_DAC_DIGITAL_0: 181 case WM8903_DAC_DIGITAL_1: 182 case WM8903_ADC_DIGITAL_VOLUME_LEFT: 183 case WM8903_ADC_DIGITAL_VOLUME_RIGHT: 184 case WM8903_ADC_DIGITAL_0: 185 case WM8903_DIGITAL_MICROPHONE_0: 186 case WM8903_DRC_0: 187 case WM8903_DRC_1: 188 case WM8903_DRC_2: 189 case WM8903_DRC_3: 190 case WM8903_ANALOGUE_LEFT_INPUT_0: 191 case WM8903_ANALOGUE_RIGHT_INPUT_0: 192 case WM8903_ANALOGUE_LEFT_INPUT_1: 193 case WM8903_ANALOGUE_RIGHT_INPUT_1: 194 case WM8903_ANALOGUE_LEFT_MIX_0: 195 case WM8903_ANALOGUE_RIGHT_MIX_0: 196 case WM8903_ANALOGUE_SPK_MIX_LEFT_0: 197 case WM8903_ANALOGUE_SPK_MIX_LEFT_1: 198 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0: 199 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1: 200 case WM8903_ANALOGUE_OUT1_LEFT: 201 case WM8903_ANALOGUE_OUT1_RIGHT: 202 case WM8903_ANALOGUE_OUT2_LEFT: 203 case WM8903_ANALOGUE_OUT2_RIGHT: 204 case WM8903_ANALOGUE_OUT3_LEFT: 205 case WM8903_ANALOGUE_OUT3_RIGHT: 206 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0: 207 case WM8903_DC_SERVO_0: 208 case WM8903_DC_SERVO_2: 209 case WM8903_DC_SERVO_READBACK_1: 210 case WM8903_DC_SERVO_READBACK_2: 211 case WM8903_DC_SERVO_READBACK_3: 212 case WM8903_DC_SERVO_READBACK_4: 213 case WM8903_ANALOGUE_HP_0: 214 case WM8903_ANALOGUE_LINEOUT_0: 215 case WM8903_CHARGE_PUMP_0: 216 case WM8903_CLASS_W_0: 217 case WM8903_WRITE_SEQUENCER_0: 218 case WM8903_WRITE_SEQUENCER_1: 219 case WM8903_WRITE_SEQUENCER_2: 220 case WM8903_WRITE_SEQUENCER_3: 221 case WM8903_WRITE_SEQUENCER_4: 222 case WM8903_CONTROL_INTERFACE: 223 case WM8903_GPIO_CONTROL_1: 224 case WM8903_GPIO_CONTROL_2: 225 case WM8903_GPIO_CONTROL_3: 226 case WM8903_GPIO_CONTROL_4: 227 case WM8903_GPIO_CONTROL_5: 228 case WM8903_INTERRUPT_STATUS_1: 229 case WM8903_INTERRUPT_STATUS_1_MASK: 230 case WM8903_INTERRUPT_POLARITY_1: 231 case WM8903_INTERRUPT_CONTROL: 232 case WM8903_CLOCK_RATE_TEST_4: 233 case WM8903_ANALOGUE_OUTPUT_BIAS_0: 234 return true; 235 default: 236 return false; 237 } 238} 239 240static bool wm8903_volatile_register(struct device *dev, unsigned int reg) 241{ 242 switch (reg) { 243 case WM8903_SW_RESET_AND_ID: 244 case WM8903_REVISION_NUMBER: 245 case WM8903_INTERRUPT_STATUS_1: 246 case WM8903_WRITE_SEQUENCER_4: 247 case WM8903_DC_SERVO_READBACK_1: 248 case WM8903_DC_SERVO_READBACK_2: 249 case WM8903_DC_SERVO_READBACK_3: 250 case WM8903_DC_SERVO_READBACK_4: 251 return true; 252 253 default: 254 return false; 255 } 256} 257 258static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 259 struct snd_kcontrol *kcontrol, int event) 260{ 261 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 262 mdelay(4); 263 264 return 0; 265} 266 267static int wm8903_dcs_event(struct snd_soc_dapm_widget *w, 268 struct snd_kcontrol *kcontrol, int event) 269{ 270 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 271 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 272 273 switch (event) { 274 case SND_SOC_DAPM_POST_PMU: 275 wm8903->dcs_pending |= 1 << w->shift; 276 break; 277 case SND_SOC_DAPM_PRE_PMD: 278 snd_soc_component_update_bits(component, WM8903_DC_SERVO_0, 279 1 << w->shift, 0); 280 break; 281 } 282 283 return 0; 284} 285 286#define WM8903_DCS_MODE_WRITE_STOP 0 287#define WM8903_DCS_MODE_START_STOP 2 288 289static void wm8903_seq_notifier(struct snd_soc_component *component, 290 enum snd_soc_dapm_type event, int subseq) 291{ 292 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 293 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP; 294 int i, val; 295 296 /* Complete any pending DC servo starts */ 297 if (wm8903->dcs_pending) { 298 dev_dbg(component->dev, "Starting DC servo for %x\n", 299 wm8903->dcs_pending); 300 301 /* If we've no cached values then we need to do startup */ 302 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 303 if (!(wm8903->dcs_pending & (1 << i))) 304 continue; 305 306 if (wm8903->dcs_cache[i]) { 307 dev_dbg(component->dev, 308 "Restore DC servo %d value %x\n", 309 3 - i, wm8903->dcs_cache[i]); 310 311 snd_soc_component_write(component, WM8903_DC_SERVO_4 + i, 312 wm8903->dcs_cache[i] & 0xff); 313 } else { 314 dev_dbg(component->dev, 315 "Calibrate DC servo %d\n", 3 - i); 316 dcs_mode = WM8903_DCS_MODE_START_STOP; 317 } 318 } 319 320 /* Don't trust the cache for analogue */ 321 if (wm8903->class_w_users) 322 dcs_mode = WM8903_DCS_MODE_START_STOP; 323 324 snd_soc_component_update_bits(component, WM8903_DC_SERVO_2, 325 WM8903_DCS_MODE_MASK, dcs_mode); 326 327 snd_soc_component_update_bits(component, WM8903_DC_SERVO_0, 328 WM8903_DCS_ENA_MASK, wm8903->dcs_pending); 329 330 switch (dcs_mode) { 331 case WM8903_DCS_MODE_WRITE_STOP: 332 break; 333 334 case WM8903_DCS_MODE_START_STOP: 335 msleep(270); 336 337 /* Cache the measured offsets for digital */ 338 if (wm8903->class_w_users) 339 break; 340 341 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 342 if (!(wm8903->dcs_pending & (1 << i))) 343 continue; 344 345 val = snd_soc_component_read(component, 346 WM8903_DC_SERVO_READBACK_1 + i); 347 dev_dbg(component->dev, "DC servo %d: %x\n", 348 3 - i, val); 349 wm8903->dcs_cache[i] = val; 350 } 351 break; 352 353 default: 354 pr_warn("DCS mode %d delay not set\n", dcs_mode); 355 break; 356 } 357 358 wm8903->dcs_pending = 0; 359 } 360} 361 362/* 363 * When used with DAC outputs only the WM8903 charge pump supports 364 * operation in class W mode, providing very low power consumption 365 * when used with digital sources. Enable and disable this mode 366 * automatically depending on the mixer configuration. 367 * 368 * All the relevant controls are simple switches. 369 */ 370static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 371 struct snd_ctl_elem_value *ucontrol) 372{ 373 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 374 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 375 u16 reg; 376 int ret; 377 378 reg = snd_soc_component_read(component, WM8903_CLASS_W_0); 379 380 /* Turn it off if we're about to enable bypass */ 381 if (ucontrol->value.integer.value[0]) { 382 if (wm8903->class_w_users == 0) { 383 dev_dbg(component->dev, "Disabling Class W\n"); 384 snd_soc_component_write(component, WM8903_CLASS_W_0, reg & 385 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 386 } 387 wm8903->class_w_users++; 388 } 389 390 /* Implement the change */ 391 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 392 393 /* If we've just disabled the last bypass path turn Class W on */ 394 if (!ucontrol->value.integer.value[0]) { 395 if (wm8903->class_w_users == 1) { 396 dev_dbg(component->dev, "Enabling Class W\n"); 397 snd_soc_component_write(component, WM8903_CLASS_W_0, reg | 398 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 399 } 400 wm8903->class_w_users--; 401 } 402 403 dev_dbg(component->dev, "Bypass use count now %d\n", 404 wm8903->class_w_users); 405 406 return ret; 407} 408 409#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 410 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 411 snd_soc_dapm_get_volsw, wm8903_class_w_put) 412 413 414static int wm8903_deemph[] = { 0, 32000, 44100, 48000 }; 415 416static int wm8903_set_deemph(struct snd_soc_component *component) 417{ 418 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 419 int val, i, best; 420 421 /* If we're using deemphasis select the nearest available sample 422 * rate. 423 */ 424 if (wm8903->deemph) { 425 best = 1; 426 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) { 427 if (abs(wm8903_deemph[i] - wm8903->fs) < 428 abs(wm8903_deemph[best] - wm8903->fs)) 429 best = i; 430 } 431 432 val = best << WM8903_DEEMPH_SHIFT; 433 } else { 434 best = 0; 435 val = 0; 436 } 437 438 dev_dbg(component->dev, "Set deemphasis %d (%dHz)\n", 439 best, wm8903_deemph[best]); 440 441 return snd_soc_component_update_bits(component, WM8903_DAC_DIGITAL_1, 442 WM8903_DEEMPH_MASK, val); 443} 444 445static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, 446 struct snd_ctl_elem_value *ucontrol) 447{ 448 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 449 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 450 451 ucontrol->value.integer.value[0] = wm8903->deemph; 452 453 return 0; 454} 455 456static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, 457 struct snd_ctl_elem_value *ucontrol) 458{ 459 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 460 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 461 unsigned int deemph = ucontrol->value.integer.value[0]; 462 int ret = 0; 463 464 if (deemph > 1) 465 return -EINVAL; 466 467 mutex_lock(&wm8903->lock); 468 if (wm8903->deemph != deemph) { 469 wm8903->deemph = deemph; 470 471 wm8903_set_deemph(component); 472 473 ret = 1; 474 } 475 mutex_unlock(&wm8903->lock); 476 477 return ret; 478} 479 480/* ALSA can only do steps of .01dB */ 481static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 482 483static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 484 485static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 486static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 487 488static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 489static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 490static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 491static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 492static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 493 494static const char *hpf_mode_text[] = { 495 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 496}; 497 498static SOC_ENUM_SINGLE_DECL(hpf_mode, 499 WM8903_ADC_DIGITAL_0, 5, hpf_mode_text); 500 501static const char *osr_text[] = { 502 "Low power", "High performance" 503}; 504 505static SOC_ENUM_SINGLE_DECL(adc_osr, 506 WM8903_ANALOGUE_ADC_0, 0, osr_text); 507 508static SOC_ENUM_SINGLE_DECL(dac_osr, 509 WM8903_DAC_DIGITAL_1, 0, osr_text); 510 511static const char *drc_slope_text[] = { 512 "1", "1/2", "1/4", "1/8", "1/16", "0" 513}; 514 515static SOC_ENUM_SINGLE_DECL(drc_slope_r0, 516 WM8903_DRC_2, 3, drc_slope_text); 517 518static SOC_ENUM_SINGLE_DECL(drc_slope_r1, 519 WM8903_DRC_2, 0, drc_slope_text); 520 521static const char *drc_attack_text[] = { 522 "instantaneous", 523 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 524 "46.4ms", "92.8ms", "185.6ms" 525}; 526 527static SOC_ENUM_SINGLE_DECL(drc_attack, 528 WM8903_DRC_1, 12, drc_attack_text); 529 530static const char *drc_decay_text[] = { 531 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 532 "23.87s", "47.56s" 533}; 534 535static SOC_ENUM_SINGLE_DECL(drc_decay, 536 WM8903_DRC_1, 8, drc_decay_text); 537 538static const char *drc_ff_delay_text[] = { 539 "5 samples", "9 samples" 540}; 541 542static SOC_ENUM_SINGLE_DECL(drc_ff_delay, 543 WM8903_DRC_0, 5, drc_ff_delay_text); 544 545static const char *drc_qr_decay_text[] = { 546 "0.725ms", "1.45ms", "5.8ms" 547}; 548 549static SOC_ENUM_SINGLE_DECL(drc_qr_decay, 550 WM8903_DRC_1, 4, drc_qr_decay_text); 551 552static const char *drc_smoothing_text[] = { 553 "Low", "Medium", "High" 554}; 555 556static SOC_ENUM_SINGLE_DECL(drc_smoothing, 557 WM8903_DRC_0, 11, drc_smoothing_text); 558 559static const char *soft_mute_text[] = { 560 "Fast (fs/2)", "Slow (fs/32)" 561}; 562 563static SOC_ENUM_SINGLE_DECL(soft_mute, 564 WM8903_DAC_DIGITAL_1, 10, soft_mute_text); 565 566static const char *mute_mode_text[] = { 567 "Hard", "Soft" 568}; 569 570static SOC_ENUM_SINGLE_DECL(mute_mode, 571 WM8903_DAC_DIGITAL_1, 9, mute_mode_text); 572 573static const char *companding_text[] = { 574 "ulaw", "alaw" 575}; 576 577static SOC_ENUM_SINGLE_DECL(dac_companding, 578 WM8903_AUDIO_INTERFACE_0, 0, companding_text); 579 580static SOC_ENUM_SINGLE_DECL(adc_companding, 581 WM8903_AUDIO_INTERFACE_0, 2, companding_text); 582 583static const char *input_mode_text[] = { 584 "Single-Ended", "Differential Line", "Differential Mic" 585}; 586 587static SOC_ENUM_SINGLE_DECL(linput_mode_enum, 588 WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text); 589 590static SOC_ENUM_SINGLE_DECL(rinput_mode_enum, 591 WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text); 592 593static const char *linput_mux_text[] = { 594 "IN1L", "IN2L", "IN3L" 595}; 596 597static SOC_ENUM_SINGLE_DECL(linput_enum, 598 WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text); 599 600static SOC_ENUM_SINGLE_DECL(linput_inv_enum, 601 WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text); 602 603static const char *rinput_mux_text[] = { 604 "IN1R", "IN2R", "IN3R" 605}; 606 607static SOC_ENUM_SINGLE_DECL(rinput_enum, 608 WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text); 609 610static SOC_ENUM_SINGLE_DECL(rinput_inv_enum, 611 WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text); 612 613 614static const char *sidetone_text[] = { 615 "None", "Left", "Right" 616}; 617 618static SOC_ENUM_SINGLE_DECL(lsidetone_enum, 619 WM8903_DAC_DIGITAL_0, 2, sidetone_text); 620 621static SOC_ENUM_SINGLE_DECL(rsidetone_enum, 622 WM8903_DAC_DIGITAL_0, 0, sidetone_text); 623 624static const char *adcinput_text[] = { 625 "ADC", "DMIC" 626}; 627 628static SOC_ENUM_SINGLE_DECL(adcinput_enum, 629 WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text); 630 631static const char *aif_text[] = { 632 "Left", "Right" 633}; 634 635static SOC_ENUM_SINGLE_DECL(lcapture_enum, 636 WM8903_AUDIO_INTERFACE_0, 7, aif_text); 637 638static SOC_ENUM_SINGLE_DECL(rcapture_enum, 639 WM8903_AUDIO_INTERFACE_0, 6, aif_text); 640 641static SOC_ENUM_SINGLE_DECL(lplay_enum, 642 WM8903_AUDIO_INTERFACE_0, 5, aif_text); 643 644static SOC_ENUM_SINGLE_DECL(rplay_enum, 645 WM8903_AUDIO_INTERFACE_0, 4, aif_text); 646 647static const struct snd_kcontrol_new wm8903_snd_controls[] = { 648 649/* Input PGAs - No TLV since the scale depends on PGA mode */ 650SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 651 7, 1, 1), 652SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 653 0, 31, 0), 654SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 655 6, 1, 0), 656 657SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 658 7, 1, 1), 659SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 660 0, 31, 0), 661SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 662 6, 1, 0), 663 664/* ADCs */ 665SOC_ENUM("ADC OSR", adc_osr), 666SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), 667SOC_ENUM("HPF Mode", hpf_mode), 668SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 669SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 670SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 671SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 672 drc_tlv_thresh), 673SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 674SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 675SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 676SOC_ENUM("DRC Attack Rate", drc_attack), 677SOC_ENUM("DRC Decay Rate", drc_decay), 678SOC_ENUM("DRC FF Delay", drc_ff_delay), 679SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 680SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 681SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 682SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 683SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 684SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 685SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 686SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 687 688SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 689 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 690SOC_ENUM("ADC Companding Mode", adc_companding), 691SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 692 693SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 694 12, 0, digital_sidetone_tlv), 695 696/* DAC */ 697SOC_ENUM("DAC OSR", dac_osr), 698SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 699 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 700SOC_ENUM("DAC Soft Mute Rate", soft_mute), 701SOC_ENUM("DAC Mute Mode", mute_mode), 702SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 703SOC_ENUM("DAC Companding Mode", dac_companding), 704SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 705SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0, 706 dac_boost_tlv), 707SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, 708 wm8903_get_deemph, wm8903_put_deemph), 709 710/* Headphones */ 711SOC_DOUBLE_R("Headphone Switch", 712 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 713 8, 1, 1), 714SOC_DOUBLE_R("Headphone ZC Switch", 715 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 716 6, 1, 0), 717SOC_DOUBLE_R_TLV("Headphone Volume", 718 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 719 0, 63, 0, out_tlv), 720 721/* Line out */ 722SOC_DOUBLE_R("Line Out Switch", 723 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 724 8, 1, 1), 725SOC_DOUBLE_R("Line Out ZC Switch", 726 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 727 6, 1, 0), 728SOC_DOUBLE_R_TLV("Line Out Volume", 729 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 730 0, 63, 0, out_tlv), 731 732/* Speaker */ 733SOC_DOUBLE_R("Speaker Switch", 734 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 735SOC_DOUBLE_R("Speaker ZC Switch", 736 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 737SOC_DOUBLE_R_TLV("Speaker Volume", 738 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 739 0, 63, 0, out_tlv), 740}; 741 742static const struct snd_kcontrol_new linput_mode_mux = 743 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 744 745static const struct snd_kcontrol_new rinput_mode_mux = 746 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 747 748static const struct snd_kcontrol_new linput_mux = 749 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 750 751static const struct snd_kcontrol_new linput_inv_mux = 752 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 753 754static const struct snd_kcontrol_new rinput_mux = 755 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 756 757static const struct snd_kcontrol_new rinput_inv_mux = 758 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 759 760static const struct snd_kcontrol_new lsidetone_mux = 761 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 762 763static const struct snd_kcontrol_new rsidetone_mux = 764 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 765 766static const struct snd_kcontrol_new adcinput_mux = 767 SOC_DAPM_ENUM("ADC Input", adcinput_enum); 768 769static const struct snd_kcontrol_new lcapture_mux = 770 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum); 771 772static const struct snd_kcontrol_new rcapture_mux = 773 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum); 774 775static const struct snd_kcontrol_new lplay_mux = 776 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum); 777 778static const struct snd_kcontrol_new rplay_mux = 779 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum); 780 781static const struct snd_kcontrol_new left_output_mixer[] = { 782SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 783SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 784SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 785SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 786}; 787 788static const struct snd_kcontrol_new right_output_mixer[] = { 789SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 790SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 791SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 792SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 793}; 794 795static const struct snd_kcontrol_new left_speaker_mixer[] = { 796SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 797SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 798SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 799SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 800 0, 1, 0), 801}; 802 803static const struct snd_kcontrol_new right_speaker_mixer[] = { 804SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 805SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 806SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 807 1, 1, 0), 808SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 809 0, 1, 0), 810}; 811 812static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 813SND_SOC_DAPM_INPUT("IN1L"), 814SND_SOC_DAPM_INPUT("IN1R"), 815SND_SOC_DAPM_INPUT("IN2L"), 816SND_SOC_DAPM_INPUT("IN2R"), 817SND_SOC_DAPM_INPUT("IN3L"), 818SND_SOC_DAPM_INPUT("IN3R"), 819SND_SOC_DAPM_INPUT("DMICDAT"), 820 821SND_SOC_DAPM_OUTPUT("HPOUTL"), 822SND_SOC_DAPM_OUTPUT("HPOUTR"), 823SND_SOC_DAPM_OUTPUT("LINEOUTL"), 824SND_SOC_DAPM_OUTPUT("LINEOUTR"), 825SND_SOC_DAPM_OUTPUT("LOP"), 826SND_SOC_DAPM_OUTPUT("LON"), 827SND_SOC_DAPM_OUTPUT("ROP"), 828SND_SOC_DAPM_OUTPUT("RON"), 829 830SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 831 832SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 833SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 834 &linput_inv_mux), 835SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 836 837SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 838SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 839 &rinput_inv_mux), 840SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 841 842SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 843SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 844 845SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 846SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 847 848SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0), 849SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0), 850 851SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux), 852SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux), 853 854SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 855SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 856 857SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 858SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 859 860SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0), 861SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0), 862 863SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux), 864SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux), 865 866SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0), 867SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0), 868 869SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 870 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 871SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 872 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 873 874SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 875 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 876SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 877 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 878 879SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 880 1, 0, NULL, 0), 881SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 882 0, 0, NULL, 0), 883 884SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0, 885 NULL, 0), 886SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0, 887 NULL, 0), 888 889SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0), 890SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0), 891SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0), 892SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0), 893SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0), 894SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0), 895SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0), 896SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0), 897 898SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0, 899 NULL, 0), 900SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0, 901 NULL, 0), 902SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0, 903 NULL, 0), 904SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0, 905 NULL, 0), 906SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0, 907 NULL, 0), 908SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0, 909 NULL, 0), 910SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0, 911 NULL, 0), 912SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0, 913 NULL, 0), 914 915SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0), 916SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event, 917 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 918SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event, 919 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 920SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event, 921 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 922SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event, 923 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 924 925SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 926 NULL, 0), 927SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 928 NULL, 0), 929 930SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 931 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 932SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 933SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0), 934}; 935 936static const struct snd_soc_dapm_route wm8903_intercon[] = { 937 938 { "CLK_DSP", NULL, "CLK_SYS" }, 939 { "MICBIAS", NULL, "CLK_SYS" }, 940 { "HPL_DCS", NULL, "CLK_SYS" }, 941 { "HPR_DCS", NULL, "CLK_SYS" }, 942 { "LINEOUTL_DCS", NULL, "CLK_SYS" }, 943 { "LINEOUTR_DCS", NULL, "CLK_SYS" }, 944 945 { "Left Input Mux", "IN1L", "IN1L" }, 946 { "Left Input Mux", "IN2L", "IN2L" }, 947 { "Left Input Mux", "IN3L", "IN3L" }, 948 949 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 950 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 951 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 952 953 { "Right Input Mux", "IN1R", "IN1R" }, 954 { "Right Input Mux", "IN2R", "IN2R" }, 955 { "Right Input Mux", "IN3R", "IN3R" }, 956 957 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 958 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 959 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 960 961 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 962 { "Left Input Mode Mux", "Differential Line", 963 "Left Input Mux" }, 964 { "Left Input Mode Mux", "Differential Line", 965 "Left Input Inverting Mux" }, 966 { "Left Input Mode Mux", "Differential Mic", 967 "Left Input Mux" }, 968 { "Left Input Mode Mux", "Differential Mic", 969 "Left Input Inverting Mux" }, 970 971 { "Right Input Mode Mux", "Single-Ended", 972 "Right Input Inverting Mux" }, 973 { "Right Input Mode Mux", "Differential Line", 974 "Right Input Mux" }, 975 { "Right Input Mode Mux", "Differential Line", 976 "Right Input Inverting Mux" }, 977 { "Right Input Mode Mux", "Differential Mic", 978 "Right Input Mux" }, 979 { "Right Input Mode Mux", "Differential Mic", 980 "Right Input Inverting Mux" }, 981 982 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 983 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 984 985 { "Left ADC Input", "ADC", "Left Input PGA" }, 986 { "Left ADC Input", "DMIC", "DMICDAT" }, 987 { "Right ADC Input", "ADC", "Right Input PGA" }, 988 { "Right ADC Input", "DMIC", "DMICDAT" }, 989 990 { "Left Capture Mux", "Left", "ADCL" }, 991 { "Left Capture Mux", "Right", "ADCR" }, 992 993 { "Right Capture Mux", "Left", "ADCL" }, 994 { "Right Capture Mux", "Right", "ADCR" }, 995 996 { "AIFTXL", NULL, "Left Capture Mux" }, 997 { "AIFTXR", NULL, "Right Capture Mux" }, 998 999 { "ADCL", NULL, "Left ADC Input" }, 1000 { "ADCL", NULL, "CLK_DSP" }, 1001 { "ADCR", NULL, "Right ADC Input" }, 1002 { "ADCR", NULL, "CLK_DSP" }, 1003 1004 { "Left Playback Mux", "Left", "AIFRXL" }, 1005 { "Left Playback Mux", "Right", "AIFRXR" }, 1006 1007 { "Right Playback Mux", "Left", "AIFRXL" }, 1008 { "Right Playback Mux", "Right", "AIFRXR" }, 1009 1010 { "DACL Sidetone", "Left", "ADCL" }, 1011 { "DACL Sidetone", "Right", "ADCR" }, 1012 { "DACR Sidetone", "Left", "ADCL" }, 1013 { "DACR Sidetone", "Right", "ADCR" }, 1014 1015 { "DACL", NULL, "Left Playback Mux" }, 1016 { "DACL", NULL, "DACL Sidetone" }, 1017 { "DACL", NULL, "CLK_DSP" }, 1018 1019 { "DACR", NULL, "Right Playback Mux" }, 1020 { "DACR", NULL, "DACR Sidetone" }, 1021 { "DACR", NULL, "CLK_DSP" }, 1022 1023 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1024 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1025 { "Left Output Mixer", "DACL Switch", "DACL" }, 1026 { "Left Output Mixer", "DACR Switch", "DACR" }, 1027 1028 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1029 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1030 { "Right Output Mixer", "DACL Switch", "DACL" }, 1031 { "Right Output Mixer", "DACR Switch", "DACR" }, 1032 1033 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1034 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1035 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 1036 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 1037 1038 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1039 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1040 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 1041 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 1042 1043 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 1044 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 1045 1046 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 1047 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 1048 1049 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 1050 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 1051 1052 { "HPL_ENA", NULL, "Left Headphone Output PGA" }, 1053 { "HPR_ENA", NULL, "Right Headphone Output PGA" }, 1054 { "HPL_ENA_DLY", NULL, "HPL_ENA" }, 1055 { "HPR_ENA_DLY", NULL, "HPR_ENA" }, 1056 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" }, 1057 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" }, 1058 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" }, 1059 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" }, 1060 1061 { "HPL_DCS", NULL, "DCS Master" }, 1062 { "HPR_DCS", NULL, "DCS Master" }, 1063 { "LINEOUTL_DCS", NULL, "DCS Master" }, 1064 { "LINEOUTR_DCS", NULL, "DCS Master" }, 1065 1066 { "HPL_DCS", NULL, "HPL_ENA_DLY" }, 1067 { "HPR_DCS", NULL, "HPR_ENA_DLY" }, 1068 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" }, 1069 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" }, 1070 1071 { "HPL_ENA_OUTP", NULL, "HPL_DCS" }, 1072 { "HPR_ENA_OUTP", NULL, "HPR_DCS" }, 1073 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" }, 1074 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" }, 1075 1076 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" }, 1077 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" }, 1078 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" }, 1079 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" }, 1080 1081 { "HPOUTL", NULL, "HPL_RMV_SHORT" }, 1082 { "HPOUTR", NULL, "HPR_RMV_SHORT" }, 1083 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" }, 1084 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" }, 1085 1086 { "LOP", NULL, "Left Speaker PGA" }, 1087 { "LON", NULL, "Left Speaker PGA" }, 1088 1089 { "ROP", NULL, "Right Speaker PGA" }, 1090 { "RON", NULL, "Right Speaker PGA" }, 1091 1092 { "Charge Pump", NULL, "CLK_DSP" }, 1093 1094 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 1095 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 1096 { "Left Line Output PGA", NULL, "Charge Pump" }, 1097 { "Right Line Output PGA", NULL, "Charge Pump" }, 1098}; 1099 1100static int wm8903_set_bias_level(struct snd_soc_component *component, 1101 enum snd_soc_bias_level level) 1102{ 1103 switch (level) { 1104 case SND_SOC_BIAS_ON: 1105 break; 1106 1107 case SND_SOC_BIAS_PREPARE: 1108 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1109 WM8903_VMID_RES_MASK, 1110 WM8903_VMID_RES_50K); 1111 break; 1112 1113 case SND_SOC_BIAS_STANDBY: 1114 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1115 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0, 1116 WM8903_POBCTRL | WM8903_ISEL_MASK | 1117 WM8903_STARTUP_BIAS_ENA | 1118 WM8903_BIAS_ENA, 1119 WM8903_POBCTRL | 1120 (2 << WM8903_ISEL_SHIFT) | 1121 WM8903_STARTUP_BIAS_ENA); 1122 1123 snd_soc_component_update_bits(component, 1124 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1125 WM8903_SPK_DISCHARGE, 1126 WM8903_SPK_DISCHARGE); 1127 1128 msleep(33); 1129 1130 snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5, 1131 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1132 WM8903_SPKL_ENA | WM8903_SPKR_ENA); 1133 1134 snd_soc_component_update_bits(component, 1135 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1136 WM8903_SPK_DISCHARGE, 0); 1137 1138 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1139 WM8903_VMID_TIE_ENA | 1140 WM8903_BUFIO_ENA | 1141 WM8903_VMID_IO_ENA | 1142 WM8903_VMID_SOFT_MASK | 1143 WM8903_VMID_RES_MASK | 1144 WM8903_VMID_BUF_ENA, 1145 WM8903_VMID_TIE_ENA | 1146 WM8903_BUFIO_ENA | 1147 WM8903_VMID_IO_ENA | 1148 (2 << WM8903_VMID_SOFT_SHIFT) | 1149 WM8903_VMID_RES_250K | 1150 WM8903_VMID_BUF_ENA); 1151 1152 msleep(129); 1153 1154 snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5, 1155 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1156 0); 1157 1158 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1159 WM8903_VMID_SOFT_MASK, 0); 1160 1161 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1162 WM8903_VMID_RES_MASK, 1163 WM8903_VMID_RES_50K); 1164 1165 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0, 1166 WM8903_BIAS_ENA | WM8903_POBCTRL, 1167 WM8903_BIAS_ENA); 1168 1169 /* By default no bypass paths are enabled so 1170 * enable Class W support. 1171 */ 1172 dev_dbg(component->dev, "Enabling Class W\n"); 1173 snd_soc_component_update_bits(component, WM8903_CLASS_W_0, 1174 WM8903_CP_DYN_FREQ | 1175 WM8903_CP_DYN_V, 1176 WM8903_CP_DYN_FREQ | 1177 WM8903_CP_DYN_V); 1178 } 1179 1180 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1181 WM8903_VMID_RES_MASK, 1182 WM8903_VMID_RES_250K); 1183 break; 1184 1185 case SND_SOC_BIAS_OFF: 1186 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0, 1187 WM8903_BIAS_ENA, 0); 1188 1189 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1190 WM8903_VMID_SOFT_MASK, 1191 2 << WM8903_VMID_SOFT_SHIFT); 1192 1193 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1194 WM8903_VMID_BUF_ENA, 0); 1195 1196 msleep(290); 1197 1198 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1199 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA | 1200 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK | 1201 WM8903_VMID_SOFT_MASK | 1202 WM8903_VMID_BUF_ENA, 0); 1203 1204 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0, 1205 WM8903_STARTUP_BIAS_ENA, 0); 1206 break; 1207 } 1208 1209 return 0; 1210} 1211 1212static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1213 int clk_id, unsigned int freq, int dir) 1214{ 1215 struct snd_soc_component *component = codec_dai->component; 1216 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 1217 1218 wm8903->sysclk = freq; 1219 1220 return 0; 1221} 1222 1223static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1224 unsigned int fmt) 1225{ 1226 struct snd_soc_component *component = codec_dai->component; 1227 u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1); 1228 1229 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1230 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1231 1232 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1233 case SND_SOC_DAIFMT_CBS_CFS: 1234 break; 1235 case SND_SOC_DAIFMT_CBS_CFM: 1236 aif1 |= WM8903_LRCLK_DIR; 1237 break; 1238 case SND_SOC_DAIFMT_CBM_CFM: 1239 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1240 break; 1241 case SND_SOC_DAIFMT_CBM_CFS: 1242 aif1 |= WM8903_BCLK_DIR; 1243 break; 1244 default: 1245 return -EINVAL; 1246 } 1247 1248 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1249 case SND_SOC_DAIFMT_DSP_A: 1250 aif1 |= 0x3; 1251 break; 1252 case SND_SOC_DAIFMT_DSP_B: 1253 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1254 break; 1255 case SND_SOC_DAIFMT_I2S: 1256 aif1 |= 0x2; 1257 break; 1258 case SND_SOC_DAIFMT_RIGHT_J: 1259 aif1 |= 0x1; 1260 break; 1261 case SND_SOC_DAIFMT_LEFT_J: 1262 break; 1263 default: 1264 return -EINVAL; 1265 } 1266 1267 /* Clock inversion */ 1268 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1269 case SND_SOC_DAIFMT_DSP_A: 1270 case SND_SOC_DAIFMT_DSP_B: 1271 /* frame inversion not valid for DSP modes */ 1272 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1273 case SND_SOC_DAIFMT_NB_NF: 1274 break; 1275 case SND_SOC_DAIFMT_IB_NF: 1276 aif1 |= WM8903_AIF_BCLK_INV; 1277 break; 1278 default: 1279 return -EINVAL; 1280 } 1281 break; 1282 case SND_SOC_DAIFMT_I2S: 1283 case SND_SOC_DAIFMT_RIGHT_J: 1284 case SND_SOC_DAIFMT_LEFT_J: 1285 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1286 case SND_SOC_DAIFMT_NB_NF: 1287 break; 1288 case SND_SOC_DAIFMT_IB_IF: 1289 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1290 break; 1291 case SND_SOC_DAIFMT_IB_NF: 1292 aif1 |= WM8903_AIF_BCLK_INV; 1293 break; 1294 case SND_SOC_DAIFMT_NB_IF: 1295 aif1 |= WM8903_AIF_LRCLK_INV; 1296 break; 1297 default: 1298 return -EINVAL; 1299 } 1300 break; 1301 default: 1302 return -EINVAL; 1303 } 1304 1305 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1); 1306 1307 return 0; 1308} 1309 1310static int wm8903_mute(struct snd_soc_dai *codec_dai, int mute, int direction) 1311{ 1312 struct snd_soc_component *component = codec_dai->component; 1313 u16 reg; 1314 1315 reg = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1); 1316 1317 if (mute) 1318 reg |= WM8903_DAC_MUTE; 1319 else 1320 reg &= ~WM8903_DAC_MUTE; 1321 1322 snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, reg); 1323 1324 return 0; 1325} 1326 1327/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1328 * for optimal performance so we list the lower rates first and match 1329 * on the last match we find. */ 1330static struct { 1331 int div; 1332 int rate; 1333 int mode; 1334 int mclk_div; 1335} clk_sys_ratios[] = { 1336 { 64, 0x0, 0x0, 1 }, 1337 { 68, 0x0, 0x1, 1 }, 1338 { 125, 0x0, 0x2, 1 }, 1339 { 128, 0x1, 0x0, 1 }, 1340 { 136, 0x1, 0x1, 1 }, 1341 { 192, 0x2, 0x0, 1 }, 1342 { 204, 0x2, 0x1, 1 }, 1343 1344 { 64, 0x0, 0x0, 2 }, 1345 { 68, 0x0, 0x1, 2 }, 1346 { 125, 0x0, 0x2, 2 }, 1347 { 128, 0x1, 0x0, 2 }, 1348 { 136, 0x1, 0x1, 2 }, 1349 { 192, 0x2, 0x0, 2 }, 1350 { 204, 0x2, 0x1, 2 }, 1351 1352 { 250, 0x2, 0x2, 1 }, 1353 { 256, 0x3, 0x0, 1 }, 1354 { 272, 0x3, 0x1, 1 }, 1355 { 384, 0x4, 0x0, 1 }, 1356 { 408, 0x4, 0x1, 1 }, 1357 { 375, 0x4, 0x2, 1 }, 1358 { 512, 0x5, 0x0, 1 }, 1359 { 544, 0x5, 0x1, 1 }, 1360 { 500, 0x5, 0x2, 1 }, 1361 { 768, 0x6, 0x0, 1 }, 1362 { 816, 0x6, 0x1, 1 }, 1363 { 750, 0x6, 0x2, 1 }, 1364 { 1024, 0x7, 0x0, 1 }, 1365 { 1088, 0x7, 0x1, 1 }, 1366 { 1000, 0x7, 0x2, 1 }, 1367 { 1408, 0x8, 0x0, 1 }, 1368 { 1496, 0x8, 0x1, 1 }, 1369 { 1536, 0x9, 0x0, 1 }, 1370 { 1632, 0x9, 0x1, 1 }, 1371 { 1500, 0x9, 0x2, 1 }, 1372 1373 { 250, 0x2, 0x2, 2 }, 1374 { 256, 0x3, 0x0, 2 }, 1375 { 272, 0x3, 0x1, 2 }, 1376 { 384, 0x4, 0x0, 2 }, 1377 { 408, 0x4, 0x1, 2 }, 1378 { 375, 0x4, 0x2, 2 }, 1379 { 512, 0x5, 0x0, 2 }, 1380 { 544, 0x5, 0x1, 2 }, 1381 { 500, 0x5, 0x2, 2 }, 1382 { 768, 0x6, 0x0, 2 }, 1383 { 816, 0x6, 0x1, 2 }, 1384 { 750, 0x6, 0x2, 2 }, 1385 { 1024, 0x7, 0x0, 2 }, 1386 { 1088, 0x7, 0x1, 2 }, 1387 { 1000, 0x7, 0x2, 2 }, 1388 { 1408, 0x8, 0x0, 2 }, 1389 { 1496, 0x8, 0x1, 2 }, 1390 { 1536, 0x9, 0x0, 2 }, 1391 { 1632, 0x9, 0x1, 2 }, 1392 { 1500, 0x9, 0x2, 2 }, 1393}; 1394 1395/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1396static struct { 1397 int ratio; 1398 int div; 1399} bclk_divs[] = { 1400 { 10, 0 }, 1401 { 20, 2 }, 1402 { 30, 3 }, 1403 { 40, 4 }, 1404 { 50, 5 }, 1405 { 60, 7 }, 1406 { 80, 8 }, 1407 { 100, 9 }, 1408 { 120, 11 }, 1409 { 160, 12 }, 1410 { 200, 13 }, 1411 { 220, 14 }, 1412 { 240, 15 }, 1413 { 300, 17 }, 1414 { 320, 18 }, 1415 { 440, 19 }, 1416 { 480, 20 }, 1417}; 1418 1419/* Sample rates for DSP */ 1420static struct { 1421 int rate; 1422 int value; 1423} sample_rates[] = { 1424 { 8000, 0 }, 1425 { 11025, 1 }, 1426 { 12000, 2 }, 1427 { 16000, 3 }, 1428 { 22050, 4 }, 1429 { 24000, 5 }, 1430 { 32000, 6 }, 1431 { 44100, 7 }, 1432 { 48000, 8 }, 1433 { 88200, 9 }, 1434 { 96000, 10 }, 1435 { 0, 0 }, 1436}; 1437 1438static int wm8903_hw_params(struct snd_pcm_substream *substream, 1439 struct snd_pcm_hw_params *params, 1440 struct snd_soc_dai *dai) 1441{ 1442 struct snd_soc_component *component = dai->component; 1443 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 1444 int fs = params_rate(params); 1445 int bclk; 1446 int bclk_div; 1447 int i; 1448 int dsp_config; 1449 int clk_config; 1450 int best_val; 1451 int cur_val; 1452 int clk_sys; 1453 1454 u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1); 1455 u16 aif2 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_2); 1456 u16 aif3 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_3); 1457 u16 clock0 = snd_soc_component_read(component, WM8903_CLOCK_RATES_0); 1458 u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1); 1459 u16 dac_digital1 = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1); 1460 1461 /* Enable sloping stopband filter for low sample rates */ 1462 if (fs <= 24000) 1463 dac_digital1 |= WM8903_DAC_SB_FILT; 1464 else 1465 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1466 1467 /* Configure sample rate logic for DSP - choose nearest rate */ 1468 dsp_config = 0; 1469 best_val = abs(sample_rates[dsp_config].rate - fs); 1470 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1471 cur_val = abs(sample_rates[i].rate - fs); 1472 if (cur_val <= best_val) { 1473 dsp_config = i; 1474 best_val = cur_val; 1475 } 1476 } 1477 1478 dev_dbg(component->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1479 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1480 clock1 |= sample_rates[dsp_config].value; 1481 1482 aif1 &= ~WM8903_AIF_WL_MASK; 1483 bclk = 2 * fs; 1484 switch (params_width(params)) { 1485 case 16: 1486 bclk *= 16; 1487 break; 1488 case 20: 1489 bclk *= 20; 1490 aif1 |= 0x4; 1491 break; 1492 case 24: 1493 bclk *= 24; 1494 aif1 |= 0x8; 1495 break; 1496 case 32: 1497 bclk *= 32; 1498 aif1 |= 0xc; 1499 break; 1500 default: 1501 return -EINVAL; 1502 } 1503 1504 dev_dbg(component->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1505 wm8903->sysclk, fs); 1506 1507 /* We may not have an MCLK which allows us to generate exactly 1508 * the clock we want, particularly with USB derived inputs, so 1509 * approximate. 1510 */ 1511 clk_config = 0; 1512 best_val = abs((wm8903->sysclk / 1513 (clk_sys_ratios[0].mclk_div * 1514 clk_sys_ratios[0].div)) - fs); 1515 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1516 cur_val = abs((wm8903->sysclk / 1517 (clk_sys_ratios[i].mclk_div * 1518 clk_sys_ratios[i].div)) - fs); 1519 1520 if (cur_val <= best_val) { 1521 clk_config = i; 1522 best_val = cur_val; 1523 } 1524 } 1525 1526 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1527 clock0 |= WM8903_MCLKDIV2; 1528 clk_sys = wm8903->sysclk / 2; 1529 } else { 1530 clock0 &= ~WM8903_MCLKDIV2; 1531 clk_sys = wm8903->sysclk; 1532 } 1533 1534 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1535 WM8903_CLK_SYS_MODE_MASK); 1536 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1537 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1538 1539 dev_dbg(component->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1540 clk_sys_ratios[clk_config].rate, 1541 clk_sys_ratios[clk_config].mode, 1542 clk_sys_ratios[clk_config].div); 1543 1544 dev_dbg(component->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1545 1546 /* We may not get quite the right frequency if using 1547 * approximate clocks so look for the closest match that is 1548 * higher than the target (we need to ensure that there enough 1549 * BCLKs to clock out the samples). 1550 */ 1551 bclk_div = 0; 1552 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1553 i = 1; 1554 while (i < ARRAY_SIZE(bclk_divs)) { 1555 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1556 if (cur_val < 0) /* BCLK table is sorted */ 1557 break; 1558 bclk_div = i; 1559 best_val = cur_val; 1560 i++; 1561 } 1562 1563 aif2 &= ~WM8903_BCLK_DIV_MASK; 1564 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1565 1566 dev_dbg(component->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1567 bclk_divs[bclk_div].ratio / 10, bclk, 1568 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1569 1570 aif2 |= bclk_divs[bclk_div].div; 1571 aif3 |= bclk / fs; 1572 1573 wm8903->fs = params_rate(params); 1574 wm8903_set_deemph(component); 1575 1576 snd_soc_component_write(component, WM8903_CLOCK_RATES_0, clock0); 1577 snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1); 1578 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1); 1579 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_2, aif2); 1580 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_3, aif3); 1581 snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, dac_digital1); 1582 1583 return 0; 1584} 1585 1586/** 1587 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ 1588 * 1589 * @component: WM8903 component 1590 * @jack: jack to report detection events on 1591 * @det: value to report for presence detection 1592 * @shrt: value to report for short detection 1593 * 1594 * Enable microphone detection via IRQ on the WM8903. If GPIOs are 1595 * being used to bring out signals to the processor then only platform 1596 * data configuration is needed for WM8903 and processor GPIOs should 1597 * be configured using snd_soc_jack_add_gpios() instead. 1598 * 1599 * The current threasholds for detection should be configured using 1600 * micdet_cfg in the platform data. Using this function will force on 1601 * the microphone bias for the device. 1602 */ 1603int wm8903_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 1604 int det, int shrt) 1605{ 1606 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 1607 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; 1608 1609 dev_dbg(component->dev, "Enabling microphone detection: %x %x\n", 1610 det, shrt); 1611 1612 /* Store the configuration */ 1613 wm8903->mic_jack = jack; 1614 wm8903->mic_det = det; 1615 wm8903->mic_short = shrt; 1616 1617 /* Enable interrupts we've got a report configured for */ 1618 if (det) 1619 irq_mask &= ~WM8903_MICDET_EINT; 1620 if (shrt) 1621 irq_mask &= ~WM8903_MICSHRT_EINT; 1622 1623 snd_soc_component_update_bits(component, WM8903_INTERRUPT_STATUS_1_MASK, 1624 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, 1625 irq_mask); 1626 1627 if (det || shrt) { 1628 /* Enable mic detection, this may not have been set through 1629 * platform data (eg, if the defaults are OK). */ 1630 snd_soc_component_update_bits(component, WM8903_WRITE_SEQUENCER_0, 1631 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1632 snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0, 1633 WM8903_MICDET_ENA, WM8903_MICDET_ENA); 1634 } else { 1635 snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0, 1636 WM8903_MICDET_ENA, 0); 1637 } 1638 1639 return 0; 1640} 1641EXPORT_SYMBOL_GPL(wm8903_mic_detect); 1642 1643static irqreturn_t wm8903_irq(int irq, void *data) 1644{ 1645 struct wm8903_priv *wm8903 = data; 1646 int mic_report, ret; 1647 unsigned int int_val, mask, int_pol; 1648 1649 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK, 1650 &mask); 1651 if (ret != 0) { 1652 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret); 1653 return IRQ_NONE; 1654 } 1655 1656 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val); 1657 if (ret != 0) { 1658 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret); 1659 return IRQ_NONE; 1660 } 1661 1662 int_val &= ~mask; 1663 1664 if (int_val & WM8903_WSEQ_BUSY_EINT) { 1665 dev_warn(wm8903->dev, "Write sequencer done\n"); 1666 } 1667 1668 /* 1669 * The rest is microphone jack detection. We need to manually 1670 * invert the polarity of the interrupt after each event - to 1671 * simplify the code keep track of the last state we reported 1672 * and just invert the relevant bits in both the report and 1673 * the polarity register. 1674 */ 1675 mic_report = wm8903->mic_last_report; 1676 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1, 1677 &int_pol); 1678 if (ret != 0) { 1679 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n", 1680 ret); 1681 return IRQ_HANDLED; 1682 } 1683 1684#ifndef CONFIG_SND_SOC_WM8903_MODULE 1685 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) 1686 trace_snd_soc_jack_irq(dev_name(wm8903->dev)); 1687#endif 1688 1689 if (int_val & WM8903_MICSHRT_EINT) { 1690 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol); 1691 1692 mic_report ^= wm8903->mic_short; 1693 int_pol ^= WM8903_MICSHRT_INV; 1694 } 1695 1696 if (int_val & WM8903_MICDET_EINT) { 1697 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol); 1698 1699 mic_report ^= wm8903->mic_det; 1700 int_pol ^= WM8903_MICDET_INV; 1701 1702 msleep(wm8903->mic_delay); 1703 } 1704 1705 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1, 1706 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); 1707 1708 snd_soc_jack_report(wm8903->mic_jack, mic_report, 1709 wm8903->mic_short | wm8903->mic_det); 1710 1711 wm8903->mic_last_report = mic_report; 1712 1713 return IRQ_HANDLED; 1714} 1715 1716#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1717 SNDRV_PCM_RATE_11025 | \ 1718 SNDRV_PCM_RATE_16000 | \ 1719 SNDRV_PCM_RATE_22050 | \ 1720 SNDRV_PCM_RATE_32000 | \ 1721 SNDRV_PCM_RATE_44100 | \ 1722 SNDRV_PCM_RATE_48000 | \ 1723 SNDRV_PCM_RATE_88200 | \ 1724 SNDRV_PCM_RATE_96000) 1725 1726#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1727 SNDRV_PCM_RATE_11025 | \ 1728 SNDRV_PCM_RATE_16000 | \ 1729 SNDRV_PCM_RATE_22050 | \ 1730 SNDRV_PCM_RATE_32000 | \ 1731 SNDRV_PCM_RATE_44100 | \ 1732 SNDRV_PCM_RATE_48000) 1733 1734#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1735 SNDRV_PCM_FMTBIT_S20_3LE |\ 1736 SNDRV_PCM_FMTBIT_S24_LE) 1737 1738static const struct snd_soc_dai_ops wm8903_dai_ops = { 1739 .hw_params = wm8903_hw_params, 1740 .mute_stream = wm8903_mute, 1741 .set_fmt = wm8903_set_dai_fmt, 1742 .set_sysclk = wm8903_set_dai_sysclk, 1743 .no_capture_mute = 1, 1744}; 1745 1746static struct snd_soc_dai_driver wm8903_dai = { 1747 .name = "wm8903-hifi", 1748 .playback = { 1749 .stream_name = "Playback", 1750 .channels_min = 2, 1751 .channels_max = 2, 1752 .rates = WM8903_PLAYBACK_RATES, 1753 .formats = WM8903_FORMATS, 1754 }, 1755 .capture = { 1756 .stream_name = "Capture", 1757 .channels_min = 2, 1758 .channels_max = 2, 1759 .rates = WM8903_CAPTURE_RATES, 1760 .formats = WM8903_FORMATS, 1761 }, 1762 .ops = &wm8903_dai_ops, 1763 .symmetric_rates = 1, 1764}; 1765 1766static int wm8903_resume(struct snd_soc_component *component) 1767{ 1768 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 1769 1770 regcache_sync(wm8903->regmap); 1771 1772 return 0; 1773} 1774 1775#ifdef CONFIG_GPIOLIB 1776static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset) 1777{ 1778 if (offset >= WM8903_NUM_GPIO) 1779 return -EINVAL; 1780 1781 return 0; 1782} 1783 1784static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 1785{ 1786 struct wm8903_priv *wm8903 = gpiochip_get_data(chip); 1787 unsigned int mask, val; 1788 int ret; 1789 1790 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK; 1791 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) | 1792 WM8903_GP1_DIR; 1793 1794 ret = regmap_update_bits(wm8903->regmap, 1795 WM8903_GPIO_CONTROL_1 + offset, mask, val); 1796 if (ret < 0) 1797 return ret; 1798 1799 return 0; 1800} 1801 1802static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset) 1803{ 1804 struct wm8903_priv *wm8903 = gpiochip_get_data(chip); 1805 unsigned int reg; 1806 1807 regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, ®); 1808 1809 return !!((reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT); 1810} 1811 1812static int wm8903_gpio_direction_out(struct gpio_chip *chip, 1813 unsigned offset, int value) 1814{ 1815 struct wm8903_priv *wm8903 = gpiochip_get_data(chip); 1816 unsigned int mask, val; 1817 int ret; 1818 1819 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK; 1820 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) | 1821 (value << WM8903_GP2_LVL_SHIFT); 1822 1823 ret = regmap_update_bits(wm8903->regmap, 1824 WM8903_GPIO_CONTROL_1 + offset, mask, val); 1825 if (ret < 0) 1826 return ret; 1827 1828 return 0; 1829} 1830 1831static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1832{ 1833 struct wm8903_priv *wm8903 = gpiochip_get_data(chip); 1834 1835 regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, 1836 WM8903_GP1_LVL_MASK, 1837 !!value << WM8903_GP1_LVL_SHIFT); 1838} 1839 1840static const struct gpio_chip wm8903_template_chip = { 1841 .label = "wm8903", 1842 .owner = THIS_MODULE, 1843 .request = wm8903_gpio_request, 1844 .direction_input = wm8903_gpio_direction_in, 1845 .get = wm8903_gpio_get, 1846 .direction_output = wm8903_gpio_direction_out, 1847 .set = wm8903_gpio_set, 1848 .can_sleep = 1, 1849}; 1850 1851static void wm8903_init_gpio(struct wm8903_priv *wm8903) 1852{ 1853 struct wm8903_platform_data *pdata = wm8903->pdata; 1854 int ret; 1855 1856 wm8903->gpio_chip = wm8903_template_chip; 1857 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO; 1858 wm8903->gpio_chip.parent = wm8903->dev; 1859 1860 if (pdata->gpio_base) 1861 wm8903->gpio_chip.base = pdata->gpio_base; 1862 else 1863 wm8903->gpio_chip.base = -1; 1864 1865 ret = gpiochip_add_data(&wm8903->gpio_chip, wm8903); 1866 if (ret != 0) 1867 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret); 1868} 1869 1870static void wm8903_free_gpio(struct wm8903_priv *wm8903) 1871{ 1872 gpiochip_remove(&wm8903->gpio_chip); 1873} 1874#else 1875static void wm8903_init_gpio(struct wm8903_priv *wm8903) 1876{ 1877} 1878 1879static void wm8903_free_gpio(struct wm8903_priv *wm8903) 1880{ 1881} 1882#endif 1883 1884static const struct snd_soc_component_driver soc_component_dev_wm8903 = { 1885 .resume = wm8903_resume, 1886 .set_bias_level = wm8903_set_bias_level, 1887 .seq_notifier = wm8903_seq_notifier, 1888 .controls = wm8903_snd_controls, 1889 .num_controls = ARRAY_SIZE(wm8903_snd_controls), 1890 .dapm_widgets = wm8903_dapm_widgets, 1891 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets), 1892 .dapm_routes = wm8903_intercon, 1893 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon), 1894 .suspend_bias_off = 1, 1895 .idle_bias_on = 1, 1896 .use_pmdown_time = 1, 1897 .endianness = 1, 1898 .non_legacy_dai_naming = 1, 1899}; 1900 1901static const struct regmap_config wm8903_regmap = { 1902 .reg_bits = 8, 1903 .val_bits = 16, 1904 1905 .max_register = WM8903_MAX_REGISTER, 1906 .volatile_reg = wm8903_volatile_register, 1907 .readable_reg = wm8903_readable_register, 1908 1909 .cache_type = REGCACHE_RBTREE, 1910 .reg_defaults = wm8903_reg_defaults, 1911 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults), 1912}; 1913 1914static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c, 1915 struct wm8903_platform_data *pdata) 1916{ 1917 struct irq_data *irq_data = irq_get_irq_data(i2c->irq); 1918 if (!irq_data) { 1919 dev_err(&i2c->dev, "Invalid IRQ: %d\n", 1920 i2c->irq); 1921 return -EINVAL; 1922 } 1923 1924 switch (irqd_get_trigger_type(irq_data)) { 1925 case IRQ_TYPE_NONE: 1926 default: 1927 /* 1928 * We assume the controller imposes no restrictions, 1929 * so we are able to select active-high 1930 */ 1931 fallthrough; 1932 case IRQ_TYPE_LEVEL_HIGH: 1933 pdata->irq_active_low = false; 1934 break; 1935 case IRQ_TYPE_LEVEL_LOW: 1936 pdata->irq_active_low = true; 1937 break; 1938 } 1939 1940 return 0; 1941} 1942 1943static int wm8903_set_pdata_from_of(struct i2c_client *i2c, 1944 struct wm8903_platform_data *pdata) 1945{ 1946 const struct device_node *np = i2c->dev.of_node; 1947 u32 val32; 1948 int i; 1949 1950 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0) 1951 pdata->micdet_cfg = val32; 1952 1953 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0) 1954 pdata->micdet_delay = val32; 1955 1956 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg, 1957 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) { 1958 /* 1959 * In device tree: 0 means "write 0", 1960 * 0xffffffff means "don't touch". 1961 * 1962 * In platform data: 0 means "don't touch", 1963 * 0x8000 means "write 0". 1964 * 1965 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000. 1966 * 1967 * Convert from DT to pdata representation here, 1968 * so no other code needs to change. 1969 */ 1970 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 1971 if (pdata->gpio_cfg[i] == 0) { 1972 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO; 1973 } else if (pdata->gpio_cfg[i] == 0xffffffff) { 1974 pdata->gpio_cfg[i] = 0; 1975 } else if (pdata->gpio_cfg[i] > 0x7fff) { 1976 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n", 1977 i, pdata->gpio_cfg[i]); 1978 return -EINVAL; 1979 } 1980 } 1981 } 1982 1983 return 0; 1984} 1985 1986static int wm8903_i2c_probe(struct i2c_client *i2c, 1987 const struct i2c_device_id *id) 1988{ 1989 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev); 1990 struct wm8903_priv *wm8903; 1991 int trigger; 1992 bool mic_gpio = false; 1993 unsigned int val, irq_pol; 1994 int ret, i; 1995 1996 wm8903 = devm_kzalloc(&i2c->dev, sizeof(*wm8903), GFP_KERNEL); 1997 if (wm8903 == NULL) 1998 return -ENOMEM; 1999 2000 mutex_init(&wm8903->lock); 2001 wm8903->dev = &i2c->dev; 2002 2003 wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap); 2004 if (IS_ERR(wm8903->regmap)) { 2005 ret = PTR_ERR(wm8903->regmap); 2006 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2007 ret); 2008 return ret; 2009 } 2010 2011 i2c_set_clientdata(i2c, wm8903); 2012 2013 /* If no platform data was supplied, create storage for defaults */ 2014 if (pdata) { 2015 wm8903->pdata = pdata; 2016 } else { 2017 wm8903->pdata = devm_kzalloc(&i2c->dev, sizeof(*wm8903->pdata), 2018 GFP_KERNEL); 2019 if (!wm8903->pdata) 2020 return -ENOMEM; 2021 2022 if (i2c->irq) { 2023 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata); 2024 if (ret != 0) 2025 return ret; 2026 } 2027 2028 if (i2c->dev.of_node) { 2029 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata); 2030 if (ret != 0) 2031 return ret; 2032 } 2033 } 2034 2035 pdata = wm8903->pdata; 2036 2037 for (i = 0; i < ARRAY_SIZE(wm8903->supplies); i++) 2038 wm8903->supplies[i].supply = wm8903_supply_names[i]; 2039 2040 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8903->supplies), 2041 wm8903->supplies); 2042 if (ret != 0) { 2043 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2044 return ret; 2045 } 2046 2047 ret = regulator_bulk_enable(ARRAY_SIZE(wm8903->supplies), 2048 wm8903->supplies); 2049 if (ret != 0) { 2050 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2051 return ret; 2052 } 2053 2054 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val); 2055 if (ret != 0) { 2056 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); 2057 goto err; 2058 } 2059 if (val != 0x8903) { 2060 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val); 2061 ret = -ENODEV; 2062 goto err; 2063 } 2064 2065 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val); 2066 if (ret != 0) { 2067 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret); 2068 goto err; 2069 } 2070 dev_info(&i2c->dev, "WM8903 revision %c\n", 2071 (val & WM8903_CHIP_REV_MASK) + 'A'); 2072 2073 /* Reset the device */ 2074 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903); 2075 2076 wm8903_init_gpio(wm8903); 2077 2078 /* Set up GPIO pin state, detect if any are MIC detect outputs */ 2079 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 2080 if ((!pdata->gpio_cfg[i]) || 2081 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO)) 2082 continue; 2083 2084 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i, 2085 pdata->gpio_cfg[i] & 0x7fff); 2086 2087 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK) 2088 >> WM8903_GP1_FN_SHIFT; 2089 2090 switch (val) { 2091 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT: 2092 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT: 2093 mic_gpio = true; 2094 break; 2095 default: 2096 break; 2097 } 2098 } 2099 2100 /* Set up microphone detection */ 2101 regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0, 2102 pdata->micdet_cfg); 2103 2104 /* Microphone detection needs the WSEQ clock */ 2105 if (pdata->micdet_cfg) 2106 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0, 2107 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 2108 2109 /* If microphone detection is enabled by pdata but 2110 * detected via IRQ then interrupts can be lost before 2111 * the machine driver has set up microphone detection 2112 * IRQs as the IRQs are clear on read. The detection 2113 * will be enabled when the machine driver configures. 2114 */ 2115 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA)); 2116 2117 wm8903->mic_delay = pdata->micdet_delay; 2118 2119 if (i2c->irq) { 2120 if (pdata->irq_active_low) { 2121 trigger = IRQF_TRIGGER_LOW; 2122 irq_pol = WM8903_IRQ_POL; 2123 } else { 2124 trigger = IRQF_TRIGGER_HIGH; 2125 irq_pol = 0; 2126 } 2127 2128 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL, 2129 WM8903_IRQ_POL, irq_pol); 2130 2131 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq, 2132 trigger | IRQF_ONESHOT, 2133 "wm8903", wm8903); 2134 if (ret != 0) { 2135 dev_err(wm8903->dev, "Failed to request IRQ: %d\n", 2136 ret); 2137 return ret; 2138 } 2139 2140 /* Enable write sequencer interrupts */ 2141 regmap_update_bits(wm8903->regmap, 2142 WM8903_INTERRUPT_STATUS_1_MASK, 2143 WM8903_IM_WSEQ_BUSY_EINT, 0); 2144 } 2145 2146 /* Latch volume update bits */ 2147 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT, 2148 WM8903_ADCVU, WM8903_ADCVU); 2149 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT, 2150 WM8903_ADCVU, WM8903_ADCVU); 2151 2152 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT, 2153 WM8903_DACVU, WM8903_DACVU); 2154 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT, 2155 WM8903_DACVU, WM8903_DACVU); 2156 2157 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT, 2158 WM8903_HPOUTVU, WM8903_HPOUTVU); 2159 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT, 2160 WM8903_HPOUTVU, WM8903_HPOUTVU); 2161 2162 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT, 2163 WM8903_LINEOUTVU, WM8903_LINEOUTVU); 2164 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT, 2165 WM8903_LINEOUTVU, WM8903_LINEOUTVU); 2166 2167 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT, 2168 WM8903_SPKVU, WM8903_SPKVU); 2169 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT, 2170 WM8903_SPKVU, WM8903_SPKVU); 2171 2172 /* Enable DAC soft mute by default */ 2173 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1, 2174 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE, 2175 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE); 2176 2177 ret = devm_snd_soc_register_component(&i2c->dev, 2178 &soc_component_dev_wm8903, &wm8903_dai, 1); 2179 if (ret != 0) 2180 goto err; 2181 2182 return 0; 2183err: 2184 regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies), 2185 wm8903->supplies); 2186 return ret; 2187} 2188 2189static int wm8903_i2c_remove(struct i2c_client *client) 2190{ 2191 struct wm8903_priv *wm8903 = i2c_get_clientdata(client); 2192 2193 regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies), 2194 wm8903->supplies); 2195 if (client->irq) 2196 free_irq(client->irq, wm8903); 2197 wm8903_free_gpio(wm8903); 2198 2199 return 0; 2200} 2201 2202static const struct of_device_id wm8903_of_match[] = { 2203 { .compatible = "wlf,wm8903", }, 2204 {}, 2205}; 2206MODULE_DEVICE_TABLE(of, wm8903_of_match); 2207 2208static const struct i2c_device_id wm8903_i2c_id[] = { 2209 { "wm8903", 0 }, 2210 { } 2211}; 2212MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 2213 2214static struct i2c_driver wm8903_i2c_driver = { 2215 .driver = { 2216 .name = "wm8903", 2217 .of_match_table = wm8903_of_match, 2218 }, 2219 .probe = wm8903_i2c_probe, 2220 .remove = wm8903_i2c_remove, 2221 .id_table = wm8903_i2c_id, 2222}; 2223 2224module_i2c_driver(wm8903_i2c_driver); 2225 2226MODULE_DESCRIPTION("ASoC WM8903 driver"); 2227MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 2228MODULE_LICENSE("GPL"); 2229