1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * wm0010.c -- WM0010 DSP Driver 4 * 5 * Copyright 2012 Wolfson Microelectronics PLC. 6 * 7 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 9 * Scott Ling <sl@opensource.wolfsonmicro.com> 10 */ 11 12#include <linux/module.h> 13#include <linux/moduleparam.h> 14#include <linux/interrupt.h> 15#include <linux/irqreturn.h> 16#include <linux/init.h> 17#include <linux/spi/spi.h> 18#include <linux/firmware.h> 19#include <linux/delay.h> 20#include <linux/fs.h> 21#include <linux/gpio.h> 22#include <linux/regulator/consumer.h> 23#include <linux/mutex.h> 24#include <linux/workqueue.h> 25 26#include <sound/soc.h> 27#include <sound/wm0010.h> 28 29#define DEVICE_ID_WM0010 10 30 31/* We only support v1 of the .dfw INFO record */ 32#define INFO_VERSION 1 33 34enum dfw_cmd { 35 DFW_CMD_FUSE = 0x01, 36 DFW_CMD_CODE_HDR, 37 DFW_CMD_CODE_DATA, 38 DFW_CMD_PLL, 39 DFW_CMD_INFO = 0xff 40}; 41 42struct dfw_binrec { 43 u8 command; 44 u32 length:24; 45 u32 address; 46 uint8_t data[]; 47} __packed; 48 49struct dfw_inforec { 50 u8 info_version; 51 u8 tool_major_version; 52 u8 tool_minor_version; 53 u8 dsp_target; 54}; 55 56struct dfw_pllrec { 57 u8 command; 58 u32 length:24; 59 u32 address; 60 u32 clkctrl1; 61 u32 clkctrl2; 62 u32 clkctrl3; 63 u32 ldetctrl; 64 u32 uart_div; 65 u32 spi_div; 66} __packed; 67 68static struct pll_clock_map { 69 int max_sysclk; 70 int max_pll_spi_speed; 71 u32 pll_clkctrl1; 72} pll_clock_map[] = { /* Dividers */ 73 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ 74 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ 75 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ 76 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ 77 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ 78 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ 79}; 80 81enum wm0010_state { 82 WM0010_POWER_OFF, 83 WM0010_OUT_OF_RESET, 84 WM0010_BOOTROM, 85 WM0010_STAGE2, 86 WM0010_FIRMWARE, 87}; 88 89struct wm0010_priv { 90 struct snd_soc_component *component; 91 92 struct mutex lock; 93 struct device *dev; 94 95 struct wm0010_pdata pdata; 96 97 int gpio_reset; 98 int gpio_reset_value; 99 100 struct regulator_bulk_data core_supplies[2]; 101 struct regulator *dbvdd; 102 103 int sysclk; 104 105 enum wm0010_state state; 106 bool boot_failed; 107 bool ready; 108 bool pll_running; 109 int max_spi_freq; 110 int board_max_spi_speed; 111 u32 pll_clkctrl1; 112 113 spinlock_t irq_lock; 114 int irq; 115 116 struct completion boot_completion; 117}; 118 119struct wm0010_spi_msg { 120 struct spi_message m; 121 struct spi_transfer t; 122 u8 *tx_buf; 123 u8 *rx_buf; 124 size_t len; 125}; 126 127static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { 128SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), 129}; 130 131static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { 132 { "SDI2 Capture", NULL, "SDI1 Playback" }, 133 { "SDI1 Capture", NULL, "SDI2 Playback" }, 134 135 { "SDI1 Capture", NULL, "CLKIN" }, 136 { "SDI2 Capture", NULL, "CLKIN" }, 137 { "SDI1 Playback", NULL, "CLKIN" }, 138 { "SDI2 Playback", NULL, "CLKIN" }, 139}; 140 141static const char *wm0010_state_to_str(enum wm0010_state state) 142{ 143 static const char * const state_to_str[] = { 144 "Power off", 145 "Out of reset", 146 "Boot ROM", 147 "Stage2", 148 "Firmware" 149 }; 150 151 if (state < 0 || state >= ARRAY_SIZE(state_to_str)) 152 return "null"; 153 return state_to_str[state]; 154} 155 156/* Called with wm0010->lock held */ 157static void wm0010_halt(struct snd_soc_component *component) 158{ 159 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 160 unsigned long flags; 161 enum wm0010_state state; 162 163 /* Fetch the wm0010 state */ 164 spin_lock_irqsave(&wm0010->irq_lock, flags); 165 state = wm0010->state; 166 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 167 168 switch (state) { 169 case WM0010_POWER_OFF: 170 /* If there's nothing to do, bail out */ 171 return; 172 case WM0010_OUT_OF_RESET: 173 case WM0010_BOOTROM: 174 case WM0010_STAGE2: 175 case WM0010_FIRMWARE: 176 /* Remember to put chip back into reset */ 177 gpio_set_value_cansleep(wm0010->gpio_reset, 178 wm0010->gpio_reset_value); 179 /* Disable the regulators */ 180 regulator_disable(wm0010->dbvdd); 181 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 182 wm0010->core_supplies); 183 break; 184 } 185 186 spin_lock_irqsave(&wm0010->irq_lock, flags); 187 wm0010->state = WM0010_POWER_OFF; 188 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 189} 190 191struct wm0010_boot_xfer { 192 struct list_head list; 193 struct snd_soc_component *component; 194 struct completion *done; 195 struct spi_message m; 196 struct spi_transfer t; 197}; 198 199/* Called with wm0010->lock held */ 200static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) 201{ 202 enum wm0010_state state; 203 unsigned long flags; 204 205 spin_lock_irqsave(&wm0010->irq_lock, flags); 206 state = wm0010->state; 207 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 208 209 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", 210 wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); 211 212 wm0010->boot_failed = true; 213} 214 215static void wm0010_boot_xfer_complete(void *data) 216{ 217 struct wm0010_boot_xfer *xfer = data; 218 struct snd_soc_component *component = xfer->component; 219 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 220 u32 *out32 = xfer->t.rx_buf; 221 int i; 222 223 if (xfer->m.status != 0) { 224 dev_err(component->dev, "SPI transfer failed: %d\n", 225 xfer->m.status); 226 wm0010_mark_boot_failure(wm0010); 227 if (xfer->done) 228 complete(xfer->done); 229 return; 230 } 231 232 for (i = 0; i < xfer->t.len / 4; i++) { 233 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]); 234 235 switch (be32_to_cpu(out32[i])) { 236 case 0xe0e0e0e0: 237 dev_err(component->dev, 238 "%d: ROM error reported in stage 2\n", i); 239 wm0010_mark_boot_failure(wm0010); 240 break; 241 242 case 0x55555555: 243 if (wm0010->state < WM0010_STAGE2) 244 break; 245 dev_err(component->dev, 246 "%d: ROM bootloader running in stage 2\n", i); 247 wm0010_mark_boot_failure(wm0010); 248 break; 249 250 case 0x0fed0000: 251 dev_dbg(component->dev, "Stage2 loader running\n"); 252 break; 253 254 case 0x0fed0007: 255 dev_dbg(component->dev, "CODE_HDR packet received\n"); 256 break; 257 258 case 0x0fed0008: 259 dev_dbg(component->dev, "CODE_DATA packet received\n"); 260 break; 261 262 case 0x0fed0009: 263 dev_dbg(component->dev, "Download complete\n"); 264 break; 265 266 case 0x0fed000c: 267 dev_dbg(component->dev, "Application start\n"); 268 break; 269 270 case 0x0fed000e: 271 dev_dbg(component->dev, "PLL packet received\n"); 272 wm0010->pll_running = true; 273 break; 274 275 case 0x0fed0025: 276 dev_err(component->dev, "Device reports image too long\n"); 277 wm0010_mark_boot_failure(wm0010); 278 break; 279 280 case 0x0fed002c: 281 dev_err(component->dev, "Device reports bad SPI packet\n"); 282 wm0010_mark_boot_failure(wm0010); 283 break; 284 285 case 0x0fed0031: 286 dev_err(component->dev, "Device reports SPI read overflow\n"); 287 wm0010_mark_boot_failure(wm0010); 288 break; 289 290 case 0x0fed0032: 291 dev_err(component->dev, "Device reports SPI underclock\n"); 292 wm0010_mark_boot_failure(wm0010); 293 break; 294 295 case 0x0fed0033: 296 dev_err(component->dev, "Device reports bad header packet\n"); 297 wm0010_mark_boot_failure(wm0010); 298 break; 299 300 case 0x0fed0034: 301 dev_err(component->dev, "Device reports invalid packet type\n"); 302 wm0010_mark_boot_failure(wm0010); 303 break; 304 305 case 0x0fed0035: 306 dev_err(component->dev, "Device reports data before header error\n"); 307 wm0010_mark_boot_failure(wm0010); 308 break; 309 310 case 0x0fed0038: 311 dev_err(component->dev, "Device reports invalid PLL packet\n"); 312 break; 313 314 case 0x0fed003a: 315 dev_err(component->dev, "Device reports packet alignment error\n"); 316 wm0010_mark_boot_failure(wm0010); 317 break; 318 319 default: 320 dev_err(component->dev, "Unrecognised return 0x%x\n", 321 be32_to_cpu(out32[i])); 322 wm0010_mark_boot_failure(wm0010); 323 break; 324 } 325 326 if (wm0010->boot_failed) 327 break; 328 } 329 330 if (xfer->done) 331 complete(xfer->done); 332} 333 334static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) 335{ 336 int i; 337 338 for (i = 0; i < len / 8; i++) 339 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i])); 340} 341 342static int wm0010_firmware_load(const char *name, struct snd_soc_component *component) 343{ 344 struct spi_device *spi = to_spi_device(component->dev); 345 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 346 struct list_head xfer_list; 347 struct wm0010_boot_xfer *xfer; 348 int ret; 349 DECLARE_COMPLETION_ONSTACK(done); 350 const struct firmware *fw; 351 const struct dfw_binrec *rec; 352 const struct dfw_inforec *inforec; 353 u64 *img; 354 u8 *out, dsp; 355 u32 len, offset; 356 357 INIT_LIST_HEAD(&xfer_list); 358 359 ret = request_firmware(&fw, name, component->dev); 360 if (ret != 0) { 361 dev_err(component->dev, "Failed to request application(%s): %d\n", 362 name, ret); 363 return ret; 364 } 365 366 rec = (const struct dfw_binrec *)fw->data; 367 inforec = (const struct dfw_inforec *)rec->data; 368 offset = 0; 369 dsp = inforec->dsp_target; 370 wm0010->boot_failed = false; 371 if (WARN_ON(!list_empty(&xfer_list))) 372 return -EINVAL; 373 374 /* First record should be INFO */ 375 if (rec->command != DFW_CMD_INFO) { 376 dev_err(component->dev, "First record not INFO\r\n"); 377 ret = -EINVAL; 378 goto abort; 379 } 380 381 if (inforec->info_version != INFO_VERSION) { 382 dev_err(component->dev, 383 "Unsupported version (%02d) of INFO record\r\n", 384 inforec->info_version); 385 ret = -EINVAL; 386 goto abort; 387 } 388 389 dev_dbg(component->dev, "Version v%02d INFO record found\r\n", 390 inforec->info_version); 391 392 /* Check it's a DSP file */ 393 if (dsp != DEVICE_ID_WM0010) { 394 dev_err(component->dev, "Not a WM0010 firmware file.\r\n"); 395 ret = -EINVAL; 396 goto abort; 397 } 398 399 /* Skip the info record as we don't need to send it */ 400 offset += ((rec->length) + 8); 401 rec = (void *)&rec->data[rec->length]; 402 403 while (offset < fw->size) { 404 dev_dbg(component->dev, 405 "Packet: command %d, data length = 0x%x\r\n", 406 rec->command, rec->length); 407 len = rec->length + 8; 408 409 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL); 410 if (!xfer) { 411 ret = -ENOMEM; 412 goto abort; 413 } 414 415 xfer->component = component; 416 list_add_tail(&xfer->list, &xfer_list); 417 418 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 419 if (!out) { 420 ret = -ENOMEM; 421 goto abort1; 422 } 423 xfer->t.rx_buf = out; 424 425 img = kzalloc(len, GFP_KERNEL | GFP_DMA); 426 if (!img) { 427 ret = -ENOMEM; 428 goto abort1; 429 } 430 xfer->t.tx_buf = img; 431 432 byte_swap_64((u64 *)&rec->command, img, len); 433 434 spi_message_init(&xfer->m); 435 xfer->m.complete = wm0010_boot_xfer_complete; 436 xfer->m.context = xfer; 437 xfer->t.len = len; 438 xfer->t.bits_per_word = 8; 439 440 if (!wm0010->pll_running) { 441 xfer->t.speed_hz = wm0010->sysclk / 6; 442 } else { 443 xfer->t.speed_hz = wm0010->max_spi_freq; 444 445 if (wm0010->board_max_spi_speed && 446 (wm0010->board_max_spi_speed < wm0010->max_spi_freq)) 447 xfer->t.speed_hz = wm0010->board_max_spi_speed; 448 } 449 450 /* Store max usable spi frequency for later use */ 451 wm0010->max_spi_freq = xfer->t.speed_hz; 452 453 spi_message_add_tail(&xfer->t, &xfer->m); 454 455 offset += ((rec->length) + 8); 456 rec = (void *)&rec->data[rec->length]; 457 458 if (offset >= fw->size) { 459 dev_dbg(component->dev, "All transfers scheduled\n"); 460 xfer->done = &done; 461 } 462 463 ret = spi_async(spi, &xfer->m); 464 if (ret != 0) { 465 dev_err(component->dev, "Write failed: %d\n", ret); 466 goto abort1; 467 } 468 469 if (wm0010->boot_failed) { 470 dev_dbg(component->dev, "Boot fail!\n"); 471 ret = -EINVAL; 472 goto abort1; 473 } 474 } 475 476 wait_for_completion(&done); 477 478 ret = 0; 479 480abort1: 481 while (!list_empty(&xfer_list)) { 482 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, 483 list); 484 kfree(xfer->t.rx_buf); 485 kfree(xfer->t.tx_buf); 486 list_del(&xfer->list); 487 kfree(xfer); 488 } 489 490abort: 491 release_firmware(fw); 492 return ret; 493} 494 495static int wm0010_stage2_load(struct snd_soc_component *component) 496{ 497 struct spi_device *spi = to_spi_device(component->dev); 498 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 499 const struct firmware *fw; 500 struct spi_message m; 501 struct spi_transfer t; 502 u32 *img; 503 u8 *out; 504 int i; 505 int ret = 0; 506 507 ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev); 508 if (ret != 0) { 509 dev_err(component->dev, "Failed to request stage2 loader: %d\n", 510 ret); 511 return ret; 512 } 513 514 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size); 515 516 /* Copy to local buffer first as vmalloc causes problems for dma */ 517 img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA); 518 if (!img) { 519 ret = -ENOMEM; 520 goto abort2; 521 } 522 523 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA); 524 if (!out) { 525 ret = -ENOMEM; 526 goto abort1; 527 } 528 529 spi_message_init(&m); 530 memset(&t, 0, sizeof(t)); 531 t.rx_buf = out; 532 t.tx_buf = img; 533 t.len = fw->size; 534 t.bits_per_word = 8; 535 t.speed_hz = wm0010->sysclk / 10; 536 spi_message_add_tail(&t, &m); 537 538 dev_dbg(component->dev, "Starting initial download at %dHz\n", 539 t.speed_hz); 540 541 ret = spi_sync(spi, &m); 542 if (ret != 0) { 543 dev_err(component->dev, "Initial download failed: %d\n", ret); 544 goto abort; 545 } 546 547 /* Look for errors from the boot ROM */ 548 for (i = 0; i < fw->size; i++) { 549 if (out[i] != 0x55) { 550 dev_err(component->dev, "Boot ROM error: %x in %d\n", 551 out[i], i); 552 wm0010_mark_boot_failure(wm0010); 553 ret = -EBUSY; 554 goto abort; 555 } 556 } 557abort: 558 kfree(out); 559abort1: 560 kfree(img); 561abort2: 562 release_firmware(fw); 563 564 return ret; 565} 566 567static int wm0010_boot(struct snd_soc_component *component) 568{ 569 struct spi_device *spi = to_spi_device(component->dev); 570 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 571 unsigned long flags; 572 int ret; 573 struct spi_message m; 574 struct spi_transfer t; 575 struct dfw_pllrec pll_rec; 576 u32 *p, len; 577 u64 *img_swap; 578 u8 *out; 579 int i; 580 581 spin_lock_irqsave(&wm0010->irq_lock, flags); 582 if (wm0010->state != WM0010_POWER_OFF) 583 dev_warn(wm0010->dev, "DSP already powered up!\n"); 584 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 585 586 if (wm0010->sysclk > 26000000) { 587 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n"); 588 ret = -ECANCELED; 589 goto err; 590 } 591 592 mutex_lock(&wm0010->lock); 593 wm0010->pll_running = false; 594 595 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); 596 597 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), 598 wm0010->core_supplies); 599 if (ret != 0) { 600 dev_err(&spi->dev, "Failed to enable core supplies: %d\n", 601 ret); 602 mutex_unlock(&wm0010->lock); 603 goto err; 604 } 605 606 ret = regulator_enable(wm0010->dbvdd); 607 if (ret != 0) { 608 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); 609 goto err_core; 610 } 611 612 /* Release reset */ 613 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value); 614 spin_lock_irqsave(&wm0010->irq_lock, flags); 615 wm0010->state = WM0010_OUT_OF_RESET; 616 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 617 618 if (!wait_for_completion_timeout(&wm0010->boot_completion, 619 msecs_to_jiffies(20))) 620 dev_err(component->dev, "Failed to get interrupt from DSP\n"); 621 622 spin_lock_irqsave(&wm0010->irq_lock, flags); 623 wm0010->state = WM0010_BOOTROM; 624 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 625 626 ret = wm0010_stage2_load(component); 627 if (ret) 628 goto abort; 629 630 if (!wait_for_completion_timeout(&wm0010->boot_completion, 631 msecs_to_jiffies(20))) 632 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n"); 633 634 spin_lock_irqsave(&wm0010->irq_lock, flags); 635 wm0010->state = WM0010_STAGE2; 636 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 637 638 /* Only initialise PLL if max_spi_freq initialised */ 639 if (wm0010->max_spi_freq) { 640 641 /* Initialise a PLL record */ 642 memset(&pll_rec, 0, sizeof(pll_rec)); 643 pll_rec.command = DFW_CMD_PLL; 644 pll_rec.length = (sizeof(pll_rec) - 8); 645 646 /* On wm0010 only the CLKCTRL1 value is used */ 647 pll_rec.clkctrl1 = wm0010->pll_clkctrl1; 648 649 ret = -ENOMEM; 650 len = pll_rec.length + 8; 651 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 652 if (!out) 653 goto abort; 654 655 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA); 656 if (!img_swap) 657 goto abort_out; 658 659 /* We need to re-order for 0010 */ 660 byte_swap_64((u64 *)&pll_rec, img_swap, len); 661 662 spi_message_init(&m); 663 memset(&t, 0, sizeof(t)); 664 t.rx_buf = out; 665 t.tx_buf = img_swap; 666 t.len = len; 667 t.bits_per_word = 8; 668 t.speed_hz = wm0010->sysclk / 6; 669 spi_message_add_tail(&t, &m); 670 671 ret = spi_sync(spi, &m); 672 if (ret) { 673 dev_err(component->dev, "First PLL write failed: %d\n", ret); 674 goto abort_swap; 675 } 676 677 /* Use a second send of the message to get the return status */ 678 ret = spi_sync(spi, &m); 679 if (ret) { 680 dev_err(component->dev, "Second PLL write failed: %d\n", ret); 681 goto abort_swap; 682 } 683 684 p = (u32 *)out; 685 686 /* Look for PLL active code from the DSP */ 687 for (i = 0; i < len / 4; i++) { 688 if (*p == 0x0e00ed0f) { 689 dev_dbg(component->dev, "PLL packet received\n"); 690 wm0010->pll_running = true; 691 break; 692 } 693 p++; 694 } 695 696 kfree(img_swap); 697 kfree(out); 698 } else 699 dev_dbg(component->dev, "Not enabling DSP PLL."); 700 701 ret = wm0010_firmware_load("wm0010.dfw", component); 702 703 if (ret != 0) 704 goto abort; 705 706 spin_lock_irqsave(&wm0010->irq_lock, flags); 707 wm0010->state = WM0010_FIRMWARE; 708 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 709 710 mutex_unlock(&wm0010->lock); 711 712 return 0; 713 714abort_swap: 715 kfree(img_swap); 716abort_out: 717 kfree(out); 718abort: 719 /* Put the chip back into reset */ 720 wm0010_halt(component); 721 mutex_unlock(&wm0010->lock); 722 return ret; 723 724err_core: 725 mutex_unlock(&wm0010->lock); 726 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 727 wm0010->core_supplies); 728err: 729 return ret; 730} 731 732static int wm0010_set_bias_level(struct snd_soc_component *component, 733 enum snd_soc_bias_level level) 734{ 735 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 736 737 switch (level) { 738 case SND_SOC_BIAS_ON: 739 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) 740 wm0010_boot(component); 741 break; 742 case SND_SOC_BIAS_PREPARE: 743 break; 744 case SND_SOC_BIAS_STANDBY: 745 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) { 746 mutex_lock(&wm0010->lock); 747 wm0010_halt(component); 748 mutex_unlock(&wm0010->lock); 749 } 750 break; 751 case SND_SOC_BIAS_OFF: 752 break; 753 } 754 755 return 0; 756} 757 758static int wm0010_set_sysclk(struct snd_soc_component *component, int source, 759 int clk_id, unsigned int freq, int dir) 760{ 761 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 762 unsigned int i; 763 764 wm0010->sysclk = freq; 765 766 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { 767 wm0010->max_spi_freq = 0; 768 } else { 769 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) 770 if (freq >= pll_clock_map[i].max_sysclk) { 771 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; 772 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; 773 break; 774 } 775 } 776 777 return 0; 778} 779 780static int wm0010_probe(struct snd_soc_component *component); 781 782static const struct snd_soc_component_driver soc_component_dev_wm0010 = { 783 .probe = wm0010_probe, 784 .set_bias_level = wm0010_set_bias_level, 785 .set_sysclk = wm0010_set_sysclk, 786 .dapm_widgets = wm0010_dapm_widgets, 787 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), 788 .dapm_routes = wm0010_dapm_routes, 789 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), 790 .use_pmdown_time = 1, 791 .endianness = 1, 792 .non_legacy_dai_naming = 1, 793}; 794 795#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 796#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 797 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 798 SNDRV_PCM_FMTBIT_S32_LE) 799 800static struct snd_soc_dai_driver wm0010_dai[] = { 801 { 802 .name = "wm0010-sdi1", 803 .playback = { 804 .stream_name = "SDI1 Playback", 805 .channels_min = 1, 806 .channels_max = 2, 807 .rates = WM0010_RATES, 808 .formats = WM0010_FORMATS, 809 }, 810 .capture = { 811 .stream_name = "SDI1 Capture", 812 .channels_min = 1, 813 .channels_max = 2, 814 .rates = WM0010_RATES, 815 .formats = WM0010_FORMATS, 816 }, 817 }, 818 { 819 .name = "wm0010-sdi2", 820 .playback = { 821 .stream_name = "SDI2 Playback", 822 .channels_min = 1, 823 .channels_max = 2, 824 .rates = WM0010_RATES, 825 .formats = WM0010_FORMATS, 826 }, 827 .capture = { 828 .stream_name = "SDI2 Capture", 829 .channels_min = 1, 830 .channels_max = 2, 831 .rates = WM0010_RATES, 832 .formats = WM0010_FORMATS, 833 }, 834 }, 835}; 836 837static irqreturn_t wm0010_irq(int irq, void *data) 838{ 839 struct wm0010_priv *wm0010 = data; 840 841 switch (wm0010->state) { 842 case WM0010_OUT_OF_RESET: 843 case WM0010_BOOTROM: 844 case WM0010_STAGE2: 845 spin_lock(&wm0010->irq_lock); 846 complete(&wm0010->boot_completion); 847 spin_unlock(&wm0010->irq_lock); 848 return IRQ_HANDLED; 849 default: 850 return IRQ_NONE; 851 } 852 853 return IRQ_NONE; 854} 855 856static int wm0010_probe(struct snd_soc_component *component) 857{ 858 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 859 860 wm0010->component = component; 861 862 return 0; 863} 864 865static int wm0010_spi_probe(struct spi_device *spi) 866{ 867 unsigned long gpio_flags; 868 int ret; 869 int trigger; 870 int irq; 871 struct wm0010_priv *wm0010; 872 873 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), 874 GFP_KERNEL); 875 if (!wm0010) 876 return -ENOMEM; 877 878 mutex_init(&wm0010->lock); 879 spin_lock_init(&wm0010->irq_lock); 880 881 spi_set_drvdata(spi, wm0010); 882 wm0010->dev = &spi->dev; 883 884 if (dev_get_platdata(&spi->dev)) 885 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), 886 sizeof(wm0010->pdata)); 887 888 init_completion(&wm0010->boot_completion); 889 890 wm0010->core_supplies[0].supply = "AVDD"; 891 wm0010->core_supplies[1].supply = "DCVDD"; 892 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), 893 wm0010->core_supplies); 894 if (ret != 0) { 895 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", 896 ret); 897 return ret; 898 } 899 900 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); 901 if (IS_ERR(wm0010->dbvdd)) { 902 ret = PTR_ERR(wm0010->dbvdd); 903 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); 904 return ret; 905 } 906 907 if (wm0010->pdata.gpio_reset) { 908 wm0010->gpio_reset = wm0010->pdata.gpio_reset; 909 910 if (wm0010->pdata.reset_active_high) 911 wm0010->gpio_reset_value = 1; 912 else 913 wm0010->gpio_reset_value = 0; 914 915 if (wm0010->gpio_reset_value) 916 gpio_flags = GPIOF_OUT_INIT_HIGH; 917 else 918 gpio_flags = GPIOF_OUT_INIT_LOW; 919 920 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset, 921 gpio_flags, "wm0010 reset"); 922 if (ret < 0) { 923 dev_err(wm0010->dev, 924 "Failed to request GPIO for DSP reset: %d\n", 925 ret); 926 return ret; 927 } 928 } else { 929 dev_err(wm0010->dev, "No reset GPIO configured\n"); 930 return -EINVAL; 931 } 932 933 wm0010->state = WM0010_POWER_OFF; 934 935 irq = spi->irq; 936 if (wm0010->pdata.irq_flags) 937 trigger = wm0010->pdata.irq_flags; 938 else 939 trigger = IRQF_TRIGGER_FALLING; 940 trigger |= IRQF_ONESHOT; 941 942 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger, 943 "wm0010", wm0010); 944 if (ret) { 945 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", 946 irq, ret); 947 return ret; 948 } 949 wm0010->irq = irq; 950 951 ret = irq_set_irq_wake(irq, 1); 952 if (ret) { 953 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n", 954 irq, ret); 955 return ret; 956 } 957 958 if (spi->max_speed_hz) 959 wm0010->board_max_spi_speed = spi->max_speed_hz; 960 else 961 wm0010->board_max_spi_speed = 0; 962 963 ret = devm_snd_soc_register_component(&spi->dev, 964 &soc_component_dev_wm0010, wm0010_dai, 965 ARRAY_SIZE(wm0010_dai)); 966 if (ret < 0) 967 return ret; 968 969 return 0; 970} 971 972static int wm0010_spi_remove(struct spi_device *spi) 973{ 974 struct wm0010_priv *wm0010 = spi_get_drvdata(spi); 975 976 gpio_set_value_cansleep(wm0010->gpio_reset, 977 wm0010->gpio_reset_value); 978 979 irq_set_irq_wake(wm0010->irq, 0); 980 981 if (wm0010->irq) 982 free_irq(wm0010->irq, wm0010); 983 984 return 0; 985} 986 987static struct spi_driver wm0010_spi_driver = { 988 .driver = { 989 .name = "wm0010", 990 }, 991 .probe = wm0010_spi_probe, 992 .remove = wm0010_spi_remove, 993}; 994 995module_spi_driver(wm0010_spi_driver); 996 997MODULE_DESCRIPTION("ASoC WM0010 driver"); 998MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 999MODULE_LICENSE("GPL"); 1000