1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * tlv320aic32x4.h
4 */
5
6
7#ifndef _TLV320AIC32X4_H
8#define _TLV320AIC32X4_H
9
10struct device;
11struct regmap_config;
12
13extern const struct regmap_config aic32x4_regmap_config;
14int aic32x4_probe(struct device *dev, struct regmap *regmap);
15int aic32x4_remove(struct device *dev);
16int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
17
18/* tlv320aic32x4 register space (in decimal to match datasheet) */
19
20#define AIC32X4_REG(page, reg)	((page * 128) + reg)
21
22#define	AIC32X4_PSEL		AIC32X4_REG(0, 0)
23
24#define	AIC32X4_RESET		AIC32X4_REG(0, 1)
25#define	AIC32X4_CLKMUX		AIC32X4_REG(0, 4)
26#define	AIC32X4_PLLPR		AIC32X4_REG(0, 5)
27#define	AIC32X4_PLLJ		AIC32X4_REG(0, 6)
28#define	AIC32X4_PLLDMSB		AIC32X4_REG(0, 7)
29#define	AIC32X4_PLLDLSB		AIC32X4_REG(0, 8)
30#define	AIC32X4_NDAC		AIC32X4_REG(0, 11)
31#define	AIC32X4_MDAC		AIC32X4_REG(0, 12)
32#define AIC32X4_DOSRMSB		AIC32X4_REG(0, 13)
33#define AIC32X4_DOSRLSB		AIC32X4_REG(0, 14)
34#define	AIC32X4_NADC		AIC32X4_REG(0, 18)
35#define	AIC32X4_MADC		AIC32X4_REG(0, 19)
36#define AIC32X4_AOSR		AIC32X4_REG(0, 20)
37#define AIC32X4_CLKMUX2		AIC32X4_REG(0, 25)
38#define AIC32X4_CLKOUTM		AIC32X4_REG(0, 26)
39#define AIC32X4_IFACE1		AIC32X4_REG(0, 27)
40#define AIC32X4_IFACE2		AIC32X4_REG(0, 28)
41#define AIC32X4_IFACE3		AIC32X4_REG(0, 29)
42#define AIC32X4_BCLKN		AIC32X4_REG(0, 30)
43#define AIC32X4_IFACE4		AIC32X4_REG(0, 31)
44#define AIC32X4_IFACE5		AIC32X4_REG(0, 32)
45#define AIC32X4_IFACE6		AIC32X4_REG(0, 33)
46#define AIC32X4_GPIOCTL		AIC32X4_REG(0, 52)
47#define AIC32X4_DOUTCTL		AIC32X4_REG(0, 53)
48#define AIC32X4_DINCTL		AIC32X4_REG(0, 54)
49#define AIC32X4_MISOCTL		AIC32X4_REG(0, 55)
50#define AIC32X4_SCLKCTL		AIC32X4_REG(0, 56)
51#define AIC32X4_DACSPB		AIC32X4_REG(0, 60)
52#define AIC32X4_ADCSPB		AIC32X4_REG(0, 61)
53#define AIC32X4_DACSETUP	AIC32X4_REG(0, 63)
54#define AIC32X4_DACMUTE		AIC32X4_REG(0, 64)
55#define AIC32X4_LDACVOL		AIC32X4_REG(0, 65)
56#define AIC32X4_RDACVOL		AIC32X4_REG(0, 66)
57#define AIC32X4_ADCSETUP	AIC32X4_REG(0, 81)
58#define	AIC32X4_ADCFGA		AIC32X4_REG(0, 82)
59#define AIC32X4_LADCVOL		AIC32X4_REG(0, 83)
60#define AIC32X4_RADCVOL		AIC32X4_REG(0, 84)
61#define AIC32X4_LAGC1		AIC32X4_REG(0, 86)
62#define AIC32X4_LAGC2		AIC32X4_REG(0, 87)
63#define AIC32X4_LAGC3		AIC32X4_REG(0, 88)
64#define AIC32X4_LAGC4		AIC32X4_REG(0, 89)
65#define AIC32X4_LAGC5		AIC32X4_REG(0, 90)
66#define AIC32X4_LAGC6		AIC32X4_REG(0, 91)
67#define AIC32X4_LAGC7		AIC32X4_REG(0, 92)
68#define AIC32X4_RAGC1		AIC32X4_REG(0, 94)
69#define AIC32X4_RAGC2		AIC32X4_REG(0, 95)
70#define AIC32X4_RAGC3		AIC32X4_REG(0, 96)
71#define AIC32X4_RAGC4		AIC32X4_REG(0, 97)
72#define AIC32X4_RAGC5		AIC32X4_REG(0, 98)
73#define AIC32X4_RAGC6		AIC32X4_REG(0, 99)
74#define AIC32X4_RAGC7		AIC32X4_REG(0, 100)
75
76#define AIC32X4_PWRCFG		AIC32X4_REG(1, 1)
77#define AIC32X4_LDOCTL		AIC32X4_REG(1, 2)
78#define AIC32X4_LPLAYBACK	AIC32X4_REG(1, 3)
79#define AIC32X4_RPLAYBACK	AIC32X4_REG(1, 4)
80#define AIC32X4_OUTPWRCTL	AIC32X4_REG(1, 9)
81#define AIC32X4_CMMODE		AIC32X4_REG(1, 10)
82#define AIC32X4_HPLROUTE	AIC32X4_REG(1, 12)
83#define AIC32X4_HPRROUTE	AIC32X4_REG(1, 13)
84#define AIC32X4_LOLROUTE	AIC32X4_REG(1, 14)
85#define AIC32X4_LORROUTE	AIC32X4_REG(1, 15)
86#define	AIC32X4_HPLGAIN		AIC32X4_REG(1, 16)
87#define	AIC32X4_HPRGAIN		AIC32X4_REG(1, 17)
88#define	AIC32X4_LOLGAIN		AIC32X4_REG(1, 18)
89#define	AIC32X4_LORGAIN		AIC32X4_REG(1, 19)
90#define AIC32X4_HEADSTART	AIC32X4_REG(1, 20)
91#define AIC32X4_MICBIAS		AIC32X4_REG(1, 51)
92#define AIC32X4_LMICPGAPIN	AIC32X4_REG(1, 52)
93#define AIC32X4_LMICPGANIN	AIC32X4_REG(1, 54)
94#define AIC32X4_RMICPGAPIN	AIC32X4_REG(1, 55)
95#define AIC32X4_RMICPGANIN	AIC32X4_REG(1, 57)
96#define AIC32X4_FLOATINGINPUT	AIC32X4_REG(1, 58)
97#define AIC32X4_LMICPGAVOL	AIC32X4_REG(1, 59)
98#define AIC32X4_RMICPGAVOL	AIC32X4_REG(1, 60)
99#define AIC32X4_REFPOWERUP	AIC32X4_REG(1, 123)
100
101/* Bits, masks, and shifts */
102
103/* AIC32X4_CLKMUX */
104#define AIC32X4_PLL_CLKIN_MASK		GENMASK(3, 2)
105#define AIC32X4_PLL_CLKIN_SHIFT		(2)
106#define AIC32X4_PLL_CLKIN_MCLK		(0x00)
107#define AIC32X4_PLL_CLKIN_BCKL		(0x01)
108#define AIC32X4_PLL_CLKIN_GPIO1		(0x02)
109#define AIC32X4_PLL_CLKIN_DIN		(0x03)
110#define AIC32X4_CODEC_CLKIN_MASK	GENMASK(1, 0)
111#define AIC32X4_CODEC_CLKIN_SHIFT	(0)
112#define AIC32X4_CODEC_CLKIN_MCLK	(0x00)
113#define AIC32X4_CODEC_CLKIN_BCLK	(0x01)
114#define AIC32X4_CODEC_CLKIN_GPIO1	(0x02)
115#define AIC32X4_CODEC_CLKIN_PLL		(0x03)
116
117/* AIC32X4_PLLPR */
118#define AIC32X4_PLLEN			BIT(7)
119#define AIC32X4_PLL_P_MASK		GENMASK(6, 4)
120#define AIC32X4_PLL_P_SHIFT		(4)
121#define AIC32X4_PLL_R_MASK		GENMASK(3, 0)
122
123/* AIC32X4_NDAC */
124#define AIC32X4_NDACEN			BIT(7)
125#define AIC32X4_NDAC_MASK		GENMASK(6, 0)
126
127/* AIC32X4_MDAC */
128#define AIC32X4_MDACEN			BIT(7)
129#define AIC32X4_MDAC_MASK		GENMASK(6, 0)
130
131/* AIC32X4_NADC */
132#define AIC32X4_NADCEN			BIT(7)
133#define AIC32X4_NADC_MASK		GENMASK(6, 0)
134
135/* AIC32X4_MADC */
136#define AIC32X4_MADCEN			BIT(7)
137#define AIC32X4_MADC_MASK		GENMASK(6, 0)
138
139/* AIC32X4_BCLKN */
140#define AIC32X4_BCLKEN			BIT(7)
141#define AIC32X4_BCLK_MASK		GENMASK(6, 0)
142
143/* AIC32X4_IFACE1 */
144#define AIC32X4_IFACE1_DATATYPE_MASK	GENMASK(7, 6)
145#define AIC32X4_IFACE1_DATATYPE_SHIFT	(6)
146#define AIC32X4_I2S_MODE		(0x00)
147#define AIC32X4_DSP_MODE		(0x01)
148#define AIC32X4_RIGHT_JUSTIFIED_MODE	(0x02)
149#define AIC32X4_LEFT_JUSTIFIED_MODE	(0x03)
150#define AIC32X4_IFACE1_DATALEN_MASK	GENMASK(5, 4)
151#define AIC32X4_IFACE1_DATALEN_SHIFT	(4)
152#define AIC32X4_WORD_LEN_16BITS		(0x00)
153#define AIC32X4_WORD_LEN_20BITS		(0x01)
154#define AIC32X4_WORD_LEN_24BITS		(0x02)
155#define AIC32X4_WORD_LEN_32BITS		(0x03)
156#define AIC32X4_IFACE1_MASTER_MASK	GENMASK(3, 2)
157#define AIC32X4_BCLKMASTER		BIT(2)
158#define AIC32X4_WCLKMASTER		BIT(3)
159
160/* AIC32X4_IFACE2 */
161#define AIC32X4_DATA_OFFSET_MASK	GENMASK(7, 0)
162
163/* AIC32X4_IFACE3 */
164#define AIC32X4_BCLKINV_MASK		BIT(3)
165#define AIC32X4_BDIVCLK_MASK		GENMASK(1, 0)
166#define AIC32X4_BDIVCLK_SHIFT		(0)
167#define AIC32X4_DAC2BCLK		(0x00)
168#define AIC32X4_DACMOD2BCLK		(0x01)
169#define AIC32X4_ADC2BCLK		(0x02)
170#define AIC32X4_ADCMOD2BCLK		(0x03)
171
172/* AIC32X4_DACSETUP */
173#define AIC32X4_DAC_CHAN_MASK		GENMASK(5, 2)
174#define AIC32X4_LDAC2RCHN		BIT(5)
175#define AIC32X4_LDAC2LCHN		BIT(4)
176#define AIC32X4_RDAC2LCHN		BIT(3)
177#define AIC32X4_RDAC2RCHN		BIT(2)
178
179/* AIC32X4_DACMUTE */
180#define AIC32X4_MUTEON			0x0C
181
182/* AIC32X4_ADCSETUP */
183#define AIC32X4_LADC_EN			BIT(7)
184#define AIC32X4_RADC_EN			BIT(6)
185
186/* AIC32X4_PWRCFG */
187#define AIC32X4_AVDDWEAKDISABLE		BIT(3)
188
189/* AIC32X4_LDOCTL */
190#define AIC32X4_LDOCTLEN		BIT(0)
191
192/* AIC32X4_CMMODE */
193#define AIC32X4_LDOIN_18_36		BIT(0)
194#define AIC32X4_LDOIN2HP		BIT(1)
195
196/* AIC32X4_MICBIAS */
197#define AIC32X4_MICBIAS_LDOIN		BIT(3)
198#define AIC32X4_MICBIAS_2075V		0x60
199#define AIC32x4_MICBIAS_MASK            GENMASK(6, 3)
200
201/* AIC32X4_LMICPGANIN */
202#define AIC32X4_LMICPGANIN_IN2R_10K	0x10
203#define AIC32X4_LMICPGANIN_CM1L_10K	0x40
204
205/* AIC32X4_RMICPGANIN */
206#define AIC32X4_RMICPGANIN_IN1L_10K	0x10
207#define AIC32X4_RMICPGANIN_CM1R_10K	0x40
208
209/* AIC32X4_REFPOWERUP */
210#define AIC32X4_REFPOWERUP_SLOW		0x04
211#define AIC32X4_REFPOWERUP_40MS		0x05
212#define AIC32X4_REFPOWERUP_80MS		0x06
213#define AIC32X4_REFPOWERUP_120MS	0x07
214
215/* Common mask and enable for all of the dividers */
216#define AIC32X4_DIVEN           BIT(7)
217#define AIC32X4_DIV_MASK        GENMASK(6, 0)
218
219/* Clock Limits */
220#define AIC32X4_MAX_DOSR_FREQ		6200000
221#define AIC32X4_MIN_DOSR_FREQ		2800000
222#define AIC32X4_MAX_CODEC_CLKIN_FREQ    110000000
223#define AIC32X4_MAX_PLL_CLKIN		20000000
224
225#endif				/* _TLV320AIC32X4_H */
226