1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Clock Tree for the Texas Instruments TLV320AIC32x4 4 * 5 * Copyright 2019 Annaliese McDermond 6 * 7 * Author: Annaliese McDermond <nh6z@nh6z.net> 8 */ 9 10#include <linux/clk-provider.h> 11#include <linux/clkdev.h> 12#include <linux/regmap.h> 13#include <linux/device.h> 14 15#include "tlv320aic32x4.h" 16 17#define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw) 18struct clk_aic32x4 { 19 struct clk_hw hw; 20 struct device *dev; 21 struct regmap *regmap; 22 unsigned int reg; 23}; 24 25/* 26 * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings 27 * @p: Divider 28 * @r: first multiplier 29 * @j: integer part of second multiplier 30 * @d: decimal part of second multiplier 31 */ 32struct clk_aic32x4_pll_muldiv { 33 u8 p; 34 u16 r; 35 u8 j; 36 u16 d; 37}; 38 39struct aic32x4_clkdesc { 40 const char *name; 41 const char * const *parent_names; 42 unsigned int num_parents; 43 const struct clk_ops *ops; 44 unsigned int reg; 45}; 46 47static int clk_aic32x4_pll_prepare(struct clk_hw *hw) 48{ 49 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); 50 51 return regmap_update_bits(pll->regmap, AIC32X4_PLLPR, 52 AIC32X4_PLLEN, AIC32X4_PLLEN); 53} 54 55static void clk_aic32x4_pll_unprepare(struct clk_hw *hw) 56{ 57 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); 58 59 regmap_update_bits(pll->regmap, AIC32X4_PLLPR, 60 AIC32X4_PLLEN, 0); 61} 62 63static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw) 64{ 65 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); 66 67 unsigned int val; 68 int ret; 69 70 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); 71 if (ret < 0) 72 return ret; 73 74 return !!(val & AIC32X4_PLLEN); 75} 76 77static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll, 78 struct clk_aic32x4_pll_muldiv *settings) 79{ 80 /* Change to use regmap_bulk_read? */ 81 unsigned int val; 82 int ret; 83 84 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); 85 if (ret < 0) 86 return ret; 87 settings->r = val & AIC32X4_PLL_R_MASK; 88 settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT; 89 90 ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val); 91 if (ret < 0) 92 return ret; 93 settings->j = val; 94 95 ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val); 96 if (ret < 0) 97 return ret; 98 settings->d = val << 8; 99 100 ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val); 101 if (ret < 0) 102 return ret; 103 settings->d |= val; 104 105 return 0; 106} 107 108static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll, 109 struct clk_aic32x4_pll_muldiv *settings) 110{ 111 int ret; 112 /* Change to use regmap_bulk_write for some if not all? */ 113 114 ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR, 115 AIC32X4_PLL_R_MASK, settings->r); 116 if (ret < 0) 117 return ret; 118 119 ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR, 120 AIC32X4_PLL_P_MASK, 121 settings->p << AIC32X4_PLL_P_SHIFT); 122 if (ret < 0) 123 return ret; 124 125 ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j); 126 if (ret < 0) 127 return ret; 128 129 ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8)); 130 if (ret < 0) 131 return ret; 132 ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff)); 133 if (ret < 0) 134 return ret; 135 136 return 0; 137} 138 139static unsigned long clk_aic32x4_pll_calc_rate( 140 struct clk_aic32x4_pll_muldiv *settings, 141 unsigned long parent_rate) 142{ 143 u64 rate; 144 /* 145 * We scale j by 10000 to account for the decimal part of P and divide 146 * it back out later. 147 */ 148 rate = (u64) parent_rate * settings->r * 149 ((settings->j * 10000) + settings->d); 150 151 return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000); 152} 153 154static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings, 155 unsigned long rate, unsigned long parent_rate) 156{ 157 u64 multiplier; 158 159 settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1; 160 if (settings->p > 8) 161 return -1; 162 163 /* 164 * We scale this figure by 10000 so that we can get the decimal part 165 * of the multiplier. This is because we can't do floating point 166 * math in the kernel. 167 */ 168 multiplier = (u64) rate * settings->p * 10000; 169 do_div(multiplier, parent_rate); 170 171 /* 172 * J can't be over 64, so R can scale this. 173 * R can't be greater than 4. 174 */ 175 settings->r = ((u32) multiplier / 640000) + 1; 176 if (settings->r > 4) 177 return -1; 178 do_div(multiplier, settings->r); 179 180 /* 181 * J can't be < 1. 182 */ 183 if (multiplier < 10000) 184 return -1; 185 186 /* Figure out the integer part, J, and the fractional part, D. */ 187 settings->j = (u32) multiplier / 10000; 188 settings->d = (u32) multiplier % 10000; 189 190 return 0; 191} 192 193static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw, 194 unsigned long parent_rate) 195{ 196 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); 197 struct clk_aic32x4_pll_muldiv settings; 198 int ret; 199 200 ret = clk_aic32x4_pll_get_muldiv(pll, &settings); 201 if (ret < 0) 202 return 0; 203 204 return clk_aic32x4_pll_calc_rate(&settings, parent_rate); 205} 206 207static long clk_aic32x4_pll_round_rate(struct clk_hw *hw, 208 unsigned long rate, 209 unsigned long *parent_rate) 210{ 211 struct clk_aic32x4_pll_muldiv settings; 212 int ret; 213 214 ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate); 215 if (ret < 0) 216 return 0; 217 218 return clk_aic32x4_pll_calc_rate(&settings, *parent_rate); 219} 220 221static int clk_aic32x4_pll_set_rate(struct clk_hw *hw, 222 unsigned long rate, 223 unsigned long parent_rate) 224{ 225 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); 226 struct clk_aic32x4_pll_muldiv settings; 227 int ret; 228 229 ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate); 230 if (ret < 0) 231 return -EINVAL; 232 233 ret = clk_aic32x4_pll_set_muldiv(pll, &settings); 234 if (ret) 235 return ret; 236 237 /* 10ms is the delay to wait before the clocks are stable */ 238 msleep(10); 239 240 return 0; 241} 242 243static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index) 244{ 245 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); 246 247 return regmap_update_bits(pll->regmap, 248 AIC32X4_CLKMUX, 249 AIC32X4_PLL_CLKIN_MASK, 250 index << AIC32X4_PLL_CLKIN_SHIFT); 251} 252 253static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw) 254{ 255 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); 256 unsigned int val; 257 258 regmap_read(pll->regmap, AIC32X4_PLLPR, &val); 259 260 return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT; 261} 262 263 264static const struct clk_ops aic32x4_pll_ops = { 265 .prepare = clk_aic32x4_pll_prepare, 266 .unprepare = clk_aic32x4_pll_unprepare, 267 .is_prepared = clk_aic32x4_pll_is_prepared, 268 .recalc_rate = clk_aic32x4_pll_recalc_rate, 269 .round_rate = clk_aic32x4_pll_round_rate, 270 .set_rate = clk_aic32x4_pll_set_rate, 271 .set_parent = clk_aic32x4_pll_set_parent, 272 .get_parent = clk_aic32x4_pll_get_parent, 273}; 274 275static int clk_aic32x4_codec_clkin_set_parent(struct clk_hw *hw, u8 index) 276{ 277 struct clk_aic32x4 *mux = to_clk_aic32x4(hw); 278 279 return regmap_update_bits(mux->regmap, 280 AIC32X4_CLKMUX, 281 AIC32X4_CODEC_CLKIN_MASK, index << AIC32X4_CODEC_CLKIN_SHIFT); 282} 283 284static u8 clk_aic32x4_codec_clkin_get_parent(struct clk_hw *hw) 285{ 286 struct clk_aic32x4 *mux = to_clk_aic32x4(hw); 287 unsigned int val; 288 289 regmap_read(mux->regmap, AIC32X4_CLKMUX, &val); 290 291 return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT; 292} 293 294static const struct clk_ops aic32x4_codec_clkin_ops = { 295 .set_parent = clk_aic32x4_codec_clkin_set_parent, 296 .get_parent = clk_aic32x4_codec_clkin_get_parent, 297}; 298 299static int clk_aic32x4_div_prepare(struct clk_hw *hw) 300{ 301 struct clk_aic32x4 *div = to_clk_aic32x4(hw); 302 303 return regmap_update_bits(div->regmap, div->reg, 304 AIC32X4_DIVEN, AIC32X4_DIVEN); 305} 306 307static void clk_aic32x4_div_unprepare(struct clk_hw *hw) 308{ 309 struct clk_aic32x4 *div = to_clk_aic32x4(hw); 310 311 regmap_update_bits(div->regmap, div->reg, 312 AIC32X4_DIVEN, 0); 313} 314 315static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate, 316 unsigned long parent_rate) 317{ 318 struct clk_aic32x4 *div = to_clk_aic32x4(hw); 319 u8 divisor; 320 321 divisor = DIV_ROUND_UP(parent_rate, rate); 322 if (divisor > 128) 323 return -EINVAL; 324 325 return regmap_update_bits(div->regmap, div->reg, 326 AIC32X4_DIV_MASK, divisor); 327} 328 329static long clk_aic32x4_div_round_rate(struct clk_hw *hw, unsigned long rate, 330 unsigned long *parent_rate) 331{ 332 unsigned long divisor; 333 334 divisor = DIV_ROUND_UP(*parent_rate, rate); 335 if (divisor > 128) 336 return -EINVAL; 337 338 return DIV_ROUND_UP(*parent_rate, divisor); 339} 340 341static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw, 342 unsigned long parent_rate) 343{ 344 struct clk_aic32x4 *div = to_clk_aic32x4(hw); 345 346 unsigned int val; 347 348 regmap_read(div->regmap, div->reg, &val); 349 350 return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK); 351} 352 353static const struct clk_ops aic32x4_div_ops = { 354 .prepare = clk_aic32x4_div_prepare, 355 .unprepare = clk_aic32x4_div_unprepare, 356 .set_rate = clk_aic32x4_div_set_rate, 357 .round_rate = clk_aic32x4_div_round_rate, 358 .recalc_rate = clk_aic32x4_div_recalc_rate, 359}; 360 361static int clk_aic32x4_bdiv_set_parent(struct clk_hw *hw, u8 index) 362{ 363 struct clk_aic32x4 *mux = to_clk_aic32x4(hw); 364 365 return regmap_update_bits(mux->regmap, AIC32X4_IFACE3, 366 AIC32X4_BDIVCLK_MASK, index); 367} 368 369static u8 clk_aic32x4_bdiv_get_parent(struct clk_hw *hw) 370{ 371 struct clk_aic32x4 *mux = to_clk_aic32x4(hw); 372 unsigned int val; 373 374 regmap_read(mux->regmap, AIC32X4_IFACE3, &val); 375 376 return val & AIC32X4_BDIVCLK_MASK; 377} 378 379static const struct clk_ops aic32x4_bdiv_ops = { 380 .prepare = clk_aic32x4_div_prepare, 381 .unprepare = clk_aic32x4_div_unprepare, 382 .set_parent = clk_aic32x4_bdiv_set_parent, 383 .get_parent = clk_aic32x4_bdiv_get_parent, 384 .set_rate = clk_aic32x4_div_set_rate, 385 .round_rate = clk_aic32x4_div_round_rate, 386 .recalc_rate = clk_aic32x4_div_recalc_rate, 387}; 388 389static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = { 390 { 391 .name = "pll", 392 .parent_names = 393 (const char* []) { "mclk", "bclk", "gpio", "din" }, 394 .num_parents = 4, 395 .ops = &aic32x4_pll_ops, 396 .reg = 0, 397 }, 398 { 399 .name = "codec_clkin", 400 .parent_names = 401 (const char *[]) { "mclk", "bclk", "gpio", "pll" }, 402 .num_parents = 4, 403 .ops = &aic32x4_codec_clkin_ops, 404 .reg = 0, 405 }, 406 { 407 .name = "ndac", 408 .parent_names = (const char * []) { "codec_clkin" }, 409 .num_parents = 1, 410 .ops = &aic32x4_div_ops, 411 .reg = AIC32X4_NDAC, 412 }, 413 { 414 .name = "mdac", 415 .parent_names = (const char * []) { "ndac" }, 416 .num_parents = 1, 417 .ops = &aic32x4_div_ops, 418 .reg = AIC32X4_MDAC, 419 }, 420 { 421 .name = "nadc", 422 .parent_names = (const char * []) { "codec_clkin" }, 423 .num_parents = 1, 424 .ops = &aic32x4_div_ops, 425 .reg = AIC32X4_NADC, 426 }, 427 { 428 .name = "madc", 429 .parent_names = (const char * []) { "nadc" }, 430 .num_parents = 1, 431 .ops = &aic32x4_div_ops, 432 .reg = AIC32X4_MADC, 433 }, 434 { 435 .name = "bdiv", 436 .parent_names = 437 (const char *[]) { "ndac", "mdac", "nadc", "madc" }, 438 .num_parents = 4, 439 .ops = &aic32x4_bdiv_ops, 440 .reg = AIC32X4_BCLKN, 441 }, 442}; 443 444static struct clk *aic32x4_register_clk(struct device *dev, 445 struct aic32x4_clkdesc *desc) 446{ 447 struct clk_init_data init; 448 struct clk_aic32x4 *priv; 449 const char *devname = dev_name(dev); 450 451 init.ops = desc->ops; 452 init.name = desc->name; 453 init.parent_names = desc->parent_names; 454 init.num_parents = desc->num_parents; 455 init.flags = 0; 456 457 priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL); 458 if (priv == NULL) 459 return (struct clk *) -ENOMEM; 460 461 priv->dev = dev; 462 priv->hw.init = &init; 463 priv->regmap = dev_get_regmap(dev, NULL); 464 priv->reg = desc->reg; 465 466 clk_hw_register_clkdev(&priv->hw, desc->name, devname); 467 return devm_clk_register(dev, &priv->hw); 468} 469 470int aic32x4_register_clocks(struct device *dev, const char *mclk_name) 471{ 472 int i; 473 474 /* 475 * These lines are here to preserve the current functionality of 476 * the driver with regard to the DT. These should eventually be set 477 * by DT nodes so that the connections can be set up in configuration 478 * rather than code. 479 */ 480 aic32x4_clkdesc_array[0].parent_names = 481 (const char* []) { mclk_name, "bclk", "gpio", "din" }; 482 aic32x4_clkdesc_array[1].parent_names = 483 (const char *[]) { mclk_name, "bclk", "gpio", "pll" }; 484 485 for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i) 486 aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]); 487 488 return 0; 489} 490EXPORT_SYMBOL_GPL(aic32x4_register_clocks); 491