1// SPDX-License-Identifier: GPL-2.0 2// TLV320ADCX140 Sound driver 3// Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4 5#include <linux/module.h> 6#include <linux/moduleparam.h> 7#include <linux/init.h> 8#include <linux/delay.h> 9#include <linux/pm.h> 10#include <linux/i2c.h> 11#include <linux/gpio/consumer.h> 12#include <linux/regulator/consumer.h> 13#include <linux/acpi.h> 14#include <linux/of.h> 15#include <linux/of_gpio.h> 16#include <linux/slab.h> 17#include <sound/core.h> 18#include <sound/pcm.h> 19#include <sound/pcm_params.h> 20#include <sound/soc.h> 21#include <sound/initval.h> 22#include <sound/tlv.h> 23 24#include "tlv320adcx140.h" 25 26struct adcx140_priv { 27 struct snd_soc_component *component; 28 struct regulator *supply_areg; 29 struct gpio_desc *gpio_reset; 30 struct regmap *regmap; 31 struct device *dev; 32 33 bool micbias_vg; 34 35 unsigned int dai_fmt; 36 unsigned int tdm_delay; 37 unsigned int slot_width; 38}; 39 40static const char * const gpo_config_names[] = { 41 "ti,gpo-config-1", 42 "ti,gpo-config-2", 43 "ti,gpo-config-3", 44 "ti,gpo-config-4", 45}; 46 47static const struct reg_default adcx140_reg_defaults[] = { 48 { ADCX140_PAGE_SELECT, 0x00 }, 49 { ADCX140_SW_RESET, 0x00 }, 50 { ADCX140_SLEEP_CFG, 0x00 }, 51 { ADCX140_SHDN_CFG, 0x05 }, 52 { ADCX140_ASI_CFG0, 0x30 }, 53 { ADCX140_ASI_CFG1, 0x00 }, 54 { ADCX140_ASI_CFG2, 0x00 }, 55 { ADCX140_ASI_CH1, 0x00 }, 56 { ADCX140_ASI_CH2, 0x01 }, 57 { ADCX140_ASI_CH3, 0x02 }, 58 { ADCX140_ASI_CH4, 0x03 }, 59 { ADCX140_ASI_CH5, 0x04 }, 60 { ADCX140_ASI_CH6, 0x05 }, 61 { ADCX140_ASI_CH7, 0x06 }, 62 { ADCX140_ASI_CH8, 0x07 }, 63 { ADCX140_MST_CFG0, 0x02 }, 64 { ADCX140_MST_CFG1, 0x48 }, 65 { ADCX140_ASI_STS, 0xff }, 66 { ADCX140_CLK_SRC, 0x10 }, 67 { ADCX140_PDMCLK_CFG, 0x40 }, 68 { ADCX140_PDM_CFG, 0x00 }, 69 { ADCX140_GPIO_CFG0, 0x22 }, 70 { ADCX140_GPO_CFG0, 0x00 }, 71 { ADCX140_GPO_CFG1, 0x00 }, 72 { ADCX140_GPO_CFG2, 0x00 }, 73 { ADCX140_GPO_CFG3, 0x00 }, 74 { ADCX140_GPO_VAL, 0x00 }, 75 { ADCX140_GPIO_MON, 0x00 }, 76 { ADCX140_GPI_CFG0, 0x00 }, 77 { ADCX140_GPI_CFG1, 0x00 }, 78 { ADCX140_GPI_MON, 0x00 }, 79 { ADCX140_INT_CFG, 0x00 }, 80 { ADCX140_INT_MASK0, 0xff }, 81 { ADCX140_INT_LTCH0, 0x00 }, 82 { ADCX140_BIAS_CFG, 0x00 }, 83 { ADCX140_CH1_CFG0, 0x00 }, 84 { ADCX140_CH1_CFG1, 0x00 }, 85 { ADCX140_CH1_CFG2, 0xc9 }, 86 { ADCX140_CH1_CFG3, 0x80 }, 87 { ADCX140_CH1_CFG4, 0x00 }, 88 { ADCX140_CH2_CFG0, 0x00 }, 89 { ADCX140_CH2_CFG1, 0x00 }, 90 { ADCX140_CH2_CFG2, 0xc9 }, 91 { ADCX140_CH2_CFG3, 0x80 }, 92 { ADCX140_CH2_CFG4, 0x00 }, 93 { ADCX140_CH3_CFG0, 0x00 }, 94 { ADCX140_CH3_CFG1, 0x00 }, 95 { ADCX140_CH3_CFG2, 0xc9 }, 96 { ADCX140_CH3_CFG3, 0x80 }, 97 { ADCX140_CH3_CFG4, 0x00 }, 98 { ADCX140_CH4_CFG0, 0x00 }, 99 { ADCX140_CH4_CFG1, 0x00 }, 100 { ADCX140_CH4_CFG2, 0xc9 }, 101 { ADCX140_CH4_CFG3, 0x80 }, 102 { ADCX140_CH4_CFG4, 0x00 }, 103 { ADCX140_CH5_CFG2, 0xc9 }, 104 { ADCX140_CH5_CFG3, 0x80 }, 105 { ADCX140_CH5_CFG4, 0x00 }, 106 { ADCX140_CH6_CFG2, 0xc9 }, 107 { ADCX140_CH6_CFG3, 0x80 }, 108 { ADCX140_CH6_CFG4, 0x00 }, 109 { ADCX140_CH7_CFG2, 0xc9 }, 110 { ADCX140_CH7_CFG3, 0x80 }, 111 { ADCX140_CH7_CFG4, 0x00 }, 112 { ADCX140_CH8_CFG2, 0xc9 }, 113 { ADCX140_CH8_CFG3, 0x80 }, 114 { ADCX140_CH8_CFG4, 0x00 }, 115 { ADCX140_DSP_CFG0, 0x01 }, 116 { ADCX140_DSP_CFG1, 0x40 }, 117 { ADCX140_DRE_CFG0, 0x7b }, 118 { ADCX140_AGC_CFG0, 0xe7 }, 119 { ADCX140_IN_CH_EN, 0xf0 }, 120 { ADCX140_ASI_OUT_CH_EN, 0x00 }, 121 { ADCX140_PWR_CFG, 0x00 }, 122 { ADCX140_DEV_STS0, 0x00 }, 123 { ADCX140_DEV_STS1, 0x80 }, 124}; 125 126static const struct regmap_range_cfg adcx140_ranges[] = { 127 { 128 .range_min = 0, 129 .range_max = 12 * 128, 130 .selector_reg = ADCX140_PAGE_SELECT, 131 .selector_mask = 0xff, 132 .selector_shift = 0, 133 .window_start = 0, 134 .window_len = 128, 135 }, 136}; 137 138static bool adcx140_volatile(struct device *dev, unsigned int reg) 139{ 140 switch (reg) { 141 case ADCX140_SW_RESET: 142 case ADCX140_DEV_STS0: 143 case ADCX140_DEV_STS1: 144 case ADCX140_ASI_STS: 145 return true; 146 default: 147 return false; 148 } 149} 150 151static const struct regmap_config adcx140_i2c_regmap = { 152 .reg_bits = 8, 153 .val_bits = 8, 154 .reg_defaults = adcx140_reg_defaults, 155 .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults), 156 .cache_type = REGCACHE_FLAT, 157 .ranges = adcx140_ranges, 158 .num_ranges = ARRAY_SIZE(adcx140_ranges), 159 .max_register = 12 * 128, 160 .volatile_reg = adcx140_volatile, 161}; 162 163/* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */ 164static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0); 165 166/* ADC gain. From 0 to 42 dB in 1 dB steps */ 167static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0); 168 169/* DRE Level. From -12 dB to -66 dB in 1 dB steps */ 170static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0); 171/* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */ 172static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0); 173 174/* AGC Level. From -6 dB to -36 dB in 2 dB steps */ 175static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0); 176/* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */ 177static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0); 178 179static const char * const decimation_filter_text[] = { 180 "Linear Phase", "Low Latency", "Ultra-low Latency" 181}; 182 183static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4, 184 decimation_filter_text); 185 186static const struct snd_kcontrol_new decimation_filter_controls[] = { 187 SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum), 188}; 189 190static const char * const pdmclk_text[] = { 191 "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz" 192}; 193 194static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0, 195 pdmclk_text); 196 197static const struct snd_kcontrol_new pdmclk_div_controls[] = { 198 SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum), 199}; 200 201static const char * const resistor_text[] = { 202 "2.5 kOhm", "10 kOhm", "20 kOhm" 203}; 204 205static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2, 206 resistor_text); 207static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2, 208 resistor_text); 209static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2, 210 resistor_text); 211static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2, 212 resistor_text); 213 214static const struct snd_kcontrol_new in1_resistor_controls[] = { 215 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum), 216}; 217static const struct snd_kcontrol_new in2_resistor_controls[] = { 218 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum), 219}; 220static const struct snd_kcontrol_new in3_resistor_controls[] = { 221 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum), 222}; 223static const struct snd_kcontrol_new in4_resistor_controls[] = { 224 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum), 225}; 226 227/* Analog/Digital Selection */ 228static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"}; 229static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"}; 230 231static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum, 232 ADCX140_CH1_CFG0, 5, 233 adcx140_mic_sel_text); 234 235static const struct snd_kcontrol_new adcx140_dapm_mic1p_control = 236SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum); 237 238static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum, 239 ADCX140_CH1_CFG0, 7, 240 adcx140_analog_sel_text); 241 242static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control = 243SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum); 244 245static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum, 246 ADCX140_CH1_CFG0, 5, 247 adcx140_mic_sel_text); 248 249static const struct snd_kcontrol_new adcx140_dapm_mic1m_control = 250SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum); 251 252static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum, 253 ADCX140_CH2_CFG0, 5, 254 adcx140_mic_sel_text); 255 256static const struct snd_kcontrol_new adcx140_dapm_mic2p_control = 257SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum); 258 259static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum, 260 ADCX140_CH2_CFG0, 7, 261 adcx140_analog_sel_text); 262 263static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control = 264SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum); 265 266static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum, 267 ADCX140_CH2_CFG0, 5, 268 adcx140_mic_sel_text); 269 270static const struct snd_kcontrol_new adcx140_dapm_mic2m_control = 271SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum); 272 273static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum, 274 ADCX140_CH3_CFG0, 5, 275 adcx140_mic_sel_text); 276 277static const struct snd_kcontrol_new adcx140_dapm_mic3p_control = 278SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum); 279 280static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum, 281 ADCX140_CH3_CFG0, 7, 282 adcx140_analog_sel_text); 283 284static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control = 285SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum); 286 287static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum, 288 ADCX140_CH3_CFG0, 5, 289 adcx140_mic_sel_text); 290 291static const struct snd_kcontrol_new adcx140_dapm_mic3m_control = 292SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum); 293 294static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum, 295 ADCX140_CH4_CFG0, 5, 296 adcx140_mic_sel_text); 297 298static const struct snd_kcontrol_new adcx140_dapm_mic4p_control = 299SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum); 300 301static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum, 302 ADCX140_CH4_CFG0, 7, 303 adcx140_analog_sel_text); 304 305static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control = 306SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum); 307 308static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum, 309 ADCX140_CH4_CFG0, 5, 310 adcx140_mic_sel_text); 311 312static const struct snd_kcontrol_new adcx140_dapm_mic4m_control = 313SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum); 314 315static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch = 316 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0); 317static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch = 318 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0); 319static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch = 320 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0); 321static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch = 322 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0); 323static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch = 324 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0); 325static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch = 326 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0); 327static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch = 328 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0); 329static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch = 330 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0); 331 332static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch = 333 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0); 334static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch = 335 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0); 336static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch = 337 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0); 338static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch = 339 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0); 340 341static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch = 342 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0); 343 344/* Output Mixer */ 345static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = { 346 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0), 347 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0), 348 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0), 349 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0), 350}; 351 352static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = { 353 /* Analog Differential Inputs */ 354 SND_SOC_DAPM_INPUT("MIC1P"), 355 SND_SOC_DAPM_INPUT("MIC1M"), 356 SND_SOC_DAPM_INPUT("MIC2P"), 357 SND_SOC_DAPM_INPUT("MIC2M"), 358 SND_SOC_DAPM_INPUT("MIC3P"), 359 SND_SOC_DAPM_INPUT("MIC3M"), 360 SND_SOC_DAPM_INPUT("MIC4P"), 361 SND_SOC_DAPM_INPUT("MIC4M"), 362 363 SND_SOC_DAPM_OUTPUT("CH1_OUT"), 364 SND_SOC_DAPM_OUTPUT("CH2_OUT"), 365 SND_SOC_DAPM_OUTPUT("CH3_OUT"), 366 SND_SOC_DAPM_OUTPUT("CH4_OUT"), 367 SND_SOC_DAPM_OUTPUT("CH5_OUT"), 368 SND_SOC_DAPM_OUTPUT("CH6_OUT"), 369 SND_SOC_DAPM_OUTPUT("CH7_OUT"), 370 SND_SOC_DAPM_OUTPUT("CH8_OUT"), 371 372 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0, 373 &adcx140_output_mixer_controls[0], 374 ARRAY_SIZE(adcx140_output_mixer_controls)), 375 376 /* Input Selection to MIC_PGA */ 377 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0, 378 &adcx140_dapm_mic1p_control), 379 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0, 380 &adcx140_dapm_mic2p_control), 381 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0, 382 &adcx140_dapm_mic3p_control), 383 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0, 384 &adcx140_dapm_mic4p_control), 385 386 /* Input Selection to MIC_PGA */ 387 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0, 388 &adcx140_dapm_mic1_analog_control), 389 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0, 390 &adcx140_dapm_mic2_analog_control), 391 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0, 392 &adcx140_dapm_mic3_analog_control), 393 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0, 394 &adcx140_dapm_mic4_analog_control), 395 396 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0, 397 &adcx140_dapm_mic1m_control), 398 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0, 399 &adcx140_dapm_mic2m_control), 400 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0, 401 &adcx140_dapm_mic3m_control), 402 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0, 403 &adcx140_dapm_mic4m_control), 404 405 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0), 406 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0), 407 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0), 408 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0), 409 410 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0), 411 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0), 412 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0), 413 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0), 414 415 SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0), 416 SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0), 417 SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0), 418 SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0), 419 SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0), 420 SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0), 421 SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0), 422 SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0), 423 424 425 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0, 426 &adcx140_dapm_ch1_en_switch), 427 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0, 428 &adcx140_dapm_ch2_en_switch), 429 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0, 430 &adcx140_dapm_ch3_en_switch), 431 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0, 432 &adcx140_dapm_ch4_en_switch), 433 434 SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0, 435 &adcx140_dapm_ch5_en_switch), 436 SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0, 437 &adcx140_dapm_ch6_en_switch), 438 SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0, 439 &adcx140_dapm_ch7_en_switch), 440 SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0, 441 &adcx140_dapm_ch8_en_switch), 442 443 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0, 444 &adcx140_dapm_dre_en_switch), 445 446 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0, 447 &adcx140_dapm_ch1_dre_en_switch), 448 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0, 449 &adcx140_dapm_ch2_dre_en_switch), 450 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0, 451 &adcx140_dapm_ch3_dre_en_switch), 452 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0, 453 &adcx140_dapm_ch4_dre_en_switch), 454 455 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 456 in1_resistor_controls), 457 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 458 in2_resistor_controls), 459 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 460 in3_resistor_controls), 461 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 462 in4_resistor_controls), 463 464 SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0, 465 pdmclk_div_controls), 466 467 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0, 468 decimation_filter_controls), 469}; 470 471static const struct snd_soc_dapm_route adcx140_audio_map[] = { 472 /* Outputs */ 473 {"CH1_OUT", NULL, "Output Mixer"}, 474 {"CH2_OUT", NULL, "Output Mixer"}, 475 {"CH3_OUT", NULL, "Output Mixer"}, 476 {"CH4_OUT", NULL, "Output Mixer"}, 477 478 {"CH1_ASI_EN", "Switch", "CH1_ADC"}, 479 {"CH2_ASI_EN", "Switch", "CH2_ADC"}, 480 {"CH3_ASI_EN", "Switch", "CH3_ADC"}, 481 {"CH4_ASI_EN", "Switch", "CH4_ADC"}, 482 483 {"CH1_ASI_EN", "Switch", "CH1_DIG"}, 484 {"CH2_ASI_EN", "Switch", "CH2_DIG"}, 485 {"CH3_ASI_EN", "Switch", "CH3_DIG"}, 486 {"CH4_ASI_EN", "Switch", "CH4_DIG"}, 487 {"CH5_ASI_EN", "Switch", "CH5_DIG"}, 488 {"CH6_ASI_EN", "Switch", "CH6_DIG"}, 489 {"CH7_ASI_EN", "Switch", "CH7_DIG"}, 490 {"CH8_ASI_EN", "Switch", "CH8_DIG"}, 491 492 {"CH5_ASI_EN", "Switch", "CH5_OUT"}, 493 {"CH6_ASI_EN", "Switch", "CH6_OUT"}, 494 {"CH7_ASI_EN", "Switch", "CH7_OUT"}, 495 {"CH8_ASI_EN", "Switch", "CH8_OUT"}, 496 497 {"Decimation Filter", "Linear Phase", "DRE_ENABLE"}, 498 {"Decimation Filter", "Low Latency", "DRE_ENABLE"}, 499 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"}, 500 501 {"DRE_ENABLE", "Switch", "CH1_DRE_EN"}, 502 {"DRE_ENABLE", "Switch", "CH2_DRE_EN"}, 503 {"DRE_ENABLE", "Switch", "CH3_DRE_EN"}, 504 {"DRE_ENABLE", "Switch", "CH4_DRE_EN"}, 505 506 {"CH1_DRE_EN", "Switch", "CH1_ADC"}, 507 {"CH2_DRE_EN", "Switch", "CH2_ADC"}, 508 {"CH3_DRE_EN", "Switch", "CH3_ADC"}, 509 {"CH4_DRE_EN", "Switch", "CH4_ADC"}, 510 511 /* Mic input */ 512 {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"}, 513 {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"}, 514 {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"}, 515 {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"}, 516 517 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"}, 518 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"}, 519 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"}, 520 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"}, 521 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"}, 522 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"}, 523 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"}, 524 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"}, 525 526 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"}, 527 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"}, 528 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"}, 529 530 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"}, 531 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"}, 532 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"}, 533 534 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"}, 535 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"}, 536 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"}, 537 538 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"}, 539 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"}, 540 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"}, 541 542 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"}, 543 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"}, 544 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"}, 545 546 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"}, 547 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"}, 548 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"}, 549 550 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"}, 551 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"}, 552 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"}, 553 554 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"}, 555 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"}, 556 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"}, 557 558 {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"}, 559 {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"}, 560 {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"}, 561 {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"}, 562 563 {"MIC1P Input Mux", NULL, "CH1_DIG"}, 564 {"MIC1M Input Mux", NULL, "CH2_DIG"}, 565 {"MIC2P Input Mux", NULL, "CH3_DIG"}, 566 {"MIC2M Input Mux", NULL, "CH4_DIG"}, 567 {"MIC3P Input Mux", NULL, "CH5_DIG"}, 568 {"MIC3M Input Mux", NULL, "CH6_DIG"}, 569 {"MIC4P Input Mux", NULL, "CH7_DIG"}, 570 {"MIC4M Input Mux", NULL, "CH8_DIG"}, 571 572 {"MIC1 Analog Mux", "Line In", "MIC1P"}, 573 {"MIC2 Analog Mux", "Line In", "MIC2P"}, 574 {"MIC3 Analog Mux", "Line In", "MIC3P"}, 575 {"MIC4 Analog Mux", "Line In", "MIC4P"}, 576 577 {"MIC1P Input Mux", "Analog", "MIC1P"}, 578 {"MIC1M Input Mux", "Analog", "MIC1M"}, 579 {"MIC2P Input Mux", "Analog", "MIC2P"}, 580 {"MIC2M Input Mux", "Analog", "MIC2M"}, 581 {"MIC3P Input Mux", "Analog", "MIC3P"}, 582 {"MIC3M Input Mux", "Analog", "MIC3M"}, 583 {"MIC4P Input Mux", "Analog", "MIC4P"}, 584 {"MIC4M Input Mux", "Analog", "MIC4M"}, 585 586 {"MIC1P Input Mux", "Digital", "MIC1P"}, 587 {"MIC1M Input Mux", "Digital", "MIC1M"}, 588 {"MIC2P Input Mux", "Digital", "MIC2P"}, 589 {"MIC2M Input Mux", "Digital", "MIC2M"}, 590 {"MIC3P Input Mux", "Digital", "MIC3P"}, 591 {"MIC3M Input Mux", "Digital", "MIC3M"}, 592 {"MIC4P Input Mux", "Digital", "MIC4P"}, 593 {"MIC4M Input Mux", "Digital", "MIC4M"}, 594}; 595 596static const struct snd_kcontrol_new adcx140_snd_controls[] = { 597 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0, 598 adc_tlv), 599 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0, 600 adc_tlv), 601 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0, 602 adc_tlv), 603 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0, 604 adc_tlv), 605 606 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0, 607 dre_thresh_tlv), 608 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0, 609 dre_gain_tlv), 610 611 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0, 612 agc_thresh_tlv), 613 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0, 614 agc_gain_tlv), 615 616 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2, 617 0, 0xff, 0, dig_vol_tlv), 618 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2, 619 0, 0xff, 0, dig_vol_tlv), 620 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2, 621 0, 0xff, 0, dig_vol_tlv), 622 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2, 623 0, 0xff, 0, dig_vol_tlv), 624 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2, 625 0, 0xff, 0, dig_vol_tlv), 626 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2, 627 0, 0xff, 0, dig_vol_tlv), 628 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2, 629 0, 0xff, 0, dig_vol_tlv), 630 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2, 631 0, 0xff, 0, dig_vol_tlv), 632}; 633 634static int adcx140_reset(struct adcx140_priv *adcx140) 635{ 636 int ret = 0; 637 638 if (adcx140->gpio_reset) { 639 gpiod_direction_output(adcx140->gpio_reset, 0); 640 /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */ 641 usleep_range(30000, 100000); 642 gpiod_direction_output(adcx140->gpio_reset, 1); 643 } else { 644 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET, 645 ADCX140_RESET); 646 } 647 648 /* 8.4.2: wait >= 10 ms after entering sleep mode. */ 649 usleep_range(10000, 100000); 650 651 return ret; 652} 653 654static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state) 655{ 656 int pwr_ctrl = 0; 657 658 if (power_state) 659 pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ; 660 661 if (adcx140->micbias_vg && power_state) 662 pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ; 663 664 regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG, 665 ADCX140_PWR_CTRL_MSK, pwr_ctrl); 666} 667 668static int adcx140_hw_params(struct snd_pcm_substream *substream, 669 struct snd_pcm_hw_params *params, 670 struct snd_soc_dai *dai) 671{ 672 struct snd_soc_component *component = dai->component; 673 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 674 u8 data = 0; 675 676 switch (params_width(params)) { 677 case 16: 678 data = ADCX140_16_BIT_WORD; 679 break; 680 case 20: 681 data = ADCX140_20_BIT_WORD; 682 break; 683 case 24: 684 data = ADCX140_24_BIT_WORD; 685 break; 686 case 32: 687 data = ADCX140_32_BIT_WORD; 688 break; 689 default: 690 dev_err(component->dev, "%s: Unsupported width %d\n", 691 __func__, params_width(params)); 692 return -EINVAL; 693 } 694 695 adcx140_pwr_ctrl(adcx140, false); 696 697 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, 698 ADCX140_WORD_LEN_MSK, data); 699 700 adcx140_pwr_ctrl(adcx140, true); 701 702 return 0; 703} 704 705static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai, 706 unsigned int fmt) 707{ 708 struct snd_soc_component *component = codec_dai->component; 709 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 710 u8 iface_reg1 = 0; 711 u8 iface_reg2 = 0; 712 int offset = 0; 713 bool inverted_bclk = false; 714 715 /* set master/slave audio interface */ 716 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 717 case SND_SOC_DAIFMT_CBM_CFM: 718 iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER; 719 break; 720 case SND_SOC_DAIFMT_CBS_CFS: 721 break; 722 case SND_SOC_DAIFMT_CBS_CFM: 723 case SND_SOC_DAIFMT_CBM_CFS: 724 default: 725 dev_err(component->dev, "Invalid DAI master/slave interface\n"); 726 return -EINVAL; 727 } 728 729 /* interface format */ 730 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 731 case SND_SOC_DAIFMT_I2S: 732 iface_reg1 |= ADCX140_I2S_MODE_BIT; 733 break; 734 case SND_SOC_DAIFMT_LEFT_J: 735 iface_reg1 |= ADCX140_LEFT_JUST_BIT; 736 break; 737 case SND_SOC_DAIFMT_DSP_A: 738 offset = 1; 739 inverted_bclk = true; 740 break; 741 case SND_SOC_DAIFMT_DSP_B: 742 inverted_bclk = true; 743 break; 744 default: 745 dev_err(component->dev, "Invalid DAI interface format\n"); 746 return -EINVAL; 747 } 748 749 /* signal polarity */ 750 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 751 case SND_SOC_DAIFMT_IB_NF: 752 case SND_SOC_DAIFMT_IB_IF: 753 inverted_bclk = !inverted_bclk; 754 break; 755 case SND_SOC_DAIFMT_NB_IF: 756 iface_reg1 |= ADCX140_FSYNCINV_BIT; 757 break; 758 case SND_SOC_DAIFMT_NB_NF: 759 break; 760 default: 761 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 762 return -EINVAL; 763 } 764 765 if (inverted_bclk) 766 iface_reg1 |= ADCX140_BCLKINV_BIT; 767 768 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 769 770 adcx140_pwr_ctrl(adcx140, false); 771 772 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, 773 ADCX140_FSYNCINV_BIT | 774 ADCX140_BCLKINV_BIT | 775 ADCX140_ASI_FORMAT_MSK, 776 iface_reg1); 777 snd_soc_component_update_bits(component, ADCX140_MST_CFG0, 778 ADCX140_BCLK_FSYNC_MASTER, iface_reg2); 779 780 /* Configure data offset */ 781 snd_soc_component_update_bits(component, ADCX140_ASI_CFG1, 782 ADCX140_TX_OFFSET_MASK, offset); 783 784 adcx140_pwr_ctrl(adcx140, true); 785 786 return 0; 787} 788 789static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, 790 unsigned int tx_mask, unsigned int rx_mask, 791 int slots, int slot_width) 792{ 793 struct snd_soc_component *component = codec_dai->component; 794 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 795 unsigned int lsb; 796 797 /* TDM based on DSP mode requires slots to be adjacent */ 798 lsb = __ffs(tx_mask); 799 if ((lsb + 1) != __fls(tx_mask)) { 800 dev_err(component->dev, "Invalid mask, slots must be adjacent\n"); 801 return -EINVAL; 802 } 803 804 switch (slot_width) { 805 case 16: 806 case 20: 807 case 24: 808 case 32: 809 break; 810 default: 811 dev_err(component->dev, "Unsupported slot width %d\n", slot_width); 812 return -EINVAL; 813 } 814 815 adcx140->tdm_delay = lsb; 816 adcx140->slot_width = slot_width; 817 818 return 0; 819} 820 821static const struct snd_soc_dai_ops adcx140_dai_ops = { 822 .hw_params = adcx140_hw_params, 823 .set_fmt = adcx140_set_dai_fmt, 824 .set_tdm_slot = adcx140_set_dai_tdm_slot, 825}; 826 827static int adcx140_configure_gpo(struct adcx140_priv *adcx140) 828{ 829 u32 gpo_outputs[ADCX140_NUM_GPOS]; 830 u32 gpo_output_val = 0; 831 int ret; 832 int i; 833 834 for (i = 0; i < ADCX140_NUM_GPOS; i++) { 835 ret = device_property_read_u32_array(adcx140->dev, 836 gpo_config_names[i], 837 gpo_outputs, 838 ADCX140_NUM_GPO_CFGS); 839 if (ret) 840 continue; 841 842 if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) { 843 dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1); 844 return -EINVAL; 845 } 846 847 if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) { 848 dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1); 849 return -EINVAL; 850 } 851 852 gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT | 853 gpo_outputs[1]; 854 ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i, 855 gpo_output_val); 856 if (ret) 857 return ret; 858 } 859 860 return 0; 861 862} 863 864static int adcx140_configure_gpio(struct adcx140_priv *adcx140) 865{ 866 int gpio_count = 0; 867 u32 gpio_outputs[ADCX140_NUM_GPIO_CFGS]; 868 u32 gpio_output_val = 0; 869 int ret; 870 871 gpio_count = device_property_count_u32(adcx140->dev, 872 "ti,gpio-config"); 873 if (gpio_count <= 0) 874 return 0; 875 876 if (gpio_count != ADCX140_NUM_GPIO_CFGS) 877 return -EINVAL; 878 879 ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config", 880 gpio_outputs, gpio_count); 881 if (ret) 882 return ret; 883 884 if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) { 885 dev_err(adcx140->dev, "GPIO config out of range\n"); 886 return -EINVAL; 887 } 888 889 if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) { 890 dev_err(adcx140->dev, "GPIO drive out of range\n"); 891 return -EINVAL; 892 } 893 894 gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT 895 | gpio_outputs[1]; 896 897 return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val); 898} 899 900static int adcx140_codec_probe(struct snd_soc_component *component) 901{ 902 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 903 int sleep_cfg_val = ADCX140_WAKE_DEV; 904 u32 bias_source; 905 u32 vref_source; 906 u8 bias_cfg; 907 int pdm_count; 908 u32 pdm_edges[ADCX140_NUM_PDM_EDGES]; 909 u32 pdm_edge_val = 0; 910 int gpi_count; 911 u32 gpi_inputs[ADCX140_NUM_GPI_PINS]; 912 u32 gpi_input_val = 0; 913 int i; 914 int ret; 915 bool tx_high_z; 916 917 ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source", 918 &bias_source); 919 if (ret || bias_source > ADCX140_MIC_BIAS_VAL_AVDD) { 920 bias_source = ADCX140_MIC_BIAS_VAL_VREF; 921 adcx140->micbias_vg = false; 922 } else { 923 adcx140->micbias_vg = true; 924 } 925 926 ret = device_property_read_u32(adcx140->dev, "ti,vref-source", 927 &vref_source); 928 if (ret) 929 vref_source = ADCX140_MIC_BIAS_VREF_275V; 930 931 if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) { 932 dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); 933 return -EINVAL; 934 } 935 936 bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source; 937 938 ret = adcx140_reset(adcx140); 939 if (ret) 940 goto out; 941 942 if (adcx140->supply_areg == NULL) 943 sleep_cfg_val |= ADCX140_AREG_INTERNAL; 944 945 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val); 946 if (ret) { 947 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret); 948 goto out; 949 } 950 951 /* 8.4.3: Wait >= 1ms after entering active mode. */ 952 usleep_range(1000, 100000); 953 954 pdm_count = device_property_count_u32(adcx140->dev, 955 "ti,pdm-edge-select"); 956 if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) { 957 ret = device_property_read_u32_array(adcx140->dev, 958 "ti,pdm-edge-select", 959 pdm_edges, pdm_count); 960 if (ret) 961 return ret; 962 963 for (i = 0; i < pdm_count; i++) 964 pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i); 965 966 ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG, 967 pdm_edge_val); 968 if (ret) 969 return ret; 970 } 971 972 gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config"); 973 if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) { 974 ret = device_property_read_u32_array(adcx140->dev, 975 "ti,gpi-config", 976 gpi_inputs, gpi_count); 977 if (ret) 978 return ret; 979 980 gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT | 981 gpi_inputs[ADCX140_GPI2_INDEX]; 982 983 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0, 984 gpi_input_val); 985 if (ret) 986 return ret; 987 988 gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT | 989 gpi_inputs[ADCX140_GPI4_INDEX]; 990 991 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1, 992 gpi_input_val); 993 if (ret) 994 return ret; 995 } 996 997 ret = adcx140_configure_gpio(adcx140); 998 if (ret) 999 return ret; 1000 1001 ret = adcx140_configure_gpo(adcx140); 1002 if (ret) 1003 goto out; 1004 1005 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG, 1006 ADCX140_MIC_BIAS_VAL_MSK | 1007 ADCX140_MIC_BIAS_VREF_MSK, bias_cfg); 1008 if (ret) 1009 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret); 1010 1011 tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive"); 1012 if (tx_high_z) { 1013 ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0, 1014 ADCX140_TX_FILL, ADCX140_TX_FILL); 1015 if (ret) { 1016 dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret); 1017 goto out; 1018 } 1019 } 1020 1021 adcx140_pwr_ctrl(adcx140, true); 1022out: 1023 return ret; 1024} 1025 1026static int adcx140_set_bias_level(struct snd_soc_component *component, 1027 enum snd_soc_bias_level level) 1028{ 1029 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 1030 1031 switch (level) { 1032 case SND_SOC_BIAS_ON: 1033 case SND_SOC_BIAS_PREPARE: 1034 case SND_SOC_BIAS_STANDBY: 1035 adcx140_pwr_ctrl(adcx140, true); 1036 break; 1037 case SND_SOC_BIAS_OFF: 1038 adcx140_pwr_ctrl(adcx140, false); 1039 break; 1040 } 1041 1042 return 0; 1043} 1044 1045static const struct snd_soc_component_driver soc_codec_driver_adcx140 = { 1046 .probe = adcx140_codec_probe, 1047 .set_bias_level = adcx140_set_bias_level, 1048 .controls = adcx140_snd_controls, 1049 .num_controls = ARRAY_SIZE(adcx140_snd_controls), 1050 .dapm_widgets = adcx140_dapm_widgets, 1051 .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets), 1052 .dapm_routes = adcx140_audio_map, 1053 .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map), 1054 .suspend_bias_off = 1, 1055 .idle_bias_on = 0, 1056 .use_pmdown_time = 1, 1057 .endianness = 1, 1058 .non_legacy_dai_naming = 1, 1059}; 1060 1061static struct snd_soc_dai_driver adcx140_dai_driver[] = { 1062 { 1063 .name = "tlv320adcx140-codec", 1064 .capture = { 1065 .stream_name = "Capture", 1066 .channels_min = 2, 1067 .channels_max = ADCX140_MAX_CHANNELS, 1068 .rates = ADCX140_RATES, 1069 .formats = ADCX140_FORMATS, 1070 }, 1071 .ops = &adcx140_dai_ops, 1072 .symmetric_rates = 1, 1073 } 1074}; 1075 1076static const struct of_device_id tlv320adcx140_of_match[] = { 1077 { .compatible = "ti,tlv320adc3140" }, 1078 { .compatible = "ti,tlv320adc5140" }, 1079 { .compatible = "ti,tlv320adc6140" }, 1080 {}, 1081}; 1082MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match); 1083 1084static int adcx140_i2c_probe(struct i2c_client *i2c, 1085 const struct i2c_device_id *id) 1086{ 1087 struct adcx140_priv *adcx140; 1088 int ret; 1089 1090 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL); 1091 if (!adcx140) 1092 return -ENOMEM; 1093 1094 adcx140->dev = &i2c->dev; 1095 1096 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev, 1097 "reset", GPIOD_OUT_LOW); 1098 if (IS_ERR(adcx140->gpio_reset)) 1099 dev_info(&i2c->dev, "Reset GPIO not defined\n"); 1100 1101 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev, 1102 "areg"); 1103 if (IS_ERR(adcx140->supply_areg)) { 1104 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER) 1105 return -EPROBE_DEFER; 1106 1107 adcx140->supply_areg = NULL; 1108 } else { 1109 ret = regulator_enable(adcx140->supply_areg); 1110 if (ret) { 1111 dev_err(adcx140->dev, "Failed to enable areg\n"); 1112 return ret; 1113 } 1114 } 1115 1116 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap); 1117 if (IS_ERR(adcx140->regmap)) { 1118 ret = PTR_ERR(adcx140->regmap); 1119 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1120 ret); 1121 return ret; 1122 } 1123 1124 i2c_set_clientdata(i2c, adcx140); 1125 1126 return devm_snd_soc_register_component(&i2c->dev, 1127 &soc_codec_driver_adcx140, 1128 adcx140_dai_driver, 1); 1129} 1130 1131static const struct i2c_device_id adcx140_i2c_id[] = { 1132 { "tlv320adc3140", 0 }, 1133 { "tlv320adc5140", 1 }, 1134 { "tlv320adc6140", 2 }, 1135 {} 1136}; 1137MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id); 1138 1139static struct i2c_driver adcx140_i2c_driver = { 1140 .driver = { 1141 .name = "tlv320adcx140-codec", 1142 .of_match_table = of_match_ptr(tlv320adcx140_of_match), 1143 }, 1144 .probe = adcx140_i2c_probe, 1145 .id_table = adcx140_i2c_id, 1146}; 1147module_i2c_driver(adcx140_i2c_driver); 1148 1149MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 1150MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver"); 1151MODULE_LICENSE("GPL v2"); 1152