1// SPDX-License-Identifier: GPL-2.0-only 2// 3// rt5682.c -- RT5682 ALSA SoC audio component driver 4// 5// Copyright 2018 Realtek Semiconductor Corp. 6// Author: Bard Liao <bardliao@realtek.com> 7// 8 9#include <linux/module.h> 10#include <linux/moduleparam.h> 11#include <linux/init.h> 12#include <linux/delay.h> 13#include <linux/pm.h> 14#include <linux/pm_runtime.h> 15#include <linux/platform_device.h> 16#include <linux/spi/spi.h> 17#include <linux/acpi.h> 18#include <linux/gpio.h> 19#include <linux/of_gpio.h> 20#include <linux/mutex.h> 21#include <sound/core.h> 22#include <sound/pcm.h> 23#include <sound/pcm_params.h> 24#include <sound/jack.h> 25#include <sound/soc.h> 26#include <sound/soc-dapm.h> 27#include <sound/initval.h> 28#include <sound/tlv.h> 29#include <sound/rt5682.h> 30 31#include "rl6231.h" 32#include "rt5682.h" 33 34const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 35 "AVDD", 36 "MICVDD", 37 "VBAT", 38}; 39EXPORT_SYMBOL_GPL(rt5682_supply_names); 40 41static const struct reg_sequence patch_list[] = { 42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 44 {RT5682_I2C_CTRL, 0x000f}, 45 {RT5682_PLL2_INTERNAL, 0x8266}, 46 {RT5682_SAR_IL_CMD_3, 0x8365}, 47 {RT5682_SAR_IL_CMD_6, 0x0180}, 48}; 49 50void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev) 51{ 52 int ret; 53 54 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 55 ARRAY_SIZE(patch_list)); 56 if (ret) 57 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 58} 59EXPORT_SYMBOL_GPL(rt5682_apply_patch_list); 60 61const struct reg_default rt5682_reg[RT5682_REG_NUM] = { 62 {0x0002, 0x8080}, 63 {0x0003, 0x8000}, 64 {0x0005, 0x0000}, 65 {0x0006, 0x0000}, 66 {0x0008, 0x800f}, 67 {0x000b, 0x0000}, 68 {0x0010, 0x4040}, 69 {0x0011, 0x0000}, 70 {0x0012, 0x1404}, 71 {0x0013, 0x1000}, 72 {0x0014, 0xa00a}, 73 {0x0015, 0x0404}, 74 {0x0016, 0x0404}, 75 {0x0019, 0xafaf}, 76 {0x001c, 0x2f2f}, 77 {0x001f, 0x0000}, 78 {0x0022, 0x5757}, 79 {0x0023, 0x0039}, 80 {0x0024, 0x000b}, 81 {0x0026, 0xc0c4}, 82 {0x0029, 0x8080}, 83 {0x002a, 0xa0a0}, 84 {0x002b, 0x0300}, 85 {0x0030, 0x0000}, 86 {0x003c, 0x0080}, 87 {0x0044, 0x0c0c}, 88 {0x0049, 0x0000}, 89 {0x0061, 0x0000}, 90 {0x0062, 0x0000}, 91 {0x0063, 0x003f}, 92 {0x0064, 0x0000}, 93 {0x0065, 0x0000}, 94 {0x0066, 0x0030}, 95 {0x0067, 0x0000}, 96 {0x006b, 0x0000}, 97 {0x006c, 0x0000}, 98 {0x006d, 0x2200}, 99 {0x006e, 0x0a10}, 100 {0x0070, 0x8000}, 101 {0x0071, 0x8000}, 102 {0x0073, 0x0000}, 103 {0x0074, 0x0000}, 104 {0x0075, 0x0002}, 105 {0x0076, 0x0001}, 106 {0x0079, 0x0000}, 107 {0x007a, 0x0000}, 108 {0x007b, 0x0000}, 109 {0x007c, 0x0100}, 110 {0x007e, 0x0000}, 111 {0x0080, 0x0000}, 112 {0x0081, 0x0000}, 113 {0x0082, 0x0000}, 114 {0x0083, 0x0000}, 115 {0x0084, 0x0000}, 116 {0x0085, 0x0000}, 117 {0x0086, 0x0005}, 118 {0x0087, 0x0000}, 119 {0x0088, 0x0000}, 120 {0x008c, 0x0003}, 121 {0x008d, 0x0000}, 122 {0x008e, 0x0060}, 123 {0x008f, 0x1000}, 124 {0x0091, 0x0c26}, 125 {0x0092, 0x0073}, 126 {0x0093, 0x0000}, 127 {0x0094, 0x0080}, 128 {0x0098, 0x0000}, 129 {0x009a, 0x0000}, 130 {0x009b, 0x0000}, 131 {0x009c, 0x0000}, 132 {0x009d, 0x0000}, 133 {0x009e, 0x100c}, 134 {0x009f, 0x0000}, 135 {0x00a0, 0x0000}, 136 {0x00a3, 0x0002}, 137 {0x00a4, 0x0001}, 138 {0x00ae, 0x2040}, 139 {0x00af, 0x0000}, 140 {0x00b6, 0x0000}, 141 {0x00b7, 0x0000}, 142 {0x00b8, 0x0000}, 143 {0x00b9, 0x0002}, 144 {0x00be, 0x0000}, 145 {0x00c0, 0x0160}, 146 {0x00c1, 0x82a0}, 147 {0x00c2, 0x0000}, 148 {0x00d0, 0x0000}, 149 {0x00d1, 0x2244}, 150 {0x00d2, 0x3300}, 151 {0x00d3, 0x2200}, 152 {0x00d4, 0x0000}, 153 {0x00d9, 0x0009}, 154 {0x00da, 0x0000}, 155 {0x00db, 0x0000}, 156 {0x00dc, 0x00c0}, 157 {0x00dd, 0x2220}, 158 {0x00de, 0x3131}, 159 {0x00df, 0x3131}, 160 {0x00e0, 0x3131}, 161 {0x00e2, 0x0000}, 162 {0x00e3, 0x4000}, 163 {0x00e4, 0x0aa0}, 164 {0x00e5, 0x3131}, 165 {0x00e6, 0x3131}, 166 {0x00e7, 0x3131}, 167 {0x00e8, 0x3131}, 168 {0x00ea, 0xb320}, 169 {0x00eb, 0x0000}, 170 {0x00f0, 0x0000}, 171 {0x00f1, 0x00d0}, 172 {0x00f2, 0x00d0}, 173 {0x00f6, 0x0000}, 174 {0x00fa, 0x0000}, 175 {0x00fb, 0x0000}, 176 {0x00fc, 0x0000}, 177 {0x00fd, 0x0000}, 178 {0x00fe, 0x10ec}, 179 {0x00ff, 0x6530}, 180 {0x0100, 0xa0a0}, 181 {0x010b, 0x0000}, 182 {0x010c, 0xae00}, 183 {0x010d, 0xaaa0}, 184 {0x010e, 0x8aa2}, 185 {0x010f, 0x02a2}, 186 {0x0110, 0xc000}, 187 {0x0111, 0x04a2}, 188 {0x0112, 0x2800}, 189 {0x0113, 0x0000}, 190 {0x0117, 0x0100}, 191 {0x0125, 0x0410}, 192 {0x0132, 0x6026}, 193 {0x0136, 0x5555}, 194 {0x0138, 0x3700}, 195 {0x013a, 0x2000}, 196 {0x013b, 0x2000}, 197 {0x013c, 0x2005}, 198 {0x013f, 0x0000}, 199 {0x0142, 0x0000}, 200 {0x0145, 0x0002}, 201 {0x0146, 0x0000}, 202 {0x0147, 0x0000}, 203 {0x0148, 0x0000}, 204 {0x0149, 0x0000}, 205 {0x0150, 0x79a1}, 206 {0x0156, 0xaaaa}, 207 {0x0160, 0x4ec0}, 208 {0x0161, 0x0080}, 209 {0x0162, 0x0200}, 210 {0x0163, 0x0800}, 211 {0x0164, 0x0000}, 212 {0x0165, 0x0000}, 213 {0x0166, 0x0000}, 214 {0x0167, 0x000f}, 215 {0x0168, 0x000f}, 216 {0x0169, 0x0021}, 217 {0x0190, 0x413d}, 218 {0x0194, 0x0000}, 219 {0x0195, 0x0000}, 220 {0x0197, 0x0022}, 221 {0x0198, 0x0000}, 222 {0x0199, 0x0000}, 223 {0x01af, 0x0000}, 224 {0x01b0, 0x0400}, 225 {0x01b1, 0x0000}, 226 {0x01b2, 0x0000}, 227 {0x01b3, 0x0000}, 228 {0x01b4, 0x0000}, 229 {0x01b5, 0x0000}, 230 {0x01b6, 0x01c3}, 231 {0x01b7, 0x02a0}, 232 {0x01b8, 0x03e9}, 233 {0x01b9, 0x1389}, 234 {0x01ba, 0xc351}, 235 {0x01bb, 0x0009}, 236 {0x01bc, 0x0018}, 237 {0x01bd, 0x002a}, 238 {0x01be, 0x004c}, 239 {0x01bf, 0x0097}, 240 {0x01c0, 0x433d}, 241 {0x01c2, 0x0000}, 242 {0x01c3, 0x0000}, 243 {0x01c4, 0x0000}, 244 {0x01c5, 0x0000}, 245 {0x01c6, 0x0000}, 246 {0x01c7, 0x0000}, 247 {0x01c8, 0x40af}, 248 {0x01c9, 0x0702}, 249 {0x01ca, 0x0000}, 250 {0x01cb, 0x0000}, 251 {0x01cc, 0x5757}, 252 {0x01cd, 0x5757}, 253 {0x01ce, 0x5757}, 254 {0x01cf, 0x5757}, 255 {0x01d0, 0x5757}, 256 {0x01d1, 0x5757}, 257 {0x01d2, 0x5757}, 258 {0x01d3, 0x5757}, 259 {0x01d4, 0x5757}, 260 {0x01d5, 0x5757}, 261 {0x01d6, 0x0000}, 262 {0x01d7, 0x0008}, 263 {0x01d8, 0x0029}, 264 {0x01d9, 0x3333}, 265 {0x01da, 0x0000}, 266 {0x01db, 0x0004}, 267 {0x01dc, 0x0000}, 268 {0x01de, 0x7c00}, 269 {0x01df, 0x0320}, 270 {0x01e0, 0x06a1}, 271 {0x01e1, 0x0000}, 272 {0x01e2, 0x0000}, 273 {0x01e3, 0x0000}, 274 {0x01e4, 0x0000}, 275 {0x01e6, 0x0001}, 276 {0x01e7, 0x0000}, 277 {0x01e8, 0x0000}, 278 {0x01ea, 0x0000}, 279 {0x01eb, 0x0000}, 280 {0x01ec, 0x0000}, 281 {0x01ed, 0x0000}, 282 {0x01ee, 0x0000}, 283 {0x01ef, 0x0000}, 284 {0x01f0, 0x0000}, 285 {0x01f1, 0x0000}, 286 {0x01f2, 0x0000}, 287 {0x01f3, 0x0000}, 288 {0x01f4, 0x0000}, 289 {0x0210, 0x6297}, 290 {0x0211, 0xa005}, 291 {0x0212, 0x824c}, 292 {0x0213, 0xf7ff}, 293 {0x0214, 0xf24c}, 294 {0x0215, 0x0102}, 295 {0x0216, 0x00a3}, 296 {0x0217, 0x0048}, 297 {0x0218, 0xa2c0}, 298 {0x0219, 0x0400}, 299 {0x021a, 0x00c8}, 300 {0x021b, 0x00c0}, 301 {0x021c, 0x0000}, 302 {0x0250, 0x4500}, 303 {0x0251, 0x40b3}, 304 {0x0252, 0x0000}, 305 {0x0253, 0x0000}, 306 {0x0254, 0x0000}, 307 {0x0255, 0x0000}, 308 {0x0256, 0x0000}, 309 {0x0257, 0x0000}, 310 {0x0258, 0x0000}, 311 {0x0259, 0x0000}, 312 {0x025a, 0x0005}, 313 {0x0270, 0x0000}, 314 {0x02ff, 0x0110}, 315 {0x0300, 0x001f}, 316 {0x0301, 0x032c}, 317 {0x0302, 0x5f21}, 318 {0x0303, 0x4000}, 319 {0x0304, 0x4000}, 320 {0x0305, 0x06d5}, 321 {0x0306, 0x8000}, 322 {0x0307, 0x0700}, 323 {0x0310, 0x4560}, 324 {0x0311, 0xa4a8}, 325 {0x0312, 0x7418}, 326 {0x0313, 0x0000}, 327 {0x0314, 0x0006}, 328 {0x0315, 0xffff}, 329 {0x0316, 0xc400}, 330 {0x0317, 0x0000}, 331 {0x03c0, 0x7e00}, 332 {0x03c1, 0x8000}, 333 {0x03c2, 0x8000}, 334 {0x03c3, 0x8000}, 335 {0x03c4, 0x8000}, 336 {0x03c5, 0x8000}, 337 {0x03c6, 0x8000}, 338 {0x03c7, 0x8000}, 339 {0x03c8, 0x8000}, 340 {0x03c9, 0x8000}, 341 {0x03ca, 0x8000}, 342 {0x03cb, 0x8000}, 343 {0x03cc, 0x8000}, 344 {0x03d0, 0x0000}, 345 {0x03d1, 0x0000}, 346 {0x03d2, 0x0000}, 347 {0x03d3, 0x0000}, 348 {0x03d4, 0x2000}, 349 {0x03d5, 0x2000}, 350 {0x03d6, 0x0000}, 351 {0x03d7, 0x0000}, 352 {0x03d8, 0x2000}, 353 {0x03d9, 0x2000}, 354 {0x03da, 0x2000}, 355 {0x03db, 0x2000}, 356 {0x03dc, 0x0000}, 357 {0x03dd, 0x0000}, 358 {0x03de, 0x0000}, 359 {0x03df, 0x2000}, 360 {0x03e0, 0x0000}, 361 {0x03e1, 0x0000}, 362 {0x03e2, 0x0000}, 363 {0x03e3, 0x0000}, 364 {0x03e4, 0x0000}, 365 {0x03e5, 0x0000}, 366 {0x03e6, 0x0000}, 367 {0x03e7, 0x0000}, 368 {0x03e8, 0x0000}, 369 {0x03e9, 0x0000}, 370 {0x03ea, 0x0000}, 371 {0x03eb, 0x0000}, 372 {0x03ec, 0x0000}, 373 {0x03ed, 0x0000}, 374 {0x03ee, 0x0000}, 375 {0x03ef, 0x0000}, 376 {0x03f0, 0x0800}, 377 {0x03f1, 0x0800}, 378 {0x03f2, 0x0800}, 379 {0x03f3, 0x0800}, 380}; 381EXPORT_SYMBOL_GPL(rt5682_reg); 382 383bool rt5682_volatile_register(struct device *dev, unsigned int reg) 384{ 385 switch (reg) { 386 case RT5682_RESET: 387 case RT5682_CBJ_CTRL_2: 388 case RT5682_INT_ST_1: 389 case RT5682_4BTN_IL_CMD_1: 390 case RT5682_AJD1_CTRL: 391 case RT5682_HP_CALIB_CTRL_1: 392 case RT5682_DEVICE_ID: 393 case RT5682_I2C_MODE: 394 case RT5682_HP_CALIB_CTRL_10: 395 case RT5682_EFUSE_CTRL_2: 396 case RT5682_JD_TOP_VC_VTRL: 397 case RT5682_HP_IMP_SENS_CTRL_19: 398 case RT5682_IL_CMD_1: 399 case RT5682_SAR_IL_CMD_2: 400 case RT5682_SAR_IL_CMD_4: 401 case RT5682_SAR_IL_CMD_10: 402 case RT5682_SAR_IL_CMD_11: 403 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 404 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 405 return true; 406 default: 407 return false; 408 } 409} 410EXPORT_SYMBOL_GPL(rt5682_volatile_register); 411 412bool rt5682_readable_register(struct device *dev, unsigned int reg) 413{ 414 switch (reg) { 415 case RT5682_RESET: 416 case RT5682_VERSION_ID: 417 case RT5682_VENDOR_ID: 418 case RT5682_DEVICE_ID: 419 case RT5682_HP_CTRL_1: 420 case RT5682_HP_CTRL_2: 421 case RT5682_HPL_GAIN: 422 case RT5682_HPR_GAIN: 423 case RT5682_I2C_CTRL: 424 case RT5682_CBJ_BST_CTRL: 425 case RT5682_CBJ_CTRL_1: 426 case RT5682_CBJ_CTRL_2: 427 case RT5682_CBJ_CTRL_3: 428 case RT5682_CBJ_CTRL_4: 429 case RT5682_CBJ_CTRL_5: 430 case RT5682_CBJ_CTRL_6: 431 case RT5682_CBJ_CTRL_7: 432 case RT5682_DAC1_DIG_VOL: 433 case RT5682_STO1_ADC_DIG_VOL: 434 case RT5682_STO1_ADC_BOOST: 435 case RT5682_HP_IMP_GAIN_1: 436 case RT5682_HP_IMP_GAIN_2: 437 case RT5682_SIDETONE_CTRL: 438 case RT5682_STO1_ADC_MIXER: 439 case RT5682_AD_DA_MIXER: 440 case RT5682_STO1_DAC_MIXER: 441 case RT5682_A_DAC1_MUX: 442 case RT5682_DIG_INF2_DATA: 443 case RT5682_REC_MIXER: 444 case RT5682_CAL_REC: 445 case RT5682_ALC_BACK_GAIN: 446 case RT5682_PWR_DIG_1: 447 case RT5682_PWR_DIG_2: 448 case RT5682_PWR_ANLG_1: 449 case RT5682_PWR_ANLG_2: 450 case RT5682_PWR_ANLG_3: 451 case RT5682_PWR_MIXER: 452 case RT5682_PWR_VOL: 453 case RT5682_CLK_DET: 454 case RT5682_RESET_LPF_CTRL: 455 case RT5682_RESET_HPF_CTRL: 456 case RT5682_DMIC_CTRL_1: 457 case RT5682_I2S1_SDP: 458 case RT5682_I2S2_SDP: 459 case RT5682_ADDA_CLK_1: 460 case RT5682_ADDA_CLK_2: 461 case RT5682_I2S1_F_DIV_CTRL_1: 462 case RT5682_I2S1_F_DIV_CTRL_2: 463 case RT5682_TDM_CTRL: 464 case RT5682_TDM_ADDA_CTRL_1: 465 case RT5682_TDM_ADDA_CTRL_2: 466 case RT5682_DATA_SEL_CTRL_1: 467 case RT5682_TDM_TCON_CTRL: 468 case RT5682_GLB_CLK: 469 case RT5682_PLL_CTRL_1: 470 case RT5682_PLL_CTRL_2: 471 case RT5682_PLL_TRACK_1: 472 case RT5682_PLL_TRACK_2: 473 case RT5682_PLL_TRACK_3: 474 case RT5682_PLL_TRACK_4: 475 case RT5682_PLL_TRACK_5: 476 case RT5682_PLL_TRACK_6: 477 case RT5682_PLL_TRACK_11: 478 case RT5682_SDW_REF_CLK: 479 case RT5682_DEPOP_1: 480 case RT5682_DEPOP_2: 481 case RT5682_HP_CHARGE_PUMP_1: 482 case RT5682_HP_CHARGE_PUMP_2: 483 case RT5682_MICBIAS_1: 484 case RT5682_MICBIAS_2: 485 case RT5682_PLL_TRACK_12: 486 case RT5682_PLL_TRACK_14: 487 case RT5682_PLL2_CTRL_1: 488 case RT5682_PLL2_CTRL_2: 489 case RT5682_PLL2_CTRL_3: 490 case RT5682_PLL2_CTRL_4: 491 case RT5682_RC_CLK_CTRL: 492 case RT5682_I2S_M_CLK_CTRL_1: 493 case RT5682_I2S2_F_DIV_CTRL_1: 494 case RT5682_I2S2_F_DIV_CTRL_2: 495 case RT5682_EQ_CTRL_1: 496 case RT5682_EQ_CTRL_2: 497 case RT5682_IRQ_CTRL_1: 498 case RT5682_IRQ_CTRL_2: 499 case RT5682_IRQ_CTRL_3: 500 case RT5682_IRQ_CTRL_4: 501 case RT5682_INT_ST_1: 502 case RT5682_GPIO_CTRL_1: 503 case RT5682_GPIO_CTRL_2: 504 case RT5682_GPIO_CTRL_3: 505 case RT5682_HP_AMP_DET_CTRL_1: 506 case RT5682_HP_AMP_DET_CTRL_2: 507 case RT5682_MID_HP_AMP_DET: 508 case RT5682_LOW_HP_AMP_DET: 509 case RT5682_DELAY_BUF_CTRL: 510 case RT5682_SV_ZCD_1: 511 case RT5682_SV_ZCD_2: 512 case RT5682_IL_CMD_1: 513 case RT5682_IL_CMD_2: 514 case RT5682_IL_CMD_3: 515 case RT5682_IL_CMD_4: 516 case RT5682_IL_CMD_5: 517 case RT5682_IL_CMD_6: 518 case RT5682_4BTN_IL_CMD_1: 519 case RT5682_4BTN_IL_CMD_2: 520 case RT5682_4BTN_IL_CMD_3: 521 case RT5682_4BTN_IL_CMD_4: 522 case RT5682_4BTN_IL_CMD_5: 523 case RT5682_4BTN_IL_CMD_6: 524 case RT5682_4BTN_IL_CMD_7: 525 case RT5682_ADC_STO1_HP_CTRL_1: 526 case RT5682_ADC_STO1_HP_CTRL_2: 527 case RT5682_AJD1_CTRL: 528 case RT5682_JD1_THD: 529 case RT5682_JD2_THD: 530 case RT5682_JD_CTRL_1: 531 case RT5682_DUMMY_1: 532 case RT5682_DUMMY_2: 533 case RT5682_DUMMY_3: 534 case RT5682_DAC_ADC_DIG_VOL1: 535 case RT5682_BIAS_CUR_CTRL_2: 536 case RT5682_BIAS_CUR_CTRL_3: 537 case RT5682_BIAS_CUR_CTRL_4: 538 case RT5682_BIAS_CUR_CTRL_5: 539 case RT5682_BIAS_CUR_CTRL_6: 540 case RT5682_BIAS_CUR_CTRL_7: 541 case RT5682_BIAS_CUR_CTRL_8: 542 case RT5682_BIAS_CUR_CTRL_9: 543 case RT5682_BIAS_CUR_CTRL_10: 544 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 545 case RT5682_CHARGE_PUMP_1: 546 case RT5682_DIG_IN_CTRL_1: 547 case RT5682_PAD_DRIVING_CTRL: 548 case RT5682_SOFT_RAMP_DEPOP: 549 case RT5682_CHOP_DAC: 550 case RT5682_CHOP_ADC: 551 case RT5682_CALIB_ADC_CTRL: 552 case RT5682_VOL_TEST: 553 case RT5682_SPKVDD_DET_STA: 554 case RT5682_TEST_MODE_CTRL_1: 555 case RT5682_TEST_MODE_CTRL_2: 556 case RT5682_TEST_MODE_CTRL_3: 557 case RT5682_TEST_MODE_CTRL_4: 558 case RT5682_TEST_MODE_CTRL_5: 559 case RT5682_PLL1_INTERNAL: 560 case RT5682_PLL2_INTERNAL: 561 case RT5682_STO_NG2_CTRL_1: 562 case RT5682_STO_NG2_CTRL_2: 563 case RT5682_STO_NG2_CTRL_3: 564 case RT5682_STO_NG2_CTRL_4: 565 case RT5682_STO_NG2_CTRL_5: 566 case RT5682_STO_NG2_CTRL_6: 567 case RT5682_STO_NG2_CTRL_7: 568 case RT5682_STO_NG2_CTRL_8: 569 case RT5682_STO_NG2_CTRL_9: 570 case RT5682_STO_NG2_CTRL_10: 571 case RT5682_STO1_DAC_SIL_DET: 572 case RT5682_SIL_PSV_CTRL1: 573 case RT5682_SIL_PSV_CTRL2: 574 case RT5682_SIL_PSV_CTRL3: 575 case RT5682_SIL_PSV_CTRL4: 576 case RT5682_SIL_PSV_CTRL5: 577 case RT5682_HP_IMP_SENS_CTRL_01: 578 case RT5682_HP_IMP_SENS_CTRL_02: 579 case RT5682_HP_IMP_SENS_CTRL_03: 580 case RT5682_HP_IMP_SENS_CTRL_04: 581 case RT5682_HP_IMP_SENS_CTRL_05: 582 case RT5682_HP_IMP_SENS_CTRL_06: 583 case RT5682_HP_IMP_SENS_CTRL_07: 584 case RT5682_HP_IMP_SENS_CTRL_08: 585 case RT5682_HP_IMP_SENS_CTRL_09: 586 case RT5682_HP_IMP_SENS_CTRL_10: 587 case RT5682_HP_IMP_SENS_CTRL_11: 588 case RT5682_HP_IMP_SENS_CTRL_12: 589 case RT5682_HP_IMP_SENS_CTRL_13: 590 case RT5682_HP_IMP_SENS_CTRL_14: 591 case RT5682_HP_IMP_SENS_CTRL_15: 592 case RT5682_HP_IMP_SENS_CTRL_16: 593 case RT5682_HP_IMP_SENS_CTRL_17: 594 case RT5682_HP_IMP_SENS_CTRL_18: 595 case RT5682_HP_IMP_SENS_CTRL_19: 596 case RT5682_HP_IMP_SENS_CTRL_20: 597 case RT5682_HP_IMP_SENS_CTRL_21: 598 case RT5682_HP_IMP_SENS_CTRL_22: 599 case RT5682_HP_IMP_SENS_CTRL_23: 600 case RT5682_HP_IMP_SENS_CTRL_24: 601 case RT5682_HP_IMP_SENS_CTRL_25: 602 case RT5682_HP_IMP_SENS_CTRL_26: 603 case RT5682_HP_IMP_SENS_CTRL_27: 604 case RT5682_HP_IMP_SENS_CTRL_28: 605 case RT5682_HP_IMP_SENS_CTRL_29: 606 case RT5682_HP_IMP_SENS_CTRL_30: 607 case RT5682_HP_IMP_SENS_CTRL_31: 608 case RT5682_HP_IMP_SENS_CTRL_32: 609 case RT5682_HP_IMP_SENS_CTRL_33: 610 case RT5682_HP_IMP_SENS_CTRL_34: 611 case RT5682_HP_IMP_SENS_CTRL_35: 612 case RT5682_HP_IMP_SENS_CTRL_36: 613 case RT5682_HP_IMP_SENS_CTRL_37: 614 case RT5682_HP_IMP_SENS_CTRL_38: 615 case RT5682_HP_IMP_SENS_CTRL_39: 616 case RT5682_HP_IMP_SENS_CTRL_40: 617 case RT5682_HP_IMP_SENS_CTRL_41: 618 case RT5682_HP_IMP_SENS_CTRL_42: 619 case RT5682_HP_IMP_SENS_CTRL_43: 620 case RT5682_HP_LOGIC_CTRL_1: 621 case RT5682_HP_LOGIC_CTRL_2: 622 case RT5682_HP_LOGIC_CTRL_3: 623 case RT5682_HP_CALIB_CTRL_1: 624 case RT5682_HP_CALIB_CTRL_2: 625 case RT5682_HP_CALIB_CTRL_3: 626 case RT5682_HP_CALIB_CTRL_4: 627 case RT5682_HP_CALIB_CTRL_5: 628 case RT5682_HP_CALIB_CTRL_6: 629 case RT5682_HP_CALIB_CTRL_7: 630 case RT5682_HP_CALIB_CTRL_9: 631 case RT5682_HP_CALIB_CTRL_10: 632 case RT5682_HP_CALIB_CTRL_11: 633 case RT5682_HP_CALIB_STA_1: 634 case RT5682_HP_CALIB_STA_2: 635 case RT5682_HP_CALIB_STA_3: 636 case RT5682_HP_CALIB_STA_4: 637 case RT5682_HP_CALIB_STA_5: 638 case RT5682_HP_CALIB_STA_6: 639 case RT5682_HP_CALIB_STA_7: 640 case RT5682_HP_CALIB_STA_8: 641 case RT5682_HP_CALIB_STA_9: 642 case RT5682_HP_CALIB_STA_10: 643 case RT5682_HP_CALIB_STA_11: 644 case RT5682_SAR_IL_CMD_1: 645 case RT5682_SAR_IL_CMD_2: 646 case RT5682_SAR_IL_CMD_3: 647 case RT5682_SAR_IL_CMD_4: 648 case RT5682_SAR_IL_CMD_5: 649 case RT5682_SAR_IL_CMD_6: 650 case RT5682_SAR_IL_CMD_7: 651 case RT5682_SAR_IL_CMD_8: 652 case RT5682_SAR_IL_CMD_9: 653 case RT5682_SAR_IL_CMD_10: 654 case RT5682_SAR_IL_CMD_11: 655 case RT5682_SAR_IL_CMD_12: 656 case RT5682_SAR_IL_CMD_13: 657 case RT5682_EFUSE_CTRL_1: 658 case RT5682_EFUSE_CTRL_2: 659 case RT5682_EFUSE_CTRL_3: 660 case RT5682_EFUSE_CTRL_4: 661 case RT5682_EFUSE_CTRL_5: 662 case RT5682_EFUSE_CTRL_6: 663 case RT5682_EFUSE_CTRL_7: 664 case RT5682_EFUSE_CTRL_8: 665 case RT5682_EFUSE_CTRL_9: 666 case RT5682_EFUSE_CTRL_10: 667 case RT5682_EFUSE_CTRL_11: 668 case RT5682_JD_TOP_VC_VTRL: 669 case RT5682_DRC1_CTRL_0: 670 case RT5682_DRC1_CTRL_1: 671 case RT5682_DRC1_CTRL_2: 672 case RT5682_DRC1_CTRL_3: 673 case RT5682_DRC1_CTRL_4: 674 case RT5682_DRC1_CTRL_5: 675 case RT5682_DRC1_CTRL_6: 676 case RT5682_DRC1_HARD_LMT_CTRL_1: 677 case RT5682_DRC1_HARD_LMT_CTRL_2: 678 case RT5682_DRC1_PRIV_1: 679 case RT5682_DRC1_PRIV_2: 680 case RT5682_DRC1_PRIV_3: 681 case RT5682_DRC1_PRIV_4: 682 case RT5682_DRC1_PRIV_5: 683 case RT5682_DRC1_PRIV_6: 684 case RT5682_DRC1_PRIV_7: 685 case RT5682_DRC1_PRIV_8: 686 case RT5682_EQ_AUTO_RCV_CTRL1: 687 case RT5682_EQ_AUTO_RCV_CTRL2: 688 case RT5682_EQ_AUTO_RCV_CTRL3: 689 case RT5682_EQ_AUTO_RCV_CTRL4: 690 case RT5682_EQ_AUTO_RCV_CTRL5: 691 case RT5682_EQ_AUTO_RCV_CTRL6: 692 case RT5682_EQ_AUTO_RCV_CTRL7: 693 case RT5682_EQ_AUTO_RCV_CTRL8: 694 case RT5682_EQ_AUTO_RCV_CTRL9: 695 case RT5682_EQ_AUTO_RCV_CTRL10: 696 case RT5682_EQ_AUTO_RCV_CTRL11: 697 case RT5682_EQ_AUTO_RCV_CTRL12: 698 case RT5682_EQ_AUTO_RCV_CTRL13: 699 case RT5682_ADC_L_EQ_LPF1_A1: 700 case RT5682_R_EQ_LPF1_A1: 701 case RT5682_L_EQ_LPF1_H0: 702 case RT5682_R_EQ_LPF1_H0: 703 case RT5682_L_EQ_BPF1_A1: 704 case RT5682_R_EQ_BPF1_A1: 705 case RT5682_L_EQ_BPF1_A2: 706 case RT5682_R_EQ_BPF1_A2: 707 case RT5682_L_EQ_BPF1_H0: 708 case RT5682_R_EQ_BPF1_H0: 709 case RT5682_L_EQ_BPF2_A1: 710 case RT5682_R_EQ_BPF2_A1: 711 case RT5682_L_EQ_BPF2_A2: 712 case RT5682_R_EQ_BPF2_A2: 713 case RT5682_L_EQ_BPF2_H0: 714 case RT5682_R_EQ_BPF2_H0: 715 case RT5682_L_EQ_BPF3_A1: 716 case RT5682_R_EQ_BPF3_A1: 717 case RT5682_L_EQ_BPF3_A2: 718 case RT5682_R_EQ_BPF3_A2: 719 case RT5682_L_EQ_BPF3_H0: 720 case RT5682_R_EQ_BPF3_H0: 721 case RT5682_L_EQ_BPF4_A1: 722 case RT5682_R_EQ_BPF4_A1: 723 case RT5682_L_EQ_BPF4_A2: 724 case RT5682_R_EQ_BPF4_A2: 725 case RT5682_L_EQ_BPF4_H0: 726 case RT5682_R_EQ_BPF4_H0: 727 case RT5682_L_EQ_HPF1_A1: 728 case RT5682_R_EQ_HPF1_A1: 729 case RT5682_L_EQ_HPF1_H0: 730 case RT5682_R_EQ_HPF1_H0: 731 case RT5682_L_EQ_PRE_VOL: 732 case RT5682_R_EQ_PRE_VOL: 733 case RT5682_L_EQ_POST_VOL: 734 case RT5682_R_EQ_POST_VOL: 735 case RT5682_I2C_MODE: 736 return true; 737 default: 738 return false; 739 } 740} 741EXPORT_SYMBOL_GPL(rt5682_readable_register); 742 743static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 744static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 745static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 746 747/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 748static const DECLARE_TLV_DB_RANGE(bst_tlv, 749 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 750 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 751 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 752 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 753 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 754 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 755 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 756); 757 758/* Interface data select */ 759static const char * const rt5682_data_select[] = { 760 "L/R", "R/L", "L/L", "R/R" 761}; 762 763static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 764 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 765 766static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 767 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 768 769static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 770 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 771 772static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 773 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 774 775static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 776 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 777 778static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 779 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 780 781static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 782 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 783 784static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 785 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 786 787static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 788 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 789 790static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 791 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 792 793static const char * const rt5682_dac_select[] = { 794 "IF1", "SOUND" 795}; 796 797static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 798 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 799 800static const struct snd_kcontrol_new rt5682_dac_l_mux = 801 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 802 803static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 804 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 805 806static const struct snd_kcontrol_new rt5682_dac_r_mux = 807 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 808 809void rt5682_reset(struct rt5682_priv *rt5682) 810{ 811 regmap_write(rt5682->regmap, RT5682_RESET, 0); 812 if (!rt5682->is_sdw) 813 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 814} 815EXPORT_SYMBOL_GPL(rt5682_reset); 816 817/** 818 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 819 * @component: SoC audio component device. 820 * @filter_mask: mask of filters. 821 * @clk_src: clock source 822 * 823 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 824 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 825 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 826 * ASRC function will track i2s clock and generate a corresponding system clock 827 * for codec. This function provides an API to select the clock source for a 828 * set of filters specified by the mask. And the component driver will turn on 829 * ASRC for these filters if ASRC is selected as their clock source. 830 */ 831int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 832 unsigned int filter_mask, unsigned int clk_src) 833{ 834 switch (clk_src) { 835 case RT5682_CLK_SEL_SYS: 836 case RT5682_CLK_SEL_I2S1_ASRC: 837 case RT5682_CLK_SEL_I2S2_ASRC: 838 break; 839 840 default: 841 return -EINVAL; 842 } 843 844 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 845 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 846 RT5682_FILTER_CLK_SEL_MASK, 847 clk_src << RT5682_FILTER_CLK_SEL_SFT); 848 } 849 850 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 851 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 852 RT5682_FILTER_CLK_SEL_MASK, 853 clk_src << RT5682_FILTER_CLK_SEL_SFT); 854 } 855 856 return 0; 857} 858EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 859 860static int rt5682_button_detect(struct snd_soc_component *component) 861{ 862 int btn_type, val; 863 864 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1); 865 btn_type = val & 0xfff0; 866 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 867 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 868 snd_soc_component_update_bits(component, 869 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 870 871 return btn_type; 872} 873 874static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 875 bool enable) 876{ 877 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 878 879 if (enable) { 880 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 881 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 882 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 883 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 884 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 885 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 886 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 887 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 888 if (rt5682->is_sdw) 889 snd_soc_component_update_bits(component, 890 RT5682_IRQ_CTRL_3, 891 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 892 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 893 else 894 snd_soc_component_update_bits(component, 895 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 896 RT5682_IL_IRQ_EN); 897 } else { 898 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 899 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 900 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 901 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 902 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 903 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 904 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 905 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 906 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 907 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 908 } 909} 910 911/** 912 * rt5682_headset_detect - Detect headset. 913 * @component: SoC audio component device. 914 * @jack_insert: Jack insert or not. 915 * 916 * Detect whether is headset or not when jack inserted. 917 * 918 * Returns detect status. 919 */ 920int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert) 921{ 922 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 923 struct snd_soc_dapm_context *dapm = &component->dapm; 924 unsigned int val, count; 925 926 if (jack_insert) { 927 snd_soc_dapm_mutex_lock(dapm); 928 929 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 930 RT5682_PWR_VREF2 | RT5682_PWR_MB, 931 RT5682_PWR_VREF2 | RT5682_PWR_MB); 932 snd_soc_component_update_bits(component, 933 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 934 usleep_range(15000, 20000); 935 snd_soc_component_update_bits(component, 936 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 937 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 938 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 939 snd_soc_component_update_bits(component, 940 RT5682_HP_CHARGE_PUMP_1, 941 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 942 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 943 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 944 945 count = 0; 946 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2) 947 & RT5682_JACK_TYPE_MASK; 948 while (val == 0 && count < 50) { 949 usleep_range(10000, 15000); 950 val = snd_soc_component_read(component, 951 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 952 count++; 953 } 954 955 switch (val) { 956 case 0x1: 957 case 0x2: 958 rt5682->jack_type = SND_JACK_HEADSET; 959 rt5682_enable_push_button_irq(component, true); 960 break; 961 default: 962 rt5682->jack_type = SND_JACK_HEADPHONE; 963 break; 964 } 965 966 snd_soc_component_update_bits(component, 967 RT5682_HP_CHARGE_PUMP_1, 968 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 969 RT5682_OSW_L_EN | RT5682_OSW_R_EN); 970 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 971 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 972 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU); 973 974 snd_soc_dapm_mutex_unlock(dapm); 975 } else { 976 rt5682_enable_push_button_irq(component, false); 977 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 978 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 979 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") && 980 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 981 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 982 snd_soc_component_update_bits(component, 983 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 984 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") && 985 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 986 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 987 snd_soc_component_update_bits(component, 988 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 989 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 990 RT5682_PWR_CBJ, 0); 991 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 992 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 993 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD); 994 995 rt5682->jack_type = 0; 996 } 997 998 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 999 return rt5682->jack_type; 1000} 1001EXPORT_SYMBOL_GPL(rt5682_headset_detect); 1002 1003static int rt5682_set_jack_detect(struct snd_soc_component *component, 1004 struct snd_soc_jack *hs_jack, void *data) 1005{ 1006 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1007 1008 rt5682->hs_jack = hs_jack; 1009 1010 if (!hs_jack) { 1011 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1012 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1013 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1014 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1015 cancel_delayed_work_sync(&rt5682->jack_detect_work); 1016 1017 return 0; 1018 } 1019 1020 if (!rt5682->is_sdw) { 1021 switch (rt5682->pdata.jd_src) { 1022 case RT5682_JD1: 1023 snd_soc_component_update_bits(component, 1024 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1025 RT5682_EXT_JD_SRC_MANUAL); 1026 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1027 0xd042); 1028 snd_soc_component_update_bits(component, 1029 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1030 RT5682_CBJ_IN_BUF_EN); 1031 snd_soc_component_update_bits(component, 1032 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1033 RT5682_SAR_POW_EN); 1034 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1035 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1036 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1037 RT5682_POW_IRQ | RT5682_POW_JDH | 1038 RT5682_POW_ANA, RT5682_POW_IRQ | 1039 RT5682_POW_JDH | RT5682_POW_ANA); 1040 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1041 RT5682_PWR_JDH, RT5682_PWR_JDH); 1042 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1043 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1044 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1045 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1046 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1047 rt5682->pdata.btndet_delay)); 1048 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1049 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1050 rt5682->pdata.btndet_delay)); 1051 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1052 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1053 rt5682->pdata.btndet_delay)); 1054 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1055 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1056 rt5682->pdata.btndet_delay)); 1057 mod_delayed_work(system_power_efficient_wq, 1058 &rt5682->jack_detect_work, 1059 msecs_to_jiffies(250)); 1060 break; 1061 1062 case RT5682_JD_NULL: 1063 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1064 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1065 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1066 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1067 break; 1068 1069 default: 1070 dev_warn(component->dev, "Wrong JD source\n"); 1071 break; 1072 } 1073 } 1074 1075 return 0; 1076} 1077 1078void rt5682_jack_detect_handler(struct work_struct *work) 1079{ 1080 struct rt5682_priv *rt5682 = 1081 container_of(work, struct rt5682_priv, jack_detect_work.work); 1082 int val, btn_type; 1083 1084 if (!rt5682->component || !rt5682->component->card || 1085 !rt5682->component->card->instantiated) { 1086 /* card not yet ready, try later */ 1087 mod_delayed_work(system_power_efficient_wq, 1088 &rt5682->jack_detect_work, msecs_to_jiffies(15)); 1089 return; 1090 } 1091 1092 mutex_lock(&rt5682->calibrate_mutex); 1093 1094 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) 1095 & RT5682_JDH_RS_MASK; 1096 if (!val) { 1097 /* jack in */ 1098 if (rt5682->jack_type == 0) { 1099 /* jack was out, report jack type */ 1100 rt5682->jack_type = 1101 rt5682_headset_detect(rt5682->component, 1); 1102 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == 1103 SND_JACK_HEADSET) { 1104 /* jack is already in, report button event */ 1105 rt5682->jack_type = SND_JACK_HEADSET; 1106 btn_type = rt5682_button_detect(rt5682->component); 1107 /** 1108 * rt5682 can report three kinds of button behavior, 1109 * one click, double click and hold. However, 1110 * currently we will report button pressed/released 1111 * event. So all the three button behaviors are 1112 * treated as button pressed. 1113 */ 1114 switch (btn_type) { 1115 case 0x8000: 1116 case 0x4000: 1117 case 0x2000: 1118 rt5682->jack_type |= SND_JACK_BTN_0; 1119 break; 1120 case 0x1000: 1121 case 0x0800: 1122 case 0x0400: 1123 rt5682->jack_type |= SND_JACK_BTN_1; 1124 break; 1125 case 0x0200: 1126 case 0x0100: 1127 case 0x0080: 1128 rt5682->jack_type |= SND_JACK_BTN_2; 1129 break; 1130 case 0x0040: 1131 case 0x0020: 1132 case 0x0010: 1133 rt5682->jack_type |= SND_JACK_BTN_3; 1134 break; 1135 case 0x0000: /* unpressed */ 1136 break; 1137 default: 1138 dev_err(rt5682->component->dev, 1139 "Unexpected button code 0x%04x\n", 1140 btn_type); 1141 break; 1142 } 1143 } 1144 } else { 1145 /* jack out */ 1146 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1147 } 1148 1149 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1150 SND_JACK_HEADSET | 1151 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1152 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1153 1154 if (!rt5682->is_sdw) { 1155 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1156 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1157 schedule_delayed_work(&rt5682->jd_check_work, 0); 1158 else 1159 cancel_delayed_work_sync(&rt5682->jd_check_work); 1160 } 1161 1162 mutex_unlock(&rt5682->calibrate_mutex); 1163} 1164EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler); 1165 1166static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1167 /* DAC Digital Volume */ 1168 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1169 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1170 1171 /* IN Boost Volume */ 1172 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1173 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1174 1175 /* ADC Digital Volume Control */ 1176 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1177 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1178 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1179 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1180 1181 /* ADC Boost Volume Control */ 1182 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1183 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1184 3, 0, adc_bst_tlv), 1185}; 1186 1187static int rt5682_div_sel(struct rt5682_priv *rt5682, 1188 int target, const int div[], int size) 1189{ 1190 int i; 1191 1192 if (rt5682->sysclk < target) { 1193 dev_err(rt5682->component->dev, 1194 "sysclk rate %d is too low\n", rt5682->sysclk); 1195 return 0; 1196 } 1197 1198 for (i = 0; i < size - 1; i++) { 1199 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1200 if (target * div[i] == rt5682->sysclk) 1201 return i; 1202 if (target * div[i + 1] > rt5682->sysclk) { 1203 dev_dbg(rt5682->component->dev, 1204 "can't find div for sysclk %d\n", 1205 rt5682->sysclk); 1206 return i; 1207 } 1208 } 1209 1210 if (target * div[i] < rt5682->sysclk) 1211 dev_err(rt5682->component->dev, 1212 "sysclk rate %d is too high\n", rt5682->sysclk); 1213 1214 return size - 1; 1215} 1216 1217/** 1218 * set_dmic_clk - Set parameter of dmic. 1219 * 1220 * @w: DAPM widget. 1221 * @kcontrol: The kcontrol of this widget. 1222 * @event: Event id. 1223 * 1224 * Choose dmic clock between 1MHz and 3MHz. 1225 * It is better for clock to approximate 3MHz. 1226 */ 1227static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1228 struct snd_kcontrol *kcontrol, int event) 1229{ 1230 struct snd_soc_component *component = 1231 snd_soc_dapm_to_component(w->dapm); 1232 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1233 int idx = -EINVAL, dmic_clk_rate = 3072000; 1234 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1235 1236 if (rt5682->pdata.dmic_clk_rate) 1237 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1238 1239 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1240 1241 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1242 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1243 1244 return 0; 1245} 1246 1247static int set_filter_clk(struct snd_soc_dapm_widget *w, 1248 struct snd_kcontrol *kcontrol, int event) 1249{ 1250 struct snd_soc_component *component = 1251 snd_soc_dapm_to_component(w->dapm); 1252 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1253 int ref, val, reg, idx = -EINVAL; 1254 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1255 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1256 1257 if (rt5682->is_sdw) 1258 return 0; 1259 1260 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) & 1261 RT5682_GP4_PIN_MASK; 1262 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1263 val == RT5682_GP4_PIN_ADCDAT2) 1264 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1265 else 1266 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1267 1268 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1269 1270 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1271 reg = RT5682_PLL_TRACK_3; 1272 else 1273 reg = RT5682_PLL_TRACK_2; 1274 1275 snd_soc_component_update_bits(component, reg, 1276 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1277 1278 /* select over sample rate */ 1279 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1280 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1281 break; 1282 } 1283 1284 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1285 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1286 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1287 1288 return 0; 1289} 1290 1291static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1292 struct snd_soc_dapm_widget *sink) 1293{ 1294 unsigned int val; 1295 struct snd_soc_component *component = 1296 snd_soc_dapm_to_component(w->dapm); 1297 1298 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1299 val &= RT5682_SCLK_SRC_MASK; 1300 if (val == RT5682_SCLK_SRC_PLL1) 1301 return 1; 1302 else 1303 return 0; 1304} 1305 1306static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1307 struct snd_soc_dapm_widget *sink) 1308{ 1309 unsigned int val; 1310 struct snd_soc_component *component = 1311 snd_soc_dapm_to_component(w->dapm); 1312 1313 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1314 val &= RT5682_SCLK_SRC_MASK; 1315 if (val == RT5682_SCLK_SRC_PLL2) 1316 return 1; 1317 else 1318 return 0; 1319} 1320 1321static int is_using_asrc(struct snd_soc_dapm_widget *w, 1322 struct snd_soc_dapm_widget *sink) 1323{ 1324 unsigned int reg, shift, val; 1325 struct snd_soc_component *component = 1326 snd_soc_dapm_to_component(w->dapm); 1327 1328 switch (w->shift) { 1329 case RT5682_ADC_STO1_ASRC_SFT: 1330 reg = RT5682_PLL_TRACK_3; 1331 shift = RT5682_FILTER_CLK_SEL_SFT; 1332 break; 1333 case RT5682_DAC_STO1_ASRC_SFT: 1334 reg = RT5682_PLL_TRACK_2; 1335 shift = RT5682_FILTER_CLK_SEL_SFT; 1336 break; 1337 default: 1338 return 0; 1339 } 1340 1341 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1342 switch (val) { 1343 case RT5682_CLK_SEL_I2S1_ASRC: 1344 case RT5682_CLK_SEL_I2S2_ASRC: 1345 return 1; 1346 default: 1347 return 0; 1348 } 1349} 1350 1351/* Digital Mixer */ 1352static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1353 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1354 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1355 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1356 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1357}; 1358 1359static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1360 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1361 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1362 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1363 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1364}; 1365 1366static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1367 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1368 RT5682_M_ADCMIX_L_SFT, 1, 1), 1369 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1370 RT5682_M_DAC1_L_SFT, 1, 1), 1371}; 1372 1373static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1374 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1375 RT5682_M_ADCMIX_R_SFT, 1, 1), 1376 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1377 RT5682_M_DAC1_R_SFT, 1, 1), 1378}; 1379 1380static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1381 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1382 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1383 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1384 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1385}; 1386 1387static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1388 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1389 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1390 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1391 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1392}; 1393 1394/* Analog Input Mixer */ 1395static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1396 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1397 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1398}; 1399 1400/* STO1 ADC1 Source */ 1401/* MX-26 [13] [5] */ 1402static const char * const rt5682_sto1_adc1_src[] = { 1403 "DAC MIX", "ADC" 1404}; 1405 1406static SOC_ENUM_SINGLE_DECL( 1407 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1408 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1409 1410static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1411 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1412 1413static SOC_ENUM_SINGLE_DECL( 1414 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1415 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1416 1417static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1418 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1419 1420/* STO1 ADC Source */ 1421/* MX-26 [11:10] [3:2] */ 1422static const char * const rt5682_sto1_adc_src[] = { 1423 "ADC1 L", "ADC1 R" 1424}; 1425 1426static SOC_ENUM_SINGLE_DECL( 1427 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1428 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1429 1430static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1431 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1432 1433static SOC_ENUM_SINGLE_DECL( 1434 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1435 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1436 1437static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1438 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1439 1440/* STO1 ADC2 Source */ 1441/* MX-26 [12] [4] */ 1442static const char * const rt5682_sto1_adc2_src[] = { 1443 "DAC MIX", "DMIC" 1444}; 1445 1446static SOC_ENUM_SINGLE_DECL( 1447 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1448 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1449 1450static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1451 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1452 1453static SOC_ENUM_SINGLE_DECL( 1454 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1455 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1456 1457static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1458 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1459 1460/* MX-79 [6:4] I2S1 ADC data location */ 1461static const unsigned int rt5682_if1_adc_slot_values[] = { 1462 0, 1463 2, 1464 4, 1465 6, 1466}; 1467 1468static const char * const rt5682_if1_adc_slot_src[] = { 1469 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1470}; 1471 1472static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1473 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1474 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1475 1476static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1477 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1478 1479/* Analog DAC L1 Source, Analog DAC R1 Source*/ 1480/* MX-2B [4], MX-2B [0]*/ 1481static const char * const rt5682_alg_dac1_src[] = { 1482 "Stereo1 DAC Mixer", "DAC1" 1483}; 1484 1485static SOC_ENUM_SINGLE_DECL( 1486 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1487 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1488 1489static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1490 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1491 1492static SOC_ENUM_SINGLE_DECL( 1493 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1494 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1495 1496static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1497 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1498 1499/* Out Switch */ 1500static const struct snd_kcontrol_new hpol_switch = 1501 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1502 RT5682_L_MUTE_SFT, 1, 1); 1503static const struct snd_kcontrol_new hpor_switch = 1504 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1505 RT5682_R_MUTE_SFT, 1, 1); 1506 1507static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1508 struct snd_kcontrol *kcontrol, int event) 1509{ 1510 struct snd_soc_component *component = 1511 snd_soc_dapm_to_component(w->dapm); 1512 1513 switch (event) { 1514 case SND_SOC_DAPM_PRE_PMU: 1515 snd_soc_component_write(component, 1516 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1517 snd_soc_component_write(component, 1518 RT5682_HP_CTRL_2, 0x6000); 1519 snd_soc_component_update_bits(component, 1520 RT5682_DEPOP_1, 0x60, 0x60); 1521 snd_soc_component_update_bits(component, 1522 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1523 break; 1524 1525 case SND_SOC_DAPM_POST_PMD: 1526 snd_soc_component_update_bits(component, 1527 RT5682_DEPOP_1, 0x60, 0x0); 1528 snd_soc_component_write(component, 1529 RT5682_HP_CTRL_2, 0x0000); 1530 snd_soc_component_update_bits(component, 1531 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1532 break; 1533 } 1534 1535 return 0; 1536} 1537 1538static int set_dmic_power(struct snd_soc_dapm_widget *w, 1539 struct snd_kcontrol *kcontrol, int event) 1540{ 1541 struct snd_soc_component *component = 1542 snd_soc_dapm_to_component(w->dapm); 1543 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1544 unsigned int delay = 50, val; 1545 1546 if (rt5682->pdata.dmic_delay) 1547 delay = rt5682->pdata.dmic_delay; 1548 1549 switch (event) { 1550 case SND_SOC_DAPM_POST_PMU: 1551 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1552 val &= RT5682_SCLK_SRC_MASK; 1553 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2) 1554 snd_soc_component_update_bits(component, 1555 RT5682_PWR_ANLG_1, 1556 RT5682_PWR_VREF2 | RT5682_PWR_MB, 1557 RT5682_PWR_VREF2 | RT5682_PWR_MB); 1558 1559 /*Add delay to avoid pop noise*/ 1560 msleep(delay); 1561 break; 1562 1563 case SND_SOC_DAPM_POST_PMD: 1564 if (!rt5682->jack_type) { 1565 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) 1566 snd_soc_component_update_bits(component, 1567 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 1568 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) 1569 snd_soc_component_update_bits(component, 1570 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 1571 } 1572 break; 1573 } 1574 1575 return 0; 1576} 1577 1578static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1579 struct snd_kcontrol *kcontrol, int event) 1580{ 1581 struct snd_soc_component *component = 1582 snd_soc_dapm_to_component(w->dapm); 1583 1584 switch (event) { 1585 case SND_SOC_DAPM_PRE_PMU: 1586 switch (w->shift) { 1587 case RT5682_PWR_VREF1_BIT: 1588 snd_soc_component_update_bits(component, 1589 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1590 break; 1591 1592 case RT5682_PWR_VREF2_BIT: 1593 snd_soc_component_update_bits(component, 1594 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1595 break; 1596 } 1597 break; 1598 1599 case SND_SOC_DAPM_POST_PMU: 1600 usleep_range(15000, 20000); 1601 switch (w->shift) { 1602 case RT5682_PWR_VREF1_BIT: 1603 snd_soc_component_update_bits(component, 1604 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1605 RT5682_PWR_FV1); 1606 break; 1607 1608 case RT5682_PWR_VREF2_BIT: 1609 snd_soc_component_update_bits(component, 1610 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1611 RT5682_PWR_FV2); 1612 break; 1613 } 1614 break; 1615 } 1616 1617 return 0; 1618} 1619 1620static const unsigned int rt5682_adcdat_pin_values[] = { 1621 1, 1622 3, 1623}; 1624 1625static const char * const rt5682_adcdat_pin_select[] = { 1626 "ADCDAT1", 1627 "ADCDAT2", 1628}; 1629 1630static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1631 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1632 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1633 1634static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1635 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1636 1637static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1638 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1639 0, NULL, 0), 1640 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1641 0, NULL, 0), 1642 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1643 0, NULL, 0), 1644 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1645 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1646 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1647 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1648 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1649 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1650 1651 /* ASRC */ 1652 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1653 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1654 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1655 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1656 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1657 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1658 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1659 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1660 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1661 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1662 1663 /* Input Side */ 1664 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1665 0, NULL, 0), 1666 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1667 0, NULL, 0), 1668 1669 /* Input Lines */ 1670 SND_SOC_DAPM_INPUT("DMIC L1"), 1671 SND_SOC_DAPM_INPUT("DMIC R1"), 1672 1673 SND_SOC_DAPM_INPUT("IN1P"), 1674 1675 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1676 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1677 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1678 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, 1679 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1680 1681 /* Boost */ 1682 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1683 0, 0, NULL, 0), 1684 1685 /* REC Mixer */ 1686 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1687 ARRAY_SIZE(rt5682_rec1_l_mix)), 1688 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1689 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1690 1691 /* ADCs */ 1692 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1693 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1694 1695 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1696 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1697 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1698 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1699 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1700 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1701 1702 /* ADC Mux */ 1703 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1704 &rt5682_sto1_adc1l_mux), 1705 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1706 &rt5682_sto1_adc1r_mux), 1707 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1708 &rt5682_sto1_adc2l_mux), 1709 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1710 &rt5682_sto1_adc2r_mux), 1711 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1712 &rt5682_sto1_adcl_mux), 1713 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1714 &rt5682_sto1_adcr_mux), 1715 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1716 &rt5682_if1_adc_slot_mux), 1717 1718 /* ADC Mixer */ 1719 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1720 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1721 SND_SOC_DAPM_PRE_PMU), 1722 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1723 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1724 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1725 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1726 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1727 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1728 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1729 14, 1, NULL, 0), 1730 1731 /* ADC PGA */ 1732 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1733 1734 /* Digital Interface */ 1735 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1736 0, NULL, 0), 1737 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1738 0, NULL, 0), 1739 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1740 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1741 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1742 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1743 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1744 1745 /* Digital Interface Select */ 1746 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1747 &rt5682_if1_01_adc_swap_mux), 1748 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1749 &rt5682_if1_23_adc_swap_mux), 1750 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1751 &rt5682_if1_45_adc_swap_mux), 1752 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1753 &rt5682_if1_67_adc_swap_mux), 1754 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1755 &rt5682_if2_adc_swap_mux), 1756 1757 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1758 &rt5682_adcdat_pin_ctrl), 1759 1760 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1761 &rt5682_dac_l_mux), 1762 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1763 &rt5682_dac_r_mux), 1764 1765 /* Audio Interface */ 1766 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1767 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1768 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1769 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1770 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1771 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1772 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1773 1774 /* Output Side */ 1775 /* DAC mixer before sound effect */ 1776 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1777 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1778 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1779 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1780 1781 /* DAC channel Mux */ 1782 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1783 &rt5682_alg_dac_l1_mux), 1784 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1785 &rt5682_alg_dac_r1_mux), 1786 1787 /* DAC Mixer */ 1788 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1789 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1790 SND_SOC_DAPM_PRE_PMU), 1791 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1792 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1793 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1794 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1795 1796 /* DACs */ 1797 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1798 RT5682_PWR_DAC_L1_BIT, 0), 1799 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1800 RT5682_PWR_DAC_R1_BIT, 0), 1801 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1802 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1803 1804 /* HPO */ 1805 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1806 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1807 1808 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1809 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1810 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1811 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1812 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1813 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1814 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1815 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1816 1817 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1818 &hpol_switch), 1819 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1820 &hpor_switch), 1821 1822 /* CLK DET */ 1823 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1824 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1825 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1826 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1827 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1828 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1829 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1830 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1831 1832 /* Output Lines */ 1833 SND_SOC_DAPM_OUTPUT("HPOL"), 1834 SND_SOC_DAPM_OUTPUT("HPOR"), 1835}; 1836 1837static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1838 /*PLL*/ 1839 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1840 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1841 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1842 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1843 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1844 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1845 1846 /*ASRC*/ 1847 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1848 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1849 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1850 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1851 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1852 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1853 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1854 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1855 1856 /*Vref*/ 1857 {"MICBIAS1", NULL, "Vref1"}, 1858 {"MICBIAS2", NULL, "Vref1"}, 1859 1860 {"CLKDET SYS", NULL, "CLKDET"}, 1861 1862 {"IN1P", NULL, "LDO2"}, 1863 1864 {"BST1 CBJ", NULL, "IN1P"}, 1865 1866 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1867 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1868 1869 {"ADC1 L", NULL, "RECMIX1L"}, 1870 {"ADC1 L", NULL, "ADC1 L Power"}, 1871 {"ADC1 L", NULL, "ADC1 clock"}, 1872 1873 {"DMIC L1", NULL, "DMIC CLK"}, 1874 {"DMIC L1", NULL, "DMIC1 Power"}, 1875 {"DMIC R1", NULL, "DMIC CLK"}, 1876 {"DMIC R1", NULL, "DMIC1 Power"}, 1877 {"DMIC CLK", NULL, "DMIC ASRC"}, 1878 1879 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1880 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1881 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1882 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1883 1884 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1885 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1886 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1887 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1888 1889 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1890 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1891 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1892 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1893 1894 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1895 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1896 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1897 1898 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1899 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1900 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1901 1902 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1903 1904 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1905 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1906 1907 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1908 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1909 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1910 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1911 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1912 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1913 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1914 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1915 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1916 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1917 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1918 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1919 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1920 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1921 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1922 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1923 1924 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1925 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1926 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1927 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1928 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1929 {"AIF1TX", NULL, "I2S1"}, 1930 {"AIF1TX", NULL, "ADCDAT Mux"}, 1931 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1932 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1933 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1934 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1935 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1936 {"AIF2TX", NULL, "ADCDAT Mux"}, 1937 1938 {"SDWTX", NULL, "PLL2B"}, 1939 {"SDWTX", NULL, "PLL2F"}, 1940 {"SDWTX", NULL, "ADCDAT Mux"}, 1941 1942 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1943 {"IF1 DAC1 L", NULL, "I2S1"}, 1944 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1945 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1946 {"IF1 DAC1 R", NULL, "I2S1"}, 1947 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1948 1949 {"SOUND DAC L", NULL, "SDWRX"}, 1950 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 1951 {"SOUND DAC L", NULL, "PLL2B"}, 1952 {"SOUND DAC L", NULL, "PLL2F"}, 1953 {"SOUND DAC R", NULL, "SDWRX"}, 1954 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 1955 {"SOUND DAC R", NULL, "PLL2B"}, 1956 {"SOUND DAC R", NULL, "PLL2F"}, 1957 1958 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 1959 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 1960 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 1961 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 1962 1963 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1964 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 1965 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1966 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 1967 1968 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1969 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1970 1971 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1972 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1973 1974 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1975 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1976 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1977 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1978 1979 {"DAC L1", NULL, "DAC L1 Source"}, 1980 {"DAC R1", NULL, "DAC R1 Source"}, 1981 1982 {"DAC L1", NULL, "DAC 1 Clock"}, 1983 {"DAC R1", NULL, "DAC 1 Clock"}, 1984 1985 {"HP Amp", NULL, "DAC L1"}, 1986 {"HP Amp", NULL, "DAC R1"}, 1987 {"HP Amp", NULL, "HP Amp L"}, 1988 {"HP Amp", NULL, "HP Amp R"}, 1989 {"HP Amp", NULL, "Capless"}, 1990 {"HP Amp", NULL, "Charge Pump"}, 1991 {"HP Amp", NULL, "CLKDET SYS"}, 1992 {"HP Amp", NULL, "Vref1"}, 1993 {"HPOL Playback", "Switch", "HP Amp"}, 1994 {"HPOR Playback", "Switch", "HP Amp"}, 1995 {"HPOL", NULL, "HPOL Playback"}, 1996 {"HPOR", NULL, "HPOR Playback"}, 1997}; 1998 1999static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2000 unsigned int rx_mask, int slots, int slot_width) 2001{ 2002 struct snd_soc_component *component = dai->component; 2003 unsigned int cl, val = 0; 2004 2005 if (tx_mask || rx_mask) 2006 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2007 RT5682_TDM_EN, RT5682_TDM_EN); 2008 else 2009 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2010 RT5682_TDM_EN, 0); 2011 2012 switch (slots) { 2013 case 4: 2014 val |= RT5682_TDM_TX_CH_4; 2015 val |= RT5682_TDM_RX_CH_4; 2016 break; 2017 case 6: 2018 val |= RT5682_TDM_TX_CH_6; 2019 val |= RT5682_TDM_RX_CH_6; 2020 break; 2021 case 8: 2022 val |= RT5682_TDM_TX_CH_8; 2023 val |= RT5682_TDM_RX_CH_8; 2024 break; 2025 case 2: 2026 break; 2027 default: 2028 return -EINVAL; 2029 } 2030 2031 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 2032 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 2033 2034 switch (slot_width) { 2035 case 8: 2036 if (tx_mask || rx_mask) 2037 return -EINVAL; 2038 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 2039 break; 2040 case 16: 2041 val = RT5682_TDM_CL_16; 2042 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 2043 break; 2044 case 20: 2045 val = RT5682_TDM_CL_20; 2046 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2047 break; 2048 case 24: 2049 val = RT5682_TDM_CL_24; 2050 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2051 break; 2052 case 32: 2053 val = RT5682_TDM_CL_32; 2054 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2055 break; 2056 default: 2057 return -EINVAL; 2058 } 2059 2060 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2061 RT5682_TDM_CL_MASK, val); 2062 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2063 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2064 2065 return 0; 2066} 2067 2068static int rt5682_hw_params(struct snd_pcm_substream *substream, 2069 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2070{ 2071 struct snd_soc_component *component = dai->component; 2072 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2073 unsigned int len_1 = 0, len_2 = 0; 2074 int pre_div, frame_size; 2075 2076 rt5682->lrck[dai->id] = params_rate(params); 2077 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2078 2079 frame_size = snd_soc_params_to_frame_size(params); 2080 if (frame_size < 0) { 2081 dev_err(component->dev, "Unsupported frame size: %d\n", 2082 frame_size); 2083 return -EINVAL; 2084 } 2085 2086 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2087 rt5682->lrck[dai->id], pre_div, dai->id); 2088 2089 switch (params_width(params)) { 2090 case 16: 2091 break; 2092 case 20: 2093 len_1 |= RT5682_I2S1_DL_20; 2094 len_2 |= RT5682_I2S2_DL_20; 2095 break; 2096 case 24: 2097 len_1 |= RT5682_I2S1_DL_24; 2098 len_2 |= RT5682_I2S2_DL_24; 2099 break; 2100 case 32: 2101 len_1 |= RT5682_I2S1_DL_32; 2102 len_2 |= RT5682_I2S2_DL_24; 2103 break; 2104 case 8: 2105 len_1 |= RT5682_I2S2_DL_8; 2106 len_2 |= RT5682_I2S2_DL_8; 2107 break; 2108 default: 2109 return -EINVAL; 2110 } 2111 2112 switch (dai->id) { 2113 case RT5682_AIF1: 2114 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2115 RT5682_I2S1_DL_MASK, len_1); 2116 if (rt5682->master[RT5682_AIF1]) { 2117 snd_soc_component_update_bits(component, 2118 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2119 RT5682_I2S_CLK_SRC_MASK, 2120 pre_div << RT5682_I2S_M_DIV_SFT | 2121 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2122 } 2123 if (params_channels(params) == 1) /* mono mode */ 2124 snd_soc_component_update_bits(component, 2125 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2126 RT5682_I2S1_MONO_EN); 2127 else 2128 snd_soc_component_update_bits(component, 2129 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2130 RT5682_I2S1_MONO_DIS); 2131 break; 2132 case RT5682_AIF2: 2133 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2134 RT5682_I2S2_DL_MASK, len_2); 2135 if (rt5682->master[RT5682_AIF2]) { 2136 snd_soc_component_update_bits(component, 2137 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2138 pre_div << RT5682_I2S2_M_PD_SFT); 2139 } 2140 if (params_channels(params) == 1) /* mono mode */ 2141 snd_soc_component_update_bits(component, 2142 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2143 RT5682_I2S2_MONO_EN); 2144 else 2145 snd_soc_component_update_bits(component, 2146 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2147 RT5682_I2S2_MONO_DIS); 2148 break; 2149 default: 2150 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2151 return -EINVAL; 2152 } 2153 2154 return 0; 2155} 2156 2157static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2158{ 2159 struct snd_soc_component *component = dai->component; 2160 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2161 unsigned int reg_val = 0, tdm_ctrl = 0; 2162 2163 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2164 case SND_SOC_DAIFMT_CBM_CFM: 2165 rt5682->master[dai->id] = 1; 2166 break; 2167 case SND_SOC_DAIFMT_CBS_CFS: 2168 rt5682->master[dai->id] = 0; 2169 break; 2170 default: 2171 return -EINVAL; 2172 } 2173 2174 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2175 case SND_SOC_DAIFMT_NB_NF: 2176 break; 2177 case SND_SOC_DAIFMT_IB_NF: 2178 reg_val |= RT5682_I2S_BP_INV; 2179 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2180 break; 2181 case SND_SOC_DAIFMT_NB_IF: 2182 if (dai->id == RT5682_AIF1) 2183 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2184 else 2185 return -EINVAL; 2186 break; 2187 case SND_SOC_DAIFMT_IB_IF: 2188 if (dai->id == RT5682_AIF1) 2189 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2190 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2191 else 2192 return -EINVAL; 2193 break; 2194 default: 2195 return -EINVAL; 2196 } 2197 2198 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2199 case SND_SOC_DAIFMT_I2S: 2200 break; 2201 case SND_SOC_DAIFMT_LEFT_J: 2202 reg_val |= RT5682_I2S_DF_LEFT; 2203 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2204 break; 2205 case SND_SOC_DAIFMT_DSP_A: 2206 reg_val |= RT5682_I2S_DF_PCM_A; 2207 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2208 break; 2209 case SND_SOC_DAIFMT_DSP_B: 2210 reg_val |= RT5682_I2S_DF_PCM_B; 2211 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2212 break; 2213 default: 2214 return -EINVAL; 2215 } 2216 2217 switch (dai->id) { 2218 case RT5682_AIF1: 2219 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2220 RT5682_I2S_DF_MASK, reg_val); 2221 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2222 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2223 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2224 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2225 tdm_ctrl | rt5682->master[dai->id]); 2226 break; 2227 case RT5682_AIF2: 2228 if (rt5682->master[dai->id] == 0) 2229 reg_val |= RT5682_I2S2_MS_S; 2230 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2231 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2232 RT5682_I2S_DF_MASK, reg_val); 2233 break; 2234 default: 2235 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2236 return -EINVAL; 2237 } 2238 return 0; 2239} 2240 2241static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2242 int clk_id, int source, unsigned int freq, int dir) 2243{ 2244 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2245 unsigned int reg_val = 0, src = 0; 2246 2247 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2248 return 0; 2249 2250 switch (clk_id) { 2251 case RT5682_SCLK_S_MCLK: 2252 reg_val |= RT5682_SCLK_SRC_MCLK; 2253 src = RT5682_CLK_SRC_MCLK; 2254 break; 2255 case RT5682_SCLK_S_PLL1: 2256 reg_val |= RT5682_SCLK_SRC_PLL1; 2257 src = RT5682_CLK_SRC_PLL1; 2258 break; 2259 case RT5682_SCLK_S_PLL2: 2260 reg_val |= RT5682_SCLK_SRC_PLL2; 2261 src = RT5682_CLK_SRC_PLL2; 2262 break; 2263 case RT5682_SCLK_S_RCCLK: 2264 reg_val |= RT5682_SCLK_SRC_RCCLK; 2265 src = RT5682_CLK_SRC_RCCLK; 2266 break; 2267 default: 2268 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2269 return -EINVAL; 2270 } 2271 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2272 RT5682_SCLK_SRC_MASK, reg_val); 2273 2274 if (rt5682->master[RT5682_AIF2]) { 2275 snd_soc_component_update_bits(component, 2276 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2277 src << RT5682_I2S2_SRC_SFT); 2278 } 2279 2280 rt5682->sysclk = freq; 2281 rt5682->sysclk_src = clk_id; 2282 2283 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2284 freq, clk_id); 2285 2286 return 0; 2287} 2288 2289static int rt5682_set_component_pll(struct snd_soc_component *component, 2290 int pll_id, int source, unsigned int freq_in, 2291 unsigned int freq_out) 2292{ 2293 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2294 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2295 unsigned int pll2_fout1, pll2_ps_val; 2296 int ret; 2297 2298 if (source == rt5682->pll_src[pll_id] && 2299 freq_in == rt5682->pll_in[pll_id] && 2300 freq_out == rt5682->pll_out[pll_id]) 2301 return 0; 2302 2303 if (!freq_in || !freq_out) { 2304 dev_dbg(component->dev, "PLL disabled\n"); 2305 2306 rt5682->pll_in[pll_id] = 0; 2307 rt5682->pll_out[pll_id] = 0; 2308 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2309 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2310 return 0; 2311 } 2312 2313 if (pll_id == RT5682_PLL2) { 2314 switch (source) { 2315 case RT5682_PLL2_S_MCLK: 2316 snd_soc_component_update_bits(component, 2317 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2318 RT5682_PLL2_SRC_MCLK); 2319 break; 2320 default: 2321 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2322 source); 2323 return -EINVAL; 2324 } 2325 2326 /** 2327 * PLL2 concatenates 2 PLL units. 2328 * We suggest the Fout of the front PLL is 3.84MHz. 2329 */ 2330 pll2_fout1 = 3840000; 2331 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2332 if (ret < 0) { 2333 dev_err(component->dev, "Unsupport input clock %d\n", 2334 freq_in); 2335 return ret; 2336 } 2337 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2338 freq_in, pll2_fout1, 2339 pll2f_code.m_bp, 2340 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2341 pll2f_code.n_code, pll2f_code.k_code); 2342 2343 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2344 if (ret < 0) { 2345 dev_err(component->dev, "Unsupport input clock %d\n", 2346 pll2_fout1); 2347 return ret; 2348 } 2349 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2350 pll2_fout1, freq_out, 2351 pll2b_code.m_bp, 2352 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2353 pll2b_code.n_code, pll2b_code.k_code); 2354 2355 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2356 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2357 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2358 pll2b_code.m_code); 2359 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2360 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2361 pll2b_code.n_code); 2362 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2363 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2364 2365 if (freq_out == 22579200) 2366 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; 2367 else 2368 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; 2369 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2370 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | 2371 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2372 pll2_ps_val | 2373 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2374 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2375 0xf); 2376 } else { 2377 switch (source) { 2378 case RT5682_PLL1_S_MCLK: 2379 snd_soc_component_update_bits(component, 2380 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2381 RT5682_PLL1_SRC_MCLK); 2382 break; 2383 case RT5682_PLL1_S_BCLK1: 2384 snd_soc_component_update_bits(component, 2385 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2386 RT5682_PLL1_SRC_BCLK1); 2387 break; 2388 default: 2389 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2390 source); 2391 return -EINVAL; 2392 } 2393 2394 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2395 if (ret < 0) { 2396 dev_err(component->dev, "Unsupport input clock %d\n", 2397 freq_in); 2398 return ret; 2399 } 2400 2401 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2402 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2403 pll_code.n_code, pll_code.k_code); 2404 2405 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2406 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2407 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2408 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2409 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2410 } 2411 2412 rt5682->pll_in[pll_id] = freq_in; 2413 rt5682->pll_out[pll_id] = freq_out; 2414 rt5682->pll_src[pll_id] = source; 2415 2416 return 0; 2417} 2418 2419static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2420{ 2421 struct snd_soc_component *component = dai->component; 2422 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2423 2424 rt5682->bclk[dai->id] = ratio; 2425 2426 switch (ratio) { 2427 case 256: 2428 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2429 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2430 break; 2431 case 128: 2432 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2433 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2434 break; 2435 case 64: 2436 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2437 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2438 break; 2439 case 32: 2440 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2441 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2442 break; 2443 default: 2444 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2445 return -EINVAL; 2446 } 2447 2448 return 0; 2449} 2450 2451static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2452{ 2453 struct snd_soc_component *component = dai->component; 2454 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2455 2456 rt5682->bclk[dai->id] = ratio; 2457 2458 switch (ratio) { 2459 case 64: 2460 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2461 RT5682_I2S2_BCLK_MS2_MASK, 2462 RT5682_I2S2_BCLK_MS2_64); 2463 break; 2464 case 32: 2465 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2466 RT5682_I2S2_BCLK_MS2_MASK, 2467 RT5682_I2S2_BCLK_MS2_32); 2468 break; 2469 default: 2470 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2471 return -EINVAL; 2472 } 2473 2474 return 0; 2475} 2476 2477static int rt5682_set_bias_level(struct snd_soc_component *component, 2478 enum snd_soc_bias_level level) 2479{ 2480 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2481 2482 switch (level) { 2483 case SND_SOC_BIAS_PREPARE: 2484 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2485 RT5682_PWR_BG, RT5682_PWR_BG); 2486 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2487 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2488 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2489 break; 2490 2491 case SND_SOC_BIAS_STANDBY: 2492 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2493 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2494 break; 2495 case SND_SOC_BIAS_OFF: 2496 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2497 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2498 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2499 RT5682_PWR_BG, 0); 2500 break; 2501 case SND_SOC_BIAS_ON: 2502 break; 2503 } 2504 2505 return 0; 2506} 2507 2508#ifdef CONFIG_COMMON_CLK 2509#define CLK_PLL2_FIN 48000000 2510#define CLK_48 48000 2511#define CLK_44 44100 2512 2513static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2514{ 2515 if (!rt5682->master[RT5682_AIF1]) { 2516 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n"); 2517 return false; 2518 } 2519 return true; 2520} 2521 2522static int rt5682_wclk_prepare(struct clk_hw *hw) 2523{ 2524 struct rt5682_priv *rt5682 = 2525 container_of(hw, struct rt5682_priv, 2526 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2527 struct snd_soc_component *component = rt5682->component; 2528 struct snd_soc_dapm_context *dapm = 2529 snd_soc_component_get_dapm(component); 2530 2531 if (!rt5682_clk_check(rt5682)) 2532 return -EINVAL; 2533 2534 snd_soc_dapm_mutex_lock(dapm); 2535 2536 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2537 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2538 RT5682_PWR_MB, RT5682_PWR_MB); 2539 2540 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2541 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2542 RT5682_PWR_VREF2 | RT5682_PWR_FV2, 2543 RT5682_PWR_VREF2); 2544 usleep_range(55000, 60000); 2545 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2546 RT5682_PWR_FV2, RT5682_PWR_FV2); 2547 2548 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2549 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2550 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2551 snd_soc_dapm_sync_unlocked(dapm); 2552 2553 snd_soc_dapm_mutex_unlock(dapm); 2554 2555 return 0; 2556} 2557 2558static void rt5682_wclk_unprepare(struct clk_hw *hw) 2559{ 2560 struct rt5682_priv *rt5682 = 2561 container_of(hw, struct rt5682_priv, 2562 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2563 struct snd_soc_component *component = rt5682->component; 2564 struct snd_soc_dapm_context *dapm = 2565 snd_soc_component_get_dapm(component); 2566 2567 if (!rt5682_clk_check(rt5682)) 2568 return; 2569 2570 snd_soc_dapm_mutex_lock(dapm); 2571 2572 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2573 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2574 if (!rt5682->jack_type) 2575 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2576 RT5682_PWR_VREF2 | RT5682_PWR_FV2 | 2577 RT5682_PWR_MB, 0); 2578 2579 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2580 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2581 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2582 snd_soc_dapm_sync_unlocked(dapm); 2583 2584 snd_soc_dapm_mutex_unlock(dapm); 2585} 2586 2587static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2588 unsigned long parent_rate) 2589{ 2590 struct rt5682_priv *rt5682 = 2591 container_of(hw, struct rt5682_priv, 2592 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2593 struct snd_soc_component *component = rt5682->component; 2594 const char * const clk_name = clk_hw_get_name(hw); 2595 2596 if (!rt5682_clk_check(rt5682)) 2597 return 0; 2598 /* 2599 * Only accept to set wclk rate to 44.1k or 48kHz. 2600 */ 2601 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && 2602 rt5682->lrck[RT5682_AIF1] != CLK_44) { 2603 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2604 __func__, clk_name, CLK_44, CLK_48); 2605 return 0; 2606 } 2607 2608 return rt5682->lrck[RT5682_AIF1]; 2609} 2610 2611static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2612 unsigned long *parent_rate) 2613{ 2614 struct rt5682_priv *rt5682 = 2615 container_of(hw, struct rt5682_priv, 2616 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2617 struct snd_soc_component *component = rt5682->component; 2618 const char * const clk_name = clk_hw_get_name(hw); 2619 2620 if (!rt5682_clk_check(rt5682)) 2621 return -EINVAL; 2622 /* 2623 * Only accept to set wclk rate to 44.1k or 48kHz. 2624 * It will force to 48kHz if not both. 2625 */ 2626 if (rate != CLK_48 && rate != CLK_44) { 2627 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2628 __func__, clk_name, CLK_44, CLK_48); 2629 rate = CLK_48; 2630 } 2631 2632 return rate; 2633} 2634 2635static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2636 unsigned long parent_rate) 2637{ 2638 struct rt5682_priv *rt5682 = 2639 container_of(hw, struct rt5682_priv, 2640 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2641 struct snd_soc_component *component = rt5682->component; 2642 struct clk *parent_clk; 2643 const char * const clk_name = clk_hw_get_name(hw); 2644 int pre_div; 2645 unsigned int clk_pll2_out; 2646 2647 if (!rt5682_clk_check(rt5682)) 2648 return -EINVAL; 2649 2650 /* 2651 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2652 * it is fixed or set to 48MHz before setting wclk rate. It's a 2653 * temporary limitation. Only accept 48MHz clk as the clk provider. 2654 * 2655 * It will set the codec anyway by assuming mclk is 48MHz. 2656 */ 2657 parent_clk = clk_get_parent(hw->clk); 2658 if (!parent_clk) 2659 dev_warn(component->dev, 2660 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2661 CLK_PLL2_FIN); 2662 2663 if (parent_rate != CLK_PLL2_FIN) 2664 dev_warn(component->dev, "clk %s only support %d Hz input\n", 2665 clk_name, CLK_PLL2_FIN); 2666 2667 /* 2668 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2669 * PLL2 is needed. 2670 */ 2671 clk_pll2_out = rate * 512; 2672 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2673 CLK_PLL2_FIN, clk_pll2_out); 2674 2675 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2676 clk_pll2_out, SND_SOC_CLOCK_IN); 2677 2678 rt5682->lrck[RT5682_AIF1] = rate; 2679 2680 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2681 2682 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2683 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2684 pre_div << RT5682_I2S_M_DIV_SFT | 2685 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2686 2687 return 0; 2688} 2689 2690static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2691 unsigned long parent_rate) 2692{ 2693 struct rt5682_priv *rt5682 = 2694 container_of(hw, struct rt5682_priv, 2695 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2696 struct snd_soc_component *component = rt5682->component; 2697 unsigned int bclks_per_wclk; 2698 2699 bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL); 2700 2701 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2702 case RT5682_TDM_BCLK_MS1_256: 2703 return parent_rate * 256; 2704 case RT5682_TDM_BCLK_MS1_128: 2705 return parent_rate * 128; 2706 case RT5682_TDM_BCLK_MS1_64: 2707 return parent_rate * 64; 2708 case RT5682_TDM_BCLK_MS1_32: 2709 return parent_rate * 32; 2710 default: 2711 return 0; 2712 } 2713} 2714 2715static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2716 unsigned long parent_rate) 2717{ 2718 unsigned long factor; 2719 2720 factor = rate / parent_rate; 2721 if (factor < 64) 2722 return 32; 2723 else if (factor < 128) 2724 return 64; 2725 else if (factor < 256) 2726 return 128; 2727 else 2728 return 256; 2729} 2730 2731static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2732 unsigned long *parent_rate) 2733{ 2734 struct rt5682_priv *rt5682 = 2735 container_of(hw, struct rt5682_priv, 2736 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2737 unsigned long factor; 2738 2739 if (!*parent_rate || !rt5682_clk_check(rt5682)) 2740 return -EINVAL; 2741 2742 /* 2743 * BCLK rates are set as a multiplier of WCLK in HW. 2744 * We don't allow changing the parent WCLK. We just do 2745 * some rounding down based on the parent WCLK rate 2746 * and find the appropriate multiplier of BCLK to 2747 * get the rounded down BCLK value. 2748 */ 2749 factor = rt5682_bclk_get_factor(rate, *parent_rate); 2750 2751 return *parent_rate * factor; 2752} 2753 2754static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2755 unsigned long parent_rate) 2756{ 2757 struct rt5682_priv *rt5682 = 2758 container_of(hw, struct rt5682_priv, 2759 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2760 struct snd_soc_component *component = rt5682->component; 2761 struct snd_soc_dai *dai = NULL; 2762 unsigned long factor; 2763 2764 if (!rt5682_clk_check(rt5682)) 2765 return -EINVAL; 2766 2767 factor = rt5682_bclk_get_factor(rate, parent_rate); 2768 2769 for_each_component_dais(component, dai) 2770 if (dai->id == RT5682_AIF1) 2771 break; 2772 if (!dai) { 2773 dev_err(component->dev, "dai %d not found in component\n", 2774 RT5682_AIF1); 2775 return -ENODEV; 2776 } 2777 2778 return rt5682_set_bclk1_ratio(dai, factor); 2779} 2780 2781static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2782 [RT5682_DAI_WCLK_IDX] = { 2783 .prepare = rt5682_wclk_prepare, 2784 .unprepare = rt5682_wclk_unprepare, 2785 .recalc_rate = rt5682_wclk_recalc_rate, 2786 .round_rate = rt5682_wclk_round_rate, 2787 .set_rate = rt5682_wclk_set_rate, 2788 }, 2789 [RT5682_DAI_BCLK_IDX] = { 2790 .recalc_rate = rt5682_bclk_recalc_rate, 2791 .round_rate = rt5682_bclk_round_rate, 2792 .set_rate = rt5682_bclk_set_rate, 2793 }, 2794}; 2795 2796static int rt5682_register_dai_clks(struct snd_soc_component *component) 2797{ 2798 struct device *dev = component->dev; 2799 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2800 struct rt5682_platform_data *pdata = &rt5682->pdata; 2801 struct clk_hw *dai_clk_hw; 2802 int i, ret; 2803 2804 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2805 struct clk_init_data init = { }; 2806 struct clk_parent_data parent_data; 2807 const struct clk_hw *parent; 2808 2809 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2810 2811 switch (i) { 2812 case RT5682_DAI_WCLK_IDX: 2813 /* Make MCLK the parent of WCLK */ 2814 if (rt5682->mclk) { 2815 parent_data = (struct clk_parent_data){ 2816 .fw_name = "mclk", 2817 }; 2818 init.parent_data = &parent_data; 2819 init.num_parents = 1; 2820 } 2821 break; 2822 case RT5682_DAI_BCLK_IDX: 2823 /* Make WCLK the parent of BCLK */ 2824 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]; 2825 init.parent_hws = &parent; 2826 init.num_parents = 1; 2827 break; 2828 default: 2829 dev_err(dev, "Invalid clock index\n"); 2830 return -EINVAL; 2831 } 2832 2833 init.name = pdata->dai_clk_names[i]; 2834 init.ops = &rt5682_dai_clk_ops[i]; 2835 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2836 dai_clk_hw->init = &init; 2837 2838 ret = devm_clk_hw_register(dev, dai_clk_hw); 2839 if (ret) { 2840 dev_warn(dev, "Failed to register %s: %d\n", 2841 init.name, ret); 2842 return ret; 2843 } 2844 2845 if (dev->of_node) { 2846 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2847 dai_clk_hw); 2848 } else { 2849 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw, 2850 init.name, 2851 dev_name(dev)); 2852 if (ret) 2853 return ret; 2854 } 2855 } 2856 2857 return 0; 2858} 2859#endif /* CONFIG_COMMON_CLK */ 2860 2861static int rt5682_probe(struct snd_soc_component *component) 2862{ 2863 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2864 struct sdw_slave *slave; 2865 unsigned long time; 2866 struct snd_soc_dapm_context *dapm = &component->dapm; 2867 2868#ifdef CONFIG_COMMON_CLK 2869 int ret; 2870#endif 2871 rt5682->component = component; 2872 2873 if (rt5682->is_sdw) { 2874 slave = rt5682->slave; 2875 time = wait_for_completion_timeout( 2876 &slave->initialization_complete, 2877 msecs_to_jiffies(RT5682_PROBE_TIMEOUT)); 2878 if (!time) { 2879 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 2880 return -ETIMEDOUT; 2881 } 2882 } else { 2883#ifdef CONFIG_COMMON_CLK 2884 /* Check if MCLK provided */ 2885 rt5682->mclk = devm_clk_get(component->dev, "mclk"); 2886 if (IS_ERR(rt5682->mclk)) { 2887 if (PTR_ERR(rt5682->mclk) != -ENOENT) { 2888 ret = PTR_ERR(rt5682->mclk); 2889 return ret; 2890 } 2891 rt5682->mclk = NULL; 2892 } 2893 2894 /* Register CCF DAI clock control */ 2895 ret = rt5682_register_dai_clks(component); 2896 if (ret) 2897 return ret; 2898 2899 /* Initial setup for CCF */ 2900 rt5682->lrck[RT5682_AIF1] = CLK_48; 2901#endif 2902 } 2903 2904 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2905 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2906 snd_soc_dapm_sync(dapm); 2907 return 0; 2908} 2909 2910static void rt5682_remove(struct snd_soc_component *component) 2911{ 2912 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2913 2914 rt5682_reset(rt5682); 2915} 2916 2917#ifdef CONFIG_PM 2918static int rt5682_suspend(struct snd_soc_component *component) 2919{ 2920 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2921 2922 regcache_cache_only(rt5682->regmap, true); 2923 regcache_mark_dirty(rt5682->regmap); 2924 return 0; 2925} 2926 2927static int rt5682_resume(struct snd_soc_component *component) 2928{ 2929 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2930 2931 regcache_cache_only(rt5682->regmap, false); 2932 regcache_sync(rt5682->regmap); 2933 2934 mod_delayed_work(system_power_efficient_wq, 2935 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 2936 2937 return 0; 2938} 2939#else 2940#define rt5682_suspend NULL 2941#define rt5682_resume NULL 2942#endif 2943 2944const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2945 .hw_params = rt5682_hw_params, 2946 .set_fmt = rt5682_set_dai_fmt, 2947 .set_tdm_slot = rt5682_set_tdm_slot, 2948 .set_bclk_ratio = rt5682_set_bclk1_ratio, 2949}; 2950EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops); 2951 2952const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2953 .hw_params = rt5682_hw_params, 2954 .set_fmt = rt5682_set_dai_fmt, 2955 .set_bclk_ratio = rt5682_set_bclk2_ratio, 2956}; 2957EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops); 2958 2959const struct snd_soc_component_driver rt5682_soc_component_dev = { 2960 .probe = rt5682_probe, 2961 .remove = rt5682_remove, 2962 .suspend = rt5682_suspend, 2963 .resume = rt5682_resume, 2964 .set_bias_level = rt5682_set_bias_level, 2965 .controls = rt5682_snd_controls, 2966 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2967 .dapm_widgets = rt5682_dapm_widgets, 2968 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2969 .dapm_routes = rt5682_dapm_routes, 2970 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2971 .set_sysclk = rt5682_set_component_sysclk, 2972 .set_pll = rt5682_set_component_pll, 2973 .set_jack = rt5682_set_jack_detect, 2974 .use_pmdown_time = 1, 2975 .endianness = 1, 2976 .non_legacy_dai_naming = 1, 2977}; 2978EXPORT_SYMBOL_GPL(rt5682_soc_component_dev); 2979 2980int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2981{ 2982 2983 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2984 &rt5682->pdata.dmic1_data_pin); 2985 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2986 &rt5682->pdata.dmic1_clk_pin); 2987 device_property_read_u32(dev, "realtek,jd-src", 2988 &rt5682->pdata.jd_src); 2989 device_property_read_u32(dev, "realtek,btndet-delay", 2990 &rt5682->pdata.btndet_delay); 2991 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 2992 &rt5682->pdata.dmic_clk_rate); 2993 device_property_read_u32(dev, "realtek,dmic-delay-ms", 2994 &rt5682->pdata.dmic_delay); 2995 2996 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2997 "realtek,ldo1-en-gpios", 0); 2998 2999 if (device_property_read_string_array(dev, "clock-output-names", 3000 rt5682->pdata.dai_clk_names, 3001 RT5682_DAI_NUM_CLKS) < 0) 3002 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 3003 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 3004 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 3005 3006 return 0; 3007} 3008EXPORT_SYMBOL_GPL(rt5682_parse_dt); 3009 3010void rt5682_calibrate(struct rt5682_priv *rt5682) 3011{ 3012 int value, count; 3013 3014 mutex_lock(&rt5682->calibrate_mutex); 3015 3016 rt5682_reset(rt5682); 3017 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 3018 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 3019 usleep_range(15000, 20000); 3020 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 3021 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 3022 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 3023 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 3024 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 3025 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 3026 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 3027 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 3028 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 3029 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 3030 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 3031 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3032 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 3033 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 3034 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3035 3036 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 3037 3038 for (count = 0; count < 60; count++) { 3039 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 3040 if (!(value & 0x8000)) 3041 break; 3042 3043 usleep_range(10000, 10005); 3044 } 3045 3046 if (count >= 60) 3047 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); 3048 3049 /* restore settings */ 3050 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); 3051 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 3052 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 3053 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3054 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3055 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3056 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3057 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); 3058 3059 mutex_unlock(&rt5682->calibrate_mutex); 3060} 3061EXPORT_SYMBOL_GPL(rt5682_calibrate); 3062 3063MODULE_DESCRIPTION("ASoC RT5682 driver"); 3064MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3065MODULE_LICENSE("GPL v2"); 3066