1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * rt1308-sdw.h -- RT1308 ALSA SoC audio driver header
4 *
5 * Copyright(c) 2019 Realtek Semiconductor Corp.
6 */
7
8#ifndef __RT1308_SDW_H__
9#define __RT1308_SDW_H__
10
11static const struct reg_default rt1308_reg_defaults[] = {
12	{ 0x0000, 0x00 },
13	{ 0x0001, 0x00 },
14	{ 0x0002, 0x00 },
15	{ 0x0003, 0x00 },
16	{ 0x0004, 0x00 },
17	{ 0x0005, 0x01 },
18	{ 0x0020, 0x00 },
19	{ 0x0022, 0x00 },
20	{ 0x0023, 0x00 },
21	{ 0x0024, 0x00 },
22	{ 0x0025, 0x00 },
23	{ 0x0026, 0x00 },
24	{ 0x0030, 0x00 },
25	{ 0x0032, 0x00 },
26	{ 0x0033, 0x00 },
27	{ 0x0034, 0x00 },
28	{ 0x0035, 0x00 },
29	{ 0x0036, 0x00 },
30	{ 0x0040, 0x00 },
31	{ 0x0041, 0x00 },
32	{ 0x0042, 0x00 },
33	{ 0x0043, 0x00 },
34	{ 0x0044, 0x20 },
35	{ 0x0045, 0x01 },
36	{ 0x0046, 0x01 },
37	{ 0x0048, 0x00 },
38	{ 0x0049, 0x00 },
39	{ 0x0050, 0x20 },
40	{ 0x0051, 0x02 },
41	{ 0x0052, 0x5D },
42	{ 0x0053, 0x13 },
43	{ 0x0054, 0x08 },
44	{ 0x0055, 0x00 },
45	{ 0x0060, 0x00 },
46	{ 0x0070, 0x00 },
47	{ 0x00E0, 0x00 },
48	{ 0x00F0, 0x00 },
49	{ 0x0100, 0x00 },
50	{ 0x0101, 0x00 },
51	{ 0x0102, 0x20 },
52	{ 0x0103, 0x00 },
53	{ 0x0104, 0x00 },
54	{ 0x0105, 0x03 },
55	{ 0x0120, 0x00 },
56	{ 0x0122, 0x00 },
57	{ 0x0123, 0x00 },
58	{ 0x0124, 0x00 },
59	{ 0x0125, 0x00 },
60	{ 0x0126, 0x00 },
61	{ 0x0127, 0x00 },
62	{ 0x0130, 0x00 },
63	{ 0x0132, 0x00 },
64	{ 0x0133, 0x00 },
65	{ 0x0134, 0x00 },
66	{ 0x0135, 0x00 },
67	{ 0x0136, 0x00 },
68	{ 0x0137, 0x00 },
69	{ 0x0200, 0x00 },
70	{ 0x0201, 0x00 },
71	{ 0x0202, 0x00 },
72	{ 0x0203, 0x00 },
73	{ 0x0204, 0x00 },
74	{ 0x0205, 0x03 },
75	{ 0x0220, 0x00 },
76	{ 0x0222, 0x00 },
77	{ 0x0223, 0x00 },
78	{ 0x0224, 0x00 },
79	{ 0x0225, 0x00 },
80	{ 0x0226, 0x00 },
81	{ 0x0227, 0x00 },
82	{ 0x0230, 0x00 },
83	{ 0x0232, 0x00 },
84	{ 0x0233, 0x00 },
85	{ 0x0234, 0x00 },
86	{ 0x0235, 0x00 },
87	{ 0x0236, 0x00 },
88	{ 0x0237, 0x00 },
89	{ 0x0400, 0x00 },
90	{ 0x0401, 0x00 },
91	{ 0x0402, 0x00 },
92	{ 0x0403, 0x00 },
93	{ 0x0404, 0x00 },
94	{ 0x0405, 0x03 },
95	{ 0x0420, 0x00 },
96	{ 0x0422, 0x00 },
97	{ 0x0423, 0x00 },
98	{ 0x0424, 0x00 },
99	{ 0x0425, 0x00 },
100	{ 0x0426, 0x00 },
101	{ 0x0427, 0x00 },
102	{ 0x0430, 0x00 },
103	{ 0x0432, 0x00 },
104	{ 0x0433, 0x00 },
105	{ 0x0434, 0x00 },
106	{ 0x0435, 0x00 },
107	{ 0x0436, 0x00 },
108	{ 0x0437, 0x00 },
109	{ 0x0f00, 0x00 },
110	{ 0x0f01, 0x00 },
111	{ 0x0f02, 0x00 },
112	{ 0x0f03, 0x00 },
113	{ 0x0f04, 0x00 },
114	{ 0x0f05, 0x00 },
115	{ 0x0f20, 0x00 },
116	{ 0x0f22, 0x00 },
117	{ 0x0f23, 0x00 },
118	{ 0x0f24, 0x00 },
119	{ 0x0f25, 0x00 },
120	{ 0x0f26, 0x00 },
121	{ 0x0f27, 0x00 },
122	{ 0x0f30, 0x00 },
123	{ 0x0f32, 0x00 },
124	{ 0x0f33, 0x00 },
125	{ 0x0f34, 0x00 },
126	{ 0x0f35, 0x00 },
127	{ 0x0f36, 0x00 },
128	{ 0x0f37, 0x00 },
129	{ 0x2f01, 0x01 },
130	{ 0x2f02, 0x09 },
131	{ 0x2f03, 0x00 },
132	{ 0x2f04, 0x0f },
133	{ 0x2f05, 0x0b },
134	{ 0x2f06, 0x01 },
135	{ 0x2f07, 0x8e },
136	{ 0x3000, 0x00 },
137	{ 0x3001, 0x00 },
138	{ 0x3004, 0x01 },
139	{ 0x3005, 0x23 },
140	{ 0x3008, 0x02 },
141	{ 0x300a, 0x00 },
142	{ 0xc000 | (RT1308_DATA_PATH << 4), 0x00 },
143	{ 0xc003 | (RT1308_DAC_SET << 4), 0x00 },
144	{ 0xc001 | (RT1308_POWER << 4), 0x00 },
145	{ 0xc002 | (RT1308_POWER << 4), 0x00 },
146	{ 0xc000 | (RT1308_POWER_STATUS << 4), 0x00 },
147};
148
149#define RT1308_SDW_OFFSET 0xc000
150#define RT1308_SDW_OFFSET_BYTE0 0xc000
151#define RT1308_SDW_OFFSET_BYTE1 0xc001
152#define RT1308_SDW_OFFSET_BYTE2 0xc002
153#define RT1308_SDW_OFFSET_BYTE3 0xc003
154
155#define RT1308_SDW_RESET (RT1308_SDW_OFFSET | (RT1308_RESET << 4))
156
157struct rt1308_sdw_priv {
158	struct snd_soc_component *component;
159	struct regmap *regmap;
160	struct sdw_slave *sdw_slave;
161	enum sdw_slave_status status;
162	struct sdw_bus_params params;
163	bool hw_init;
164	bool first_hw_init;
165	int rx_mask;
166	int slots;
167};
168
169struct sdw_stream_data {
170	struct sdw_stream_runtime *sdw_stream;
171};
172
173#endif /* __RT1308_SDW_H__ */
174