1// SPDX-License-Identifier: GPL-2.0 2// 3// rt1015.c -- RT1015 ALSA SoC audio amplifier driver 4// 5// Copyright 2019 Realtek Semiconductor Corp. 6// 7// Author: Jack Yu <jack.yu@realtek.com> 8// 9// 10 11#include <linux/acpi.h> 12#include <linux/delay.h> 13#include <linux/firmware.h> 14#include <linux/fs.h> 15#include <linux/gpio.h> 16#include <linux/i2c.h> 17#include <linux/init.h> 18#include <linux/module.h> 19#include <linux/moduleparam.h> 20#include <linux/platform_device.h> 21#include <linux/pm.h> 22#include <linux/regmap.h> 23#include <sound/core.h> 24#include <sound/initval.h> 25#include <sound/pcm.h> 26#include <sound/pcm_params.h> 27#include <sound/soc-dapm.h> 28#include <sound/soc.h> 29#include <sound/tlv.h> 30#include <sound/rt1015.h> 31 32#include "rl6231.h" 33#include "rt1015.h" 34 35static const struct rt1015_platform_data i2s_default_platform_data = { 36 .power_up_delay_ms = 50, 37}; 38 39static const struct reg_default rt1015_reg[] = { 40 { 0x0000, 0x0000 }, 41 { 0x0004, 0xa000 }, 42 { 0x0006, 0x0003 }, 43 { 0x000a, 0x081e }, 44 { 0x000c, 0x0006 }, 45 { 0x000e, 0x0000 }, 46 { 0x0010, 0x0000 }, 47 { 0x0012, 0x0000 }, 48 { 0x0014, 0x0000 }, 49 { 0x0016, 0x0000 }, 50 { 0x0018, 0x0000 }, 51 { 0x0020, 0x8000 }, 52 { 0x0022, 0x8043 }, 53 { 0x0076, 0x0000 }, 54 { 0x0078, 0x0000 }, 55 { 0x007a, 0x0002 }, 56 { 0x007c, 0x10ec }, 57 { 0x007d, 0x1015 }, 58 { 0x00f0, 0x5000 }, 59 { 0x00f2, 0x004c }, 60 { 0x00f3, 0xecfe }, 61 { 0x00f4, 0x0000 }, 62 { 0x00f6, 0x0400 }, 63 { 0x0100, 0x0028 }, 64 { 0x0102, 0xff02 }, 65 { 0x0104, 0xa213 }, 66 { 0x0106, 0x200c }, 67 { 0x010c, 0x0000 }, 68 { 0x010e, 0x0058 }, 69 { 0x0111, 0x0200 }, 70 { 0x0112, 0x0400 }, 71 { 0x0114, 0x0022 }, 72 { 0x0116, 0x0000 }, 73 { 0x0118, 0x0000 }, 74 { 0x011a, 0x0123 }, 75 { 0x011c, 0x4567 }, 76 { 0x0300, 0x203d }, 77 { 0x0302, 0x001e }, 78 { 0x0311, 0x0000 }, 79 { 0x0313, 0x6014 }, 80 { 0x0314, 0x00a2 }, 81 { 0x031a, 0x00a0 }, 82 { 0x031c, 0x001f }, 83 { 0x031d, 0xffff }, 84 { 0x031e, 0x0000 }, 85 { 0x031f, 0x0000 }, 86 { 0x0320, 0x0000 }, 87 { 0x0321, 0x0000 }, 88 { 0x0322, 0xd7df }, 89 { 0x0328, 0x10b2 }, 90 { 0x0329, 0x0175 }, 91 { 0x032a, 0x36ad }, 92 { 0x032b, 0x7e55 }, 93 { 0x032c, 0x0520 }, 94 { 0x032d, 0xaa00 }, 95 { 0x032e, 0x570e }, 96 { 0x0330, 0xe180 }, 97 { 0x0332, 0x0034 }, 98 { 0x0334, 0x0001 }, 99 { 0x0336, 0x0010 }, 100 { 0x0338, 0x0000 }, 101 { 0x04fa, 0x0030 }, 102 { 0x04fc, 0x35c8 }, 103 { 0x04fe, 0x0800 }, 104 { 0x0500, 0x0400 }, 105 { 0x0502, 0x1000 }, 106 { 0x0504, 0x0000 }, 107 { 0x0506, 0x04ff }, 108 { 0x0508, 0x0010 }, 109 { 0x050a, 0x001a }, 110 { 0x0519, 0x1c68 }, 111 { 0x051a, 0x0ccc }, 112 { 0x051b, 0x0666 }, 113 { 0x051d, 0x0000 }, 114 { 0x051f, 0x0000 }, 115 { 0x0536, 0x061c }, 116 { 0x0538, 0x0000 }, 117 { 0x053a, 0x0000 }, 118 { 0x053c, 0x0000 }, 119 { 0x053d, 0x0000 }, 120 { 0x053e, 0x0000 }, 121 { 0x053f, 0x0000 }, 122 { 0x0540, 0x0000 }, 123 { 0x0541, 0x0000 }, 124 { 0x0542, 0x0000 }, 125 { 0x0543, 0x0000 }, 126 { 0x0544, 0x0000 }, 127 { 0x0568, 0x0000 }, 128 { 0x056a, 0x0000 }, 129 { 0x1000, 0x0040 }, 130 { 0x1002, 0x5405 }, 131 { 0x1006, 0x5515 }, 132 { 0x1007, 0x05f7 }, 133 { 0x1009, 0x0b0a }, 134 { 0x100a, 0x00ef }, 135 { 0x100d, 0x0003 }, 136 { 0x1010, 0xa433 }, 137 { 0x1020, 0x0000 }, 138 { 0x1200, 0x5a01 }, 139 { 0x1202, 0x6524 }, 140 { 0x1204, 0x1f00 }, 141 { 0x1206, 0x0000 }, 142 { 0x1208, 0x0000 }, 143 { 0x120a, 0x0000 }, 144 { 0x120c, 0x0000 }, 145 { 0x120e, 0x0000 }, 146 { 0x1210, 0x0000 }, 147 { 0x1212, 0x0000 }, 148 { 0x1300, 0x10a1 }, 149 { 0x1302, 0x12ff }, 150 { 0x1304, 0x0400 }, 151 { 0x1305, 0x0844 }, 152 { 0x1306, 0x4611 }, 153 { 0x1308, 0x555e }, 154 { 0x130a, 0x0000 }, 155 { 0x130c, 0x2000 }, 156 { 0x130e, 0x0100 }, 157 { 0x130f, 0x0001 }, 158 { 0x1310, 0x0000 }, 159 { 0x1312, 0x0000 }, 160 { 0x1314, 0x0000 }, 161 { 0x1316, 0x0000 }, 162 { 0x1318, 0x0000 }, 163 { 0x131a, 0x0000 }, 164 { 0x1322, 0x0029 }, 165 { 0x1323, 0x4a52 }, 166 { 0x1324, 0x002c }, 167 { 0x1325, 0x0b02 }, 168 { 0x1326, 0x002d }, 169 { 0x1327, 0x6b5a }, 170 { 0x1328, 0x002e }, 171 { 0x1329, 0xcbb2 }, 172 { 0x132a, 0x0030 }, 173 { 0x132b, 0x2c0b }, 174 { 0x1330, 0x0031 }, 175 { 0x1331, 0x8c63 }, 176 { 0x1332, 0x0032 }, 177 { 0x1333, 0xecbb }, 178 { 0x1334, 0x0034 }, 179 { 0x1335, 0x4d13 }, 180 { 0x1336, 0x0037 }, 181 { 0x1337, 0x0dc3 }, 182 { 0x1338, 0x003d }, 183 { 0x1339, 0xef7b }, 184 { 0x133a, 0x0044 }, 185 { 0x133b, 0xd134 }, 186 { 0x133c, 0x0047 }, 187 { 0x133d, 0x91e4 }, 188 { 0x133e, 0x004d }, 189 { 0x133f, 0xc370 }, 190 { 0x1340, 0x0053 }, 191 { 0x1341, 0xf4fd }, 192 { 0x1342, 0x0060 }, 193 { 0x1343, 0x5816 }, 194 { 0x1344, 0x006c }, 195 { 0x1345, 0xbb2e }, 196 { 0x1346, 0x0072 }, 197 { 0x1347, 0xecbb }, 198 { 0x1348, 0x0076 }, 199 { 0x1349, 0x5d97 }, 200}; 201 202static bool rt1015_volatile_register(struct device *dev, unsigned int reg) 203{ 204 switch (reg) { 205 case RT1015_RESET: 206 case RT1015_CLK_DET: 207 case RT1015_SIL_DET: 208 case RT1015_VER_ID: 209 case RT1015_VENDOR_ID: 210 case RT1015_DEVICE_ID: 211 case RT1015_PRO_ALT: 212 case RT1015_MAN_I2C: 213 case RT1015_DAC3: 214 case RT1015_VBAT_TEST_OUT1: 215 case RT1015_VBAT_TEST_OUT2: 216 case RT1015_VBAT_PROT_ATT: 217 case RT1015_VBAT_DET_CODE: 218 case RT1015_SMART_BST_CTRL1: 219 case RT1015_SPK_DC_DETECT1: 220 case RT1015_SPK_DC_DETECT4: 221 case RT1015_SPK_DC_DETECT5: 222 case RT1015_DC_CALIB_CLSD1: 223 case RT1015_DC_CALIB_CLSD5: 224 case RT1015_DC_CALIB_CLSD6: 225 case RT1015_DC_CALIB_CLSD7: 226 case RT1015_DC_CALIB_CLSD8: 227 case RT1015_S_BST_TIMING_INTER1: 228 case RT1015_OSCK_STA: 229 case RT1015_MONO_DYNA_CTRL1: 230 case RT1015_MONO_DYNA_CTRL5: 231 return true; 232 233 default: 234 return false; 235 } 236} 237 238static bool rt1015_readable_register(struct device *dev, unsigned int reg) 239{ 240 switch (reg) { 241 case RT1015_RESET: 242 case RT1015_CLK2: 243 case RT1015_CLK3: 244 case RT1015_PLL1: 245 case RT1015_PLL2: 246 case RT1015_DUM_RW1: 247 case RT1015_DUM_RW2: 248 case RT1015_DUM_RW3: 249 case RT1015_DUM_RW4: 250 case RT1015_DUM_RW5: 251 case RT1015_DUM_RW6: 252 case RT1015_CLK_DET: 253 case RT1015_SIL_DET: 254 case RT1015_CUSTOMER_ID: 255 case RT1015_PCODE_FWVER: 256 case RT1015_VER_ID: 257 case RT1015_VENDOR_ID: 258 case RT1015_DEVICE_ID: 259 case RT1015_PAD_DRV1: 260 case RT1015_PAD_DRV2: 261 case RT1015_GAT_BOOST: 262 case RT1015_PRO_ALT: 263 case RT1015_OSCK_STA: 264 case RT1015_MAN_I2C: 265 case RT1015_DAC1: 266 case RT1015_DAC2: 267 case RT1015_DAC3: 268 case RT1015_ADC1: 269 case RT1015_ADC2: 270 case RT1015_TDM_MASTER: 271 case RT1015_TDM_TCON: 272 case RT1015_TDM1_1: 273 case RT1015_TDM1_2: 274 case RT1015_TDM1_3: 275 case RT1015_TDM1_4: 276 case RT1015_TDM1_5: 277 case RT1015_MIXER1: 278 case RT1015_MIXER2: 279 case RT1015_ANA_PROTECT1: 280 case RT1015_ANA_CTRL_SEQ1: 281 case RT1015_ANA_CTRL_SEQ2: 282 case RT1015_VBAT_DET_DEB: 283 case RT1015_VBAT_VOLT_DET1: 284 case RT1015_VBAT_VOLT_DET2: 285 case RT1015_VBAT_TEST_OUT1: 286 case RT1015_VBAT_TEST_OUT2: 287 case RT1015_VBAT_PROT_ATT: 288 case RT1015_VBAT_DET_CODE: 289 case RT1015_PWR1: 290 case RT1015_PWR4: 291 case RT1015_PWR5: 292 case RT1015_PWR6: 293 case RT1015_PWR7: 294 case RT1015_PWR8: 295 case RT1015_PWR9: 296 case RT1015_CLASSD_SEQ: 297 case RT1015_SMART_BST_CTRL1: 298 case RT1015_SMART_BST_CTRL2: 299 case RT1015_ANA_CTRL1: 300 case RT1015_ANA_CTRL2: 301 case RT1015_PWR_STATE_CTRL: 302 case RT1015_MONO_DYNA_CTRL: 303 case RT1015_MONO_DYNA_CTRL1: 304 case RT1015_MONO_DYNA_CTRL2: 305 case RT1015_MONO_DYNA_CTRL3: 306 case RT1015_MONO_DYNA_CTRL4: 307 case RT1015_MONO_DYNA_CTRL5: 308 case RT1015_SPK_VOL: 309 case RT1015_SHORT_DETTOP1: 310 case RT1015_SHORT_DETTOP2: 311 case RT1015_SPK_DC_DETECT1: 312 case RT1015_SPK_DC_DETECT2: 313 case RT1015_SPK_DC_DETECT3: 314 case RT1015_SPK_DC_DETECT4: 315 case RT1015_SPK_DC_DETECT5: 316 case RT1015_BAT_RPO_STEP1: 317 case RT1015_BAT_RPO_STEP2: 318 case RT1015_BAT_RPO_STEP3: 319 case RT1015_BAT_RPO_STEP4: 320 case RT1015_BAT_RPO_STEP5: 321 case RT1015_BAT_RPO_STEP6: 322 case RT1015_BAT_RPO_STEP7: 323 case RT1015_BAT_RPO_STEP8: 324 case RT1015_BAT_RPO_STEP9: 325 case RT1015_BAT_RPO_STEP10: 326 case RT1015_BAT_RPO_STEP11: 327 case RT1015_BAT_RPO_STEP12: 328 case RT1015_SPREAD_SPEC1: 329 case RT1015_SPREAD_SPEC2: 330 case RT1015_PAD_STATUS: 331 case RT1015_PADS_PULLING_CTRL1: 332 case RT1015_PADS_DRIVING: 333 case RT1015_SYS_RST1: 334 case RT1015_SYS_RST2: 335 case RT1015_SYS_GATING1: 336 case RT1015_TEST_MODE1: 337 case RT1015_TEST_MODE2: 338 case RT1015_TIMING_CTRL1: 339 case RT1015_PLL_INT: 340 case RT1015_TEST_OUT1: 341 case RT1015_DC_CALIB_CLSD1: 342 case RT1015_DC_CALIB_CLSD2: 343 case RT1015_DC_CALIB_CLSD3: 344 case RT1015_DC_CALIB_CLSD4: 345 case RT1015_DC_CALIB_CLSD5: 346 case RT1015_DC_CALIB_CLSD6: 347 case RT1015_DC_CALIB_CLSD7: 348 case RT1015_DC_CALIB_CLSD8: 349 case RT1015_DC_CALIB_CLSD9: 350 case RT1015_DC_CALIB_CLSD10: 351 case RT1015_CLSD_INTERNAL1: 352 case RT1015_CLSD_INTERNAL2: 353 case RT1015_CLSD_INTERNAL3: 354 case RT1015_CLSD_INTERNAL4: 355 case RT1015_CLSD_INTERNAL5: 356 case RT1015_CLSD_INTERNAL6: 357 case RT1015_CLSD_INTERNAL7: 358 case RT1015_CLSD_INTERNAL8: 359 case RT1015_CLSD_INTERNAL9: 360 case RT1015_CLSD_OCP_CTRL: 361 case RT1015_VREF_LV: 362 case RT1015_MBIAS1: 363 case RT1015_MBIAS2: 364 case RT1015_MBIAS3: 365 case RT1015_MBIAS4: 366 case RT1015_VREF_LV1: 367 case RT1015_S_BST_TIMING_INTER1: 368 case RT1015_S_BST_TIMING_INTER2: 369 case RT1015_S_BST_TIMING_INTER3: 370 case RT1015_S_BST_TIMING_INTER4: 371 case RT1015_S_BST_TIMING_INTER5: 372 case RT1015_S_BST_TIMING_INTER6: 373 case RT1015_S_BST_TIMING_INTER7: 374 case RT1015_S_BST_TIMING_INTER8: 375 case RT1015_S_BST_TIMING_INTER9: 376 case RT1015_S_BST_TIMING_INTER10: 377 case RT1015_S_BST_TIMING_INTER11: 378 case RT1015_S_BST_TIMING_INTER12: 379 case RT1015_S_BST_TIMING_INTER13: 380 case RT1015_S_BST_TIMING_INTER14: 381 case RT1015_S_BST_TIMING_INTER15: 382 case RT1015_S_BST_TIMING_INTER16: 383 case RT1015_S_BST_TIMING_INTER17: 384 case RT1015_S_BST_TIMING_INTER18: 385 case RT1015_S_BST_TIMING_INTER19: 386 case RT1015_S_BST_TIMING_INTER20: 387 case RT1015_S_BST_TIMING_INTER21: 388 case RT1015_S_BST_TIMING_INTER22: 389 case RT1015_S_BST_TIMING_INTER23: 390 case RT1015_S_BST_TIMING_INTER24: 391 case RT1015_S_BST_TIMING_INTER25: 392 case RT1015_S_BST_TIMING_INTER26: 393 case RT1015_S_BST_TIMING_INTER27: 394 case RT1015_S_BST_TIMING_INTER28: 395 case RT1015_S_BST_TIMING_INTER29: 396 case RT1015_S_BST_TIMING_INTER30: 397 case RT1015_S_BST_TIMING_INTER31: 398 case RT1015_S_BST_TIMING_INTER32: 399 case RT1015_S_BST_TIMING_INTER33: 400 case RT1015_S_BST_TIMING_INTER34: 401 case RT1015_S_BST_TIMING_INTER35: 402 case RT1015_S_BST_TIMING_INTER36: 403 return true; 404 405 default: 406 return false; 407 } 408} 409 410static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0); 411 412static const char * const rt1015_din_source_select[] = { 413 "Left", 414 "Right", 415 "Left + Right average", 416}; 417 418static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4, 419 rt1015_din_source_select); 420 421static const char * const rt1015_boost_mode[] = { 422 "Bypass", "Adaptive", "Fixed Adaptive" 423}; 424 425static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0, 426 rt1015_boost_mode); 427 428static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol, 429 struct snd_ctl_elem_value *ucontrol) 430{ 431 struct snd_soc_component *component = 432 snd_soc_kcontrol_component(kcontrol); 433 struct rt1015_priv *rt1015 = 434 snd_soc_component_get_drvdata(component); 435 436 ucontrol->value.integer.value[0] = rt1015->boost_mode; 437 438 return 0; 439} 440 441static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol, 442 struct snd_ctl_elem_value *ucontrol) 443{ 444 struct snd_soc_component *component = 445 snd_soc_kcontrol_component(kcontrol); 446 struct rt1015_priv *rt1015 = 447 snd_soc_component_get_drvdata(component); 448 449 rt1015->boost_mode = ucontrol->value.integer.value[0]; 450 451 switch (rt1015->boost_mode) { 452 case BYPASS: 453 snd_soc_component_update_bits(component, 454 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 455 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 456 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS | 457 RT1015_BYPASS_SWRREG_BYPASS); 458 break; 459 case ADAPTIVE: 460 snd_soc_component_update_bits(component, 461 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 462 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 463 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS | 464 RT1015_BYPASS_SWRREG_PASS); 465 break; 466 case FIXED_ADAPTIVE: 467 snd_soc_component_update_bits(component, 468 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK | 469 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK, 470 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN | 471 RT1015_BYPASS_SWRREG_PASS); 472 break; 473 default: 474 dev_err(component->dev, "Unknown boost control.\n"); 475 } 476 477 return 0; 478} 479 480static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol, 481 struct snd_ctl_elem_value *ucontrol) 482{ 483 struct snd_soc_component *component = 484 snd_soc_kcontrol_component(kcontrol); 485 struct rt1015_priv *rt1015 = 486 snd_soc_component_get_drvdata(component); 487 488 ucontrol->value.integer.value[0] = rt1015->bypass_boost; 489 490 return 0; 491} 492 493static void rt1015_calibrate(struct rt1015_priv *rt1015) 494{ 495 struct snd_soc_component *component = rt1015->component; 496 struct regmap *regmap = rt1015->regmap; 497 498 snd_soc_dapm_mutex_lock(&component->dapm); 499 regcache_cache_bypass(regmap, true); 500 501 regmap_write(regmap, RT1015_PWR1, 0xd7df); 502 regmap_write(regmap, RT1015_PWR4, 0x00b2); 503 regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2008); 504 regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140); 505 regmap_write(regmap, RT1015_GAT_BOOST, 0x0efe); 506 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000d); 507 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000e); 508 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a00); 509 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a01); 510 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a05); 511 msleep(500); 512 regmap_write(regmap, RT1015_PWR1, 0x0); 513 514 regcache_cache_bypass(regmap, false); 515 regcache_mark_dirty(regmap); 516 regcache_sync(regmap); 517 snd_soc_dapm_mutex_unlock(&component->dapm); 518} 519 520static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol, 521 struct snd_ctl_elem_value *ucontrol) 522{ 523 struct snd_soc_component *component = 524 snd_soc_kcontrol_component(kcontrol); 525 struct rt1015_priv *rt1015 = 526 snd_soc_component_get_drvdata(component); 527 528 if (!rt1015->dac_is_used) { 529 rt1015->bypass_boost = ucontrol->value.integer.value[0]; 530 if (rt1015->bypass_boost == RT1015_Bypass_Boost && 531 !rt1015->cali_done) { 532 rt1015_calibrate(rt1015); 533 rt1015->cali_done = 1; 534 535 regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010); 536 } 537 } else 538 dev_err(component->dev, "DAC is being used!\n"); 539 540 return 0; 541} 542 543static void rt1015_flush_work(struct work_struct *work) 544{ 545 struct rt1015_priv *rt1015 = container_of(work, struct rt1015_priv, 546 flush_work.work); 547 struct snd_soc_component *component = rt1015->component; 548 unsigned int val, i = 0, count = 200; 549 550 while (i < count) { 551 usleep_range(1000, 1500); 552 dev_dbg(component->dev, "Flush DAC (retry:%u)\n", i); 553 regmap_read(rt1015->regmap, RT1015_CLK_DET, &val); 554 if (val & 0x800) 555 break; 556 i++; 557 } 558 559 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597); 560 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7); 561 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028); 562 563 if (val & 0x800) 564 dev_dbg(component->dev, "Flush DAC completed.\n"); 565 else 566 dev_warn(component->dev, "Fail to flush DAC data.\n"); 567} 568 569static const struct snd_kcontrol_new rt1015_snd_controls[] = { 570 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT, 571 127, 0, dac_vol_tlv), 572 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3, 573 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1), 574 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum, 575 rt1015_boost_mode_get, rt1015_boost_mode_put), 576 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel), 577 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0, 578 rt1015_bypass_boost_get, rt1015_bypass_boost_put), 579}; 580 581static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 582 struct snd_soc_dapm_widget *sink) 583{ 584 struct snd_soc_component *component = 585 snd_soc_dapm_to_component(source->dapm); 586 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 587 588 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL) 589 return 1; 590 else 591 return 0; 592} 593 594static int r1015_dac_event(struct snd_soc_dapm_widget *w, 595 struct snd_kcontrol *kcontrol, int event) 596{ 597 struct snd_soc_component *component = 598 snd_soc_dapm_to_component(w->dapm); 599 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 600 601 switch (event) { 602 case SND_SOC_DAPM_PRE_PMU: 603 rt1015->dac_is_used = 1; 604 if (rt1015->bypass_boost == RT1015_Enable_Boost) { 605 snd_soc_component_write(component, 606 RT1015_SYS_RST1, 0x05f7); 607 snd_soc_component_write(component, 608 RT1015_GAT_BOOST, 0xacfe); 609 snd_soc_component_write(component, 610 RT1015_PWR9, 0xaa00); 611 snd_soc_component_write(component, 612 RT1015_GAT_BOOST, 0xecfe); 613 } else { 614 snd_soc_component_write(component, 615 RT1015_SYS_RST1, 0x05f7); 616 snd_soc_component_write(component, 617 RT1015_PWR_STATE_CTRL, 0x026e); 618 } 619 break; 620 621 case SND_SOC_DAPM_POST_PMU: 622 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8); 623 break; 624 625 case SND_SOC_DAPM_POST_PMD: 626 if (rt1015->bypass_boost == RT1015_Enable_Boost) { 627 snd_soc_component_write(component, 628 RT1015_PWR9, 0xa800); 629 snd_soc_component_write(component, 630 RT1015_SYS_RST1, 0x05f5); 631 } else { 632 snd_soc_component_write(component, 633 RT1015_PWR_STATE_CTRL, 0x0268); 634 snd_soc_component_write(component, 635 RT1015_SYS_RST1, 0x05f5); 636 } 637 rt1015->dac_is_used = 0; 638 639 cancel_delayed_work_sync(&rt1015->flush_work); 640 break; 641 642 default: 643 break; 644 } 645 return 0; 646} 647 648static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w, 649 struct snd_kcontrol *kcontrol, int event) 650{ 651 struct snd_soc_component *component = 652 snd_soc_dapm_to_component(w->dapm); 653 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 654 655 switch (event) { 656 case SND_SOC_DAPM_POST_PMU: 657 if (rt1015->hw_config == RT1015_HW_28) 658 schedule_delayed_work(&rt1015->flush_work, msecs_to_jiffies(10)); 659 msleep(rt1015->pdata.power_up_delay_ms); 660 break; 661 default: 662 break; 663 } 664 return 0; 665} 666 667static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = { 668 SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0, 669 NULL, 0), 670 SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT, 671 0, NULL, 0), 672 SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0, 673 NULL, 0), 674 SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0, 675 NULL, 0), 676 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0, 677 NULL, 0), 678 SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0, 679 NULL, 0), 680 SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0, 681 NULL, 0), 682 SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL, 683 0), 684 SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0, 685 NULL, 0), 686 SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL, 687 0), 688 SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0, 689 NULL, 0), 690 SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL, 691 0), 692 SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0, 693 NULL, 0), 694 695 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 696 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0, 697 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 698 SND_SOC_DAPM_POST_PMD), 699 700 SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0, 701 rt1015_amp_drv_event, SND_SOC_DAPM_POST_PMU), 702 SND_SOC_DAPM_OUTPUT("SPO"), 703}; 704 705static const struct snd_soc_dapm_route rt1015_dapm_routes[] = { 706 { "DAC", NULL, "AIFRX" }, 707 { "DAC", NULL, "LDO2" }, 708 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll}, 709 { "DAC", NULL, "INT RC CLK" }, 710 { "DAC", NULL, "ISENSE" }, 711 { "DAC", NULL, "VSENSE" }, 712 { "DAC", NULL, "BG1 BG2" }, 713 { "DAC", NULL, "MBIAS BG" }, 714 { "DAC", NULL, "VBAT" }, 715 { "DAC", NULL, "MBIAS" }, 716 { "DAC", NULL, "ADCV" }, 717 { "DAC", NULL, "MIXERV" }, 718 { "DAC", NULL, "SUMV" }, 719 { "DAC", NULL, "VREFLV" }, 720 { "Amp Drv", NULL, "DAC" }, 721 { "SPO", NULL, "Amp Drv" }, 722}; 723 724static int rt1015_hw_params(struct snd_pcm_substream *substream, 725 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 726{ 727 struct snd_soc_component *component = dai->component; 728 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 729 int pre_div, bclk_ms, frame_size; 730 unsigned int val_len = 0; 731 732 rt1015->lrck = params_rate(params); 733 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck); 734 if (pre_div < 0) { 735 dev_err(component->dev, "Unsupported clock rate\n"); 736 return -EINVAL; 737 } 738 739 frame_size = snd_soc_params_to_frame_size(params); 740 if (frame_size < 0) { 741 dev_err(component->dev, "Unsupported frame size: %d\n", 742 frame_size); 743 return -EINVAL; 744 } 745 746 bclk_ms = frame_size > 32; 747 rt1015->bclk = rt1015->lrck * (32 << bclk_ms); 748 749 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 750 bclk_ms, pre_div, dai->id); 751 752 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 753 rt1015->lrck, pre_div, dai->id); 754 755 switch (params_width(params)) { 756 case 16: 757 break; 758 case 20: 759 val_len = RT1015_I2S_DL_20; 760 break; 761 case 24: 762 val_len = RT1015_I2S_DL_24; 763 break; 764 case 8: 765 val_len = RT1015_I2S_DL_8; 766 break; 767 default: 768 return -EINVAL; 769 } 770 771 snd_soc_component_update_bits(component, RT1015_TDM_MASTER, 772 RT1015_I2S_DL_MASK, val_len); 773 snd_soc_component_update_bits(component, RT1015_CLK2, 774 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT); 775 776 return 0; 777} 778 779static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 780{ 781 struct snd_soc_component *component = dai->component; 782 unsigned int reg_val = 0, reg_val2 = 0; 783 784 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 785 case SND_SOC_DAIFMT_CBM_CFM: 786 reg_val |= RT1015_TCON_TDM_MS_M; 787 break; 788 case SND_SOC_DAIFMT_CBS_CFS: 789 reg_val |= RT1015_TCON_TDM_MS_S; 790 break; 791 default: 792 return -EINVAL; 793 } 794 795 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 796 case SND_SOC_DAIFMT_NB_NF: 797 break; 798 case SND_SOC_DAIFMT_IB_NF: 799 reg_val2 |= RT1015_TDM_INV_BCLK; 800 break; 801 default: 802 return -EINVAL; 803 } 804 805 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 806 case SND_SOC_DAIFMT_I2S: 807 break; 808 809 case SND_SOC_DAIFMT_LEFT_J: 810 reg_val |= RT1015_I2S_M_DF_LEFT; 811 break; 812 813 case SND_SOC_DAIFMT_DSP_A: 814 reg_val |= RT1015_I2S_M_DF_PCM_A; 815 break; 816 817 case SND_SOC_DAIFMT_DSP_B: 818 reg_val |= RT1015_I2S_M_DF_PCM_B; 819 break; 820 821 default: 822 return -EINVAL; 823 } 824 825 snd_soc_component_update_bits(component, RT1015_TDM_MASTER, 826 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK, 827 reg_val); 828 snd_soc_component_update_bits(component, RT1015_TDM1_1, 829 RT1015_TDM_INV_BCLK_MASK, reg_val2); 830 831 return 0; 832} 833 834static int rt1015_set_component_sysclk(struct snd_soc_component *component, 835 int clk_id, int source, unsigned int freq, int dir) 836{ 837 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 838 unsigned int reg_val = 0; 839 840 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src) 841 return 0; 842 843 switch (clk_id) { 844 case RT1015_SCLK_S_MCLK: 845 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK; 846 break; 847 848 case RT1015_SCLK_S_PLL: 849 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL; 850 break; 851 852 default: 853 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 854 return -EINVAL; 855 } 856 857 rt1015->sysclk = freq; 858 rt1015->sysclk_src = clk_id; 859 860 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 861 freq, clk_id); 862 863 snd_soc_component_update_bits(component, RT1015_CLK2, 864 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val); 865 866 return 0; 867} 868 869static int rt1015_set_component_pll(struct snd_soc_component *component, 870 int pll_id, int source, unsigned int freq_in, 871 unsigned int freq_out) 872{ 873 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 874 struct rl6231_pll_code pll_code; 875 int ret; 876 877 if (!freq_in || !freq_out) { 878 dev_dbg(component->dev, "PLL disabled\n"); 879 880 rt1015->pll_in = 0; 881 rt1015->pll_out = 0; 882 883 return 0; 884 } 885 886 if (source == rt1015->pll_src && freq_in == rt1015->pll_in && 887 freq_out == rt1015->pll_out) 888 return 0; 889 890 if (source == RT1015_PLL_S_BCLK) { 891 if (rt1015->bclk_ratio == 0) { 892 dev_err(component->dev, 893 "Can not support bclk ratio as 0.\n"); 894 return -EINVAL; 895 } 896 } 897 898 switch (source) { 899 case RT1015_PLL_S_MCLK: 900 snd_soc_component_update_bits(component, RT1015_CLK2, 901 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2); 902 break; 903 904 case RT1015_PLL_S_BCLK: 905 snd_soc_component_update_bits(component, RT1015_CLK2, 906 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK); 907 break; 908 909 default: 910 dev_err(component->dev, "Unknown PLL Source %d\n", source); 911 return -EINVAL; 912 } 913 914 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 915 if (ret < 0) { 916 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 917 return ret; 918 } 919 920 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 921 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 922 pll_code.n_code, pll_code.k_code); 923 924 snd_soc_component_write(component, RT1015_PLL1, 925 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT | 926 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code); 927 snd_soc_component_write(component, RT1015_PLL2, 928 pll_code.k_code); 929 930 rt1015->pll_in = freq_in; 931 rt1015->pll_out = freq_out; 932 rt1015->pll_src = source; 933 934 return 0; 935} 936 937static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 938{ 939 struct snd_soc_component *component = dai->component; 940 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 941 942 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); 943 944 rt1015->bclk_ratio = ratio; 945 946 if (ratio == 50) { 947 dev_dbg(component->dev, "Unsupport bclk ratio\n"); 948 return -EINVAL; 949 } 950 951 return 0; 952} 953 954static int rt1015_probe(struct snd_soc_component *component) 955{ 956 struct rt1015_priv *rt1015 = 957 snd_soc_component_get_drvdata(component); 958 959 rt1015->component = component; 960 rt1015->bclk_ratio = 0; 961 rt1015->cali_done = 0; 962 snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c); 963 964 INIT_DELAYED_WORK(&rt1015->flush_work, rt1015_flush_work); 965 966 return 0; 967} 968 969static void rt1015_remove(struct snd_soc_component *component) 970{ 971 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 972 973 cancel_delayed_work_sync(&rt1015->flush_work); 974 regmap_write(rt1015->regmap, RT1015_RESET, 0); 975} 976 977#define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000 978#define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 979 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 980 981static struct snd_soc_dai_ops rt1015_aif_dai_ops = { 982 .hw_params = rt1015_hw_params, 983 .set_fmt = rt1015_set_dai_fmt, 984 .set_bclk_ratio = rt1015_set_bclk_ratio, 985}; 986 987static struct snd_soc_dai_driver rt1015_dai[] = { 988 { 989 .name = "rt1015-aif", 990 .id = 0, 991 .playback = { 992 .stream_name = "AIF Playback", 993 .channels_min = 1, 994 .channels_max = 4, 995 .rates = RT1015_STEREO_RATES, 996 .formats = RT1015_FORMATS, 997 }, 998 .ops = &rt1015_aif_dai_ops, 999 } 1000}; 1001 1002#ifdef CONFIG_PM 1003static int rt1015_suspend(struct snd_soc_component *component) 1004{ 1005 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 1006 1007 regcache_cache_only(rt1015->regmap, true); 1008 regcache_mark_dirty(rt1015->regmap); 1009 1010 return 0; 1011} 1012 1013static int rt1015_resume(struct snd_soc_component *component) 1014{ 1015 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component); 1016 1017 regcache_cache_only(rt1015->regmap, false); 1018 regcache_sync(rt1015->regmap); 1019 return 0; 1020} 1021#else 1022#define rt1015_suspend NULL 1023#define rt1015_resume NULL 1024#endif 1025 1026static const struct snd_soc_component_driver soc_component_dev_rt1015 = { 1027 .probe = rt1015_probe, 1028 .remove = rt1015_remove, 1029 .suspend = rt1015_suspend, 1030 .resume = rt1015_resume, 1031 .controls = rt1015_snd_controls, 1032 .num_controls = ARRAY_SIZE(rt1015_snd_controls), 1033 .dapm_widgets = rt1015_dapm_widgets, 1034 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets), 1035 .dapm_routes = rt1015_dapm_routes, 1036 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes), 1037 .set_sysclk = rt1015_set_component_sysclk, 1038 .set_pll = rt1015_set_component_pll, 1039 .use_pmdown_time = 1, 1040 .endianness = 1, 1041 .non_legacy_dai_naming = 1, 1042}; 1043 1044static const struct regmap_config rt1015_regmap = { 1045 .reg_bits = 16, 1046 .val_bits = 16, 1047 .max_register = RT1015_S_BST_TIMING_INTER36, 1048 .volatile_reg = rt1015_volatile_register, 1049 .readable_reg = rt1015_readable_register, 1050 .cache_type = REGCACHE_RBTREE, 1051 .reg_defaults = rt1015_reg, 1052 .num_reg_defaults = ARRAY_SIZE(rt1015_reg), 1053}; 1054 1055static const struct i2c_device_id rt1015_i2c_id[] = { 1056 { "rt1015", 0 }, 1057 { } 1058}; 1059MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id); 1060 1061#if defined(CONFIG_OF) 1062static const struct of_device_id rt1015_of_match[] = { 1063 { .compatible = "realtek,rt1015", }, 1064 {}, 1065}; 1066MODULE_DEVICE_TABLE(of, rt1015_of_match); 1067#endif 1068 1069#ifdef CONFIG_ACPI 1070static struct acpi_device_id rt1015_acpi_match[] = { 1071 {"10EC1015", 0,}, 1072 {}, 1073}; 1074MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match); 1075#endif 1076 1077static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev) 1078{ 1079 device_property_read_u32(dev, "realtek,power-up-delay-ms", 1080 &rt1015->pdata.power_up_delay_ms); 1081} 1082 1083static int rt1015_i2c_probe(struct i2c_client *i2c, 1084 const struct i2c_device_id *id) 1085{ 1086 struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev); 1087 struct rt1015_priv *rt1015; 1088 int ret; 1089 unsigned int val; 1090 1091 rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv), 1092 GFP_KERNEL); 1093 if (rt1015 == NULL) 1094 return -ENOMEM; 1095 1096 i2c_set_clientdata(i2c, rt1015); 1097 1098 rt1015->pdata = i2s_default_platform_data; 1099 1100 if (pdata) 1101 rt1015->pdata = *pdata; 1102 else 1103 rt1015_parse_dt(rt1015, &i2c->dev); 1104 1105 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap); 1106 if (IS_ERR(rt1015->regmap)) { 1107 ret = PTR_ERR(rt1015->regmap); 1108 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1109 ret); 1110 return ret; 1111 } 1112 1113 rt1015->hw_config = (i2c->addr == 0x29) ? RT1015_HW_29 : RT1015_HW_28; 1114 1115 regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val); 1116 if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) { 1117 dev_err(&i2c->dev, 1118 "Device with ID register %x is not rt1015\n", val); 1119 return -ENODEV; 1120 } 1121 1122 return devm_snd_soc_register_component(&i2c->dev, 1123 &soc_component_dev_rt1015, 1124 rt1015_dai, ARRAY_SIZE(rt1015_dai)); 1125} 1126 1127static void rt1015_i2c_shutdown(struct i2c_client *client) 1128{ 1129 struct rt1015_priv *rt1015 = i2c_get_clientdata(client); 1130 1131 regmap_write(rt1015->regmap, RT1015_RESET, 0); 1132} 1133 1134static struct i2c_driver rt1015_i2c_driver = { 1135 .driver = { 1136 .name = "rt1015", 1137 .of_match_table = of_match_ptr(rt1015_of_match), 1138 .acpi_match_table = ACPI_PTR(rt1015_acpi_match), 1139 }, 1140 .probe = rt1015_i2c_probe, 1141 .shutdown = rt1015_i2c_shutdown, 1142 .id_table = rt1015_i2c_id, 1143}; 1144module_i2c_driver(rt1015_i2c_driver); 1145 1146MODULE_DESCRIPTION("ASoC RT1015 driver"); 1147MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1148MODULE_LICENSE("GPL v2"); 1149