1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * NAU8825 ALSA SoC audio driver 4 * 5 * Copyright 2015 Google Inc. 6 * Author: Anatol Pomozov <anatol.pomozov@chrominium.org> 7 */ 8 9#ifndef __NAU8825_H__ 10#define __NAU8825_H__ 11 12#define NAU8825_REG_RESET 0x00 13#define NAU8825_REG_ENA_CTRL 0x01 14#define NAU8825_REG_IIC_ADDR_SET 0x02 15#define NAU8825_REG_CLK_DIVIDER 0x03 16#define NAU8825_REG_FLL1 0x04 17#define NAU8825_REG_FLL2 0x05 18#define NAU8825_REG_FLL3 0x06 19#define NAU8825_REG_FLL4 0x07 20#define NAU8825_REG_FLL5 0x08 21#define NAU8825_REG_FLL6 0x09 22#define NAU8825_REG_FLL_VCO_RSV 0x0a 23#define NAU8825_REG_HSD_CTRL 0x0c 24#define NAU8825_REG_JACK_DET_CTRL 0x0d 25#define NAU8825_REG_INTERRUPT_MASK 0x0f 26#define NAU8825_REG_IRQ_STATUS 0x10 27#define NAU8825_REG_INT_CLR_KEY_STATUS 0x11 28#define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12 29#define NAU8825_REG_SAR_CTRL 0x13 30#define NAU8825_REG_KEYDET_CTRL 0x14 31#define NAU8825_REG_VDET_THRESHOLD_1 0x15 32#define NAU8825_REG_VDET_THRESHOLD_2 0x16 33#define NAU8825_REG_VDET_THRESHOLD_3 0x17 34#define NAU8825_REG_VDET_THRESHOLD_4 0x18 35#define NAU8825_REG_GPIO34_CTRL 0x19 36#define NAU8825_REG_GPIO12_CTRL 0x1a 37#define NAU8825_REG_TDM_CTRL 0x1b 38#define NAU8825_REG_I2S_PCM_CTRL1 0x1c 39#define NAU8825_REG_I2S_PCM_CTRL2 0x1d 40#define NAU8825_REG_LEFT_TIME_SLOT 0x1e 41#define NAU8825_REG_RIGHT_TIME_SLOT 0x1f 42#define NAU8825_REG_BIQ_CTRL 0x20 43#define NAU8825_REG_BIQ_COF1 0x21 44#define NAU8825_REG_BIQ_COF2 0x22 45#define NAU8825_REG_BIQ_COF3 0x23 46#define NAU8825_REG_BIQ_COF4 0x24 47#define NAU8825_REG_BIQ_COF5 0x25 48#define NAU8825_REG_BIQ_COF6 0x26 49#define NAU8825_REG_BIQ_COF7 0x27 50#define NAU8825_REG_BIQ_COF8 0x28 51#define NAU8825_REG_BIQ_COF9 0x29 52#define NAU8825_REG_BIQ_COF10 0x2a 53#define NAU8825_REG_ADC_RATE 0x2b 54#define NAU8825_REG_DAC_CTRL1 0x2c 55#define NAU8825_REG_DAC_CTRL2 0x2d 56#define NAU8825_REG_DAC_DGAIN_CTRL 0x2f 57#define NAU8825_REG_ADC_DGAIN_CTRL 0x30 58#define NAU8825_REG_MUTE_CTRL 0x31 59#define NAU8825_REG_HSVOL_CTRL 0x32 60#define NAU8825_REG_DACL_CTRL 0x33 61#define NAU8825_REG_DACR_CTRL 0x34 62#define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38 63#define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39 64#define NAU8825_REG_ADC_DRC_SLOPES 0x3a 65#define NAU8825_REG_ADC_DRC_ATKDCY 0x3b 66#define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45 67#define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46 68#define NAU8825_REG_DAC_DRC_SLOPES 0x47 69#define NAU8825_REG_DAC_DRC_ATKDCY 0x48 70#define NAU8825_REG_IMM_MODE_CTRL 0x4c 71#define NAU8825_REG_IMM_RMS_L 0x4d 72#define NAU8825_REG_IMM_RMS_R 0x4e 73#define NAU8825_REG_CLASSG_CTRL 0x50 74#define NAU8825_REG_OPT_EFUSE_CTRL 0x51 75#define NAU8825_REG_MISC_CTRL 0x55 76#define NAU8825_REG_I2C_DEVICE_ID 0x58 77#define NAU8825_REG_SARDOUT_RAM_STATUS 0x59 78#define NAU8825_REG_BIAS_ADJ 0x66 79#define NAU8825_REG_TRIM_SETTINGS 0x68 80#define NAU8825_REG_ANALOG_CONTROL_1 0x69 81#define NAU8825_REG_ANALOG_CONTROL_2 0x6a 82#define NAU8825_REG_ANALOG_ADC_1 0x71 83#define NAU8825_REG_ANALOG_ADC_2 0x72 84#define NAU8825_REG_RDAC 0x73 85#define NAU8825_REG_MIC_BIAS 0x74 86#define NAU8825_REG_BOOST 0x76 87#define NAU8825_REG_FEPGA 0x77 88#define NAU8825_REG_POWER_UP_CONTROL 0x7f 89#define NAU8825_REG_CHARGE_PUMP 0x80 90#define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81 91#define NAU8825_REG_GENERAL_STATUS 0x82 92#define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS 93/* 16-bit control register address, and 16-bits control register data */ 94#define NAU8825_REG_ADDR_LEN 16 95#define NAU8825_REG_DATA_LEN 16 96 97/* ENA_CTRL (0x1) */ 98#define NAU8825_ENABLE_DACR_SFT 10 99#define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT) 100#define NAU8825_ENABLE_DACL_SFT 9 101#define NAU8825_ENABLE_DACL (1 << NAU8825_ENABLE_DACL_SFT) 102#define NAU8825_ENABLE_ADC_SFT 8 103#define NAU8825_ENABLE_ADC (1 << NAU8825_ENABLE_ADC_SFT) 104#define NAU8825_ENABLE_ADC_CLK_SFT 7 105#define NAU8825_ENABLE_ADC_CLK (1 << NAU8825_ENABLE_ADC_CLK_SFT) 106#define NAU8825_ENABLE_DAC_CLK_SFT 6 107#define NAU8825_ENABLE_DAC_CLK (1 << NAU8825_ENABLE_DAC_CLK_SFT) 108#define NAU8825_ENABLE_SAR_SFT 1 109 110/* CLK_DIVIDER (0x3) */ 111#define NAU8825_CLK_SRC_SFT 15 112#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) 113#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) 114#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) 115#define NAU8825_CLK_ADC_SRC_SFT 6 116#define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT) 117#define NAU8825_CLK_DAC_SRC_SFT 4 118#define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT) 119#define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) 120 121/* FLL1 (0x04) */ 122#define NAU8825_ICTRL_LATCH_SFT 10 123#define NAU8825_ICTRL_LATCH_MASK (0x7 << NAU8825_ICTRL_LATCH_SFT) 124#define NAU8825_FLL_RATIO_MASK (0x7f << 0) 125 126/* FLL3 (0x06) */ 127#define NAU8825_GAIN_ERR_SFT 12 128#define NAU8825_GAIN_ERR_MASK (0xf << NAU8825_GAIN_ERR_SFT) 129#define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) 130#define NAU8825_FLL_CLK_SRC_SFT 10 131#define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT) 132#define NAU8825_FLL_CLK_SRC_MCLK (0 << NAU8825_FLL_CLK_SRC_SFT) 133#define NAU8825_FLL_CLK_SRC_BLK (0x2 << NAU8825_FLL_CLK_SRC_SFT) 134#define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT) 135 136/* FLL4 (0x07) */ 137#define NAU8825_FLL_REF_DIV_SFT 10 138#define NAU8825_FLL_REF_DIV_MASK (0x3 << NAU8825_FLL_REF_DIV_SFT) 139 140/* FLL5 (0x08) */ 141#define NAU8825_FLL_PDB_DAC_EN (0x1 << 15) 142#define NAU8825_FLL_LOOP_FTR_EN (0x1 << 14) 143#define NAU8825_FLL_CLK_SW_MASK (0x1 << 13) 144#define NAU8825_FLL_CLK_SW_N2 (0x1 << 13) 145#define NAU8825_FLL_CLK_SW_REF (0x0 << 13) 146#define NAU8825_FLL_FTR_SW_MASK (0x1 << 12) 147#define NAU8825_FLL_FTR_SW_ACCU (0x1 << 12) 148#define NAU8825_FLL_FTR_SW_FILTER (0x0 << 12) 149 150/* FLL6 (0x9) */ 151#define NAU8825_DCO_EN (0x1 << 15) 152#define NAU8825_SDM_EN (0x1 << 14) 153#define NAU8825_CUTOFF500 (0x1 << 13) 154 155/* HSD_CTRL (0xc) */ 156#define NAU8825_HSD_AUTO_MODE (1 << 6) 157/* 0 - open, 1 - short to GND */ 158#define NAU8825_SPKR_DWN1R (1 << 1) 159#define NAU8825_SPKR_DWN1L (1 << 0) 160 161/* JACK_DET_CTRL (0xd) */ 162#define NAU8825_JACK_DET_RESTART (1 << 9) 163#define NAU8825_JACK_DET_DB_BYPASS (1 << 8) 164#define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5 165#define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT) 166#define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2 167#define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT) 168#define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */ 169 170/* INTERRUPT_MASK (0xf) */ 171#define NAU8825_IRQ_PIN_PULLUP (1 << 14) 172#define NAU8825_IRQ_PIN_PULL_EN (1 << 13) 173#define NAU8825_IRQ_OUTPUT_EN (1 << 11) 174#define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10) 175#define NAU8825_IRQ_RMS_EN (1 << 8) 176#define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7) 177#define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5) 178#define NAU8825_IRQ_EJECT_EN (1 << 2) 179#define NAU8825_IRQ_INSERT_EN (1 << 0) 180 181/* IRQ_STATUS (0x10) */ 182#define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10) 183#define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9) 184#define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8) 185#define NAU8825_KEY_IRQ_MASK (0x7 << 5) 186#define NAU8825_KEY_RELEASE_IRQ (1 << 7) 187#define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6) 188#define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5) 189#define NAU8825_MIC_DETECTION_IRQ (1 << 4) 190#define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2) 191#define NAU8825_JACK_EJECTION_DETECTED (1 << 2) 192#define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0) 193#define NAU8825_JACK_INSERTION_DETECTED (1 << 0) 194 195/* INTERRUPT_DIS_CTRL (0x12) */ 196#define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10) 197#define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7) 198#define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5) 199#define NAU8825_IRQ_EJECT_DIS (1 << 2) 200#define NAU8825_IRQ_INSERT_DIS (1 << 0) 201 202/* SAR_CTRL (0x13) */ 203#define NAU8825_SAR_ADC_EN_SFT 12 204#define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT) 205#define NAU8825_SAR_INPUT_MASK (1 << 11) 206#define NAU8825_SAR_INPUT_JKSLV (1 << 11) 207#define NAU8825_SAR_INPUT_JKR2 (0 << 11) 208#define NAU8825_SAR_TRACKING_GAIN_SFT 8 209#define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT) 210#define NAU8825_SAR_COMPARE_TIME_SFT 2 211#define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2) 212#define NAU8825_SAR_SAMPLING_TIME_SFT 0 213#define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0) 214 215/* KEYDET_CTRL (0x14) */ 216#define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12 217#define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT) 218#define NAU8825_KEYDET_LEVELS_NR_SFT 8 219#define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8) 220#define NAU8825_KEYDET_HYSTERESIS_SFT 0 221#define NAU8825_KEYDET_HYSTERESIS_MASK 0xf 222 223/* GPIO12_CTRL (0x1a) */ 224#define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */ 225#define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */ 226#define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */ 227 228/* I2S_PCM_CTRL1 (0x1c) */ 229#define NAU8825_I2S_BP_SFT 7 230#define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT) 231#define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT) 232#define NAU8825_I2S_PCMB_SFT 6 233#define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT) 234#define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT) 235#define NAU8825_I2S_DL_SFT 2 236#define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT) 237#define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT) 238#define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT) 239#define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT) 240#define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT) 241#define NAU8825_I2S_DF_SFT 0 242#define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT) 243#define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT) 244#define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT) 245#define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT) 246#define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT) 247 248/* I2S_PCM_CTRL2 (0x1d) */ 249#define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */ 250#define NAU8825_I2S_LRC_DIV_SFT 12 251#define NAU8825_I2S_LRC_DIV_MASK (0x3 << NAU8825_I2S_LRC_DIV_SFT) 252#define NAU8825_I2S_MS_SFT 3 253#define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT) 254#define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT) 255#define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT) 256#define NAU8825_I2S_BLK_DIV_MASK 0x7 257 258/* LEFT_TIME_SLOT (0x1e) */ 259#define NAU8825_FS_ERR_CMP_SEL_SFT 14 260#define NAU8825_FS_ERR_CMP_SEL_MASK (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT) 261#define NAU8825_DIS_FS_SHORT_DET (1 << 13) 262 263/* BIQ_CTRL (0x20) */ 264#define NAU8825_BIQ_WRT_SFT 4 265#define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT) 266#define NAU8825_BIQ_PATH_SFT 0 267#define NAU8825_BIQ_PATH_MASK (1 << NAU8825_BIQ_PATH_SFT) 268#define NAU8825_BIQ_PATH_ADC (0 << NAU8825_BIQ_PATH_SFT) 269#define NAU8825_BIQ_PATH_DAC (1 << NAU8825_BIQ_PATH_SFT) 270 271/* ADC_RATE (0x2b) */ 272#define NAU8825_ADC_SINC4_SFT 4 273#define NAU8825_ADC_SINC4_EN (1 << NAU8825_ADC_SINC4_SFT) 274#define NAU8825_ADC_SYNC_DOWN_SFT 0 275#define NAU8825_ADC_SYNC_DOWN_MASK 0x3 276#define NAU8825_ADC_SYNC_DOWN_32 0 277#define NAU8825_ADC_SYNC_DOWN_64 1 278#define NAU8825_ADC_SYNC_DOWN_128 2 279#define NAU8825_ADC_SYNC_DOWN_256 3 280 281/* DAC_CTRL1 (0x2c) */ 282#define NAU8825_DAC_CLIP_OFF (1 << 7) 283#define NAU8825_DAC_OVERSAMPLE_SFT 0 284#define NAU8825_DAC_OVERSAMPLE_MASK 0x7 285#define NAU8825_DAC_OVERSAMPLE_64 0 286#define NAU8825_DAC_OVERSAMPLE_256 1 287#define NAU8825_DAC_OVERSAMPLE_128 2 288#define NAU8825_DAC_OVERSAMPLE_32 4 289 290/* ADC_DGAIN_CTRL (0x30) */ 291#define NAU8825_ADC_DIG_VOL_MASK 0xff 292 293/* MUTE_CTRL (0x31) */ 294#define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9) 295#define NAU8825_DAC_SOFT_MUTE (1 << 9) 296 297/* HSVOL_CTRL (0x32) */ 298#define NAU8825_HP_MUTE (1 << 15) 299#define NAU8825_HP_MUTE_AUTO (1 << 14) 300#define NAU8825_HPL_MUTE (1 << 13) 301#define NAU8825_HPR_MUTE (1 << 12) 302#define NAU8825_HPL_VOL_SFT 6 303#define NAU8825_HPL_VOL_MASK (0x3f << NAU8825_HPL_VOL_SFT) 304#define NAU8825_HPR_VOL_SFT 0 305#define NAU8825_HPR_VOL_MASK (0x3f << NAU8825_HPR_VOL_SFT) 306#define NAU8825_HP_VOL_MIN 0x36 307 308/* DACL_CTRL (0x33) */ 309#define NAU8825_DACL_CH_SEL_SFT 9 310#define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT) 311#define NAU8825_DACL_CH_SEL_L (0x0 << NAU8825_DACL_CH_SEL_SFT) 312#define NAU8825_DACL_CH_SEL_R (0x1 << NAU8825_DACL_CH_SEL_SFT) 313#define NAU8825_DACL_CH_VOL_MASK 0xff 314 315/* DACR_CTRL (0x34) */ 316#define NAU8825_DACR_CH_SEL_SFT 9 317#define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT) 318#define NAU8825_DACR_CH_SEL_L (0x0 << NAU8825_DACR_CH_SEL_SFT) 319#define NAU8825_DACR_CH_SEL_R (0x1 << NAU8825_DACR_CH_SEL_SFT) 320#define NAU8825_DACR_CH_VOL_MASK 0xff 321 322/* IMM_MODE_CTRL (0x4C) */ 323#define NAU8825_IMM_THD_SFT 8 324#define NAU8825_IMM_THD_MASK (0x3f << NAU8825_IMM_THD_SFT) 325#define NAU8825_IMM_GEN_VOL_SFT 6 326#define NAU8825_IMM_GEN_VOL_MASK (0x3 << NAU8825_IMM_GEN_VOL_SFT) 327#define NAU8825_IMM_GEN_VOL_1_2nd (0x0 << NAU8825_IMM_GEN_VOL_SFT) 328#define NAU8825_IMM_GEN_VOL_1_4th (0x1 << NAU8825_IMM_GEN_VOL_SFT) 329#define NAU8825_IMM_GEN_VOL_1_8th (0x2 << NAU8825_IMM_GEN_VOL_SFT) 330#define NAU8825_IMM_GEN_VOL_1_16th (0x3 << NAU8825_IMM_GEN_VOL_SFT) 331 332#define NAU8825_IMM_CYC_SFT 4 333#define NAU8825_IMM_CYC_MASK (0x3 << NAU8825_IMM_CYC_SFT) 334#define NAU8825_IMM_CYC_1024 (0x0 << NAU8825_IMM_CYC_SFT) 335#define NAU8825_IMM_CYC_2048 (0x1 << NAU8825_IMM_CYC_SFT) 336#define NAU8825_IMM_CYC_4096 (0x2 << NAU8825_IMM_CYC_SFT) 337#define NAU8825_IMM_CYC_8192 (0x3 << NAU8825_IMM_CYC_SFT) 338#define NAU8825_IMM_EN (1 << 3) 339#define NAU8825_IMM_DAC_SRC_MASK 0x7 340#define NAU8825_IMM_DAC_SRC_BIQ 0x0 341#define NAU8825_IMM_DAC_SRC_DRC 0x1 342#define NAU8825_IMM_DAC_SRC_MIX 0x2 343#define NAU8825_IMM_DAC_SRC_SIN 0x3 344 345/* CLASSG_CTRL (0x50) */ 346#define NAU8825_CLASSG_TIMER_SFT 8 347#define NAU8825_CLASSG_TIMER_MASK (0x3f << NAU8825_CLASSG_TIMER_SFT) 348#define NAU8825_CLASSG_TIMER_1ms (0x1 << NAU8825_CLASSG_TIMER_SFT) 349#define NAU8825_CLASSG_TIMER_2ms (0x2 << NAU8825_CLASSG_TIMER_SFT) 350#define NAU8825_CLASSG_TIMER_8ms (0x4 << NAU8825_CLASSG_TIMER_SFT) 351#define NAU8825_CLASSG_TIMER_16ms (0x8 << NAU8825_CLASSG_TIMER_SFT) 352#define NAU8825_CLASSG_TIMER_32ms (0x10 << NAU8825_CLASSG_TIMER_SFT) 353#define NAU8825_CLASSG_TIMER_64ms (0x20 << NAU8825_CLASSG_TIMER_SFT) 354#define NAU8825_CLASSG_LDAC_EN (0x1 << 2) 355#define NAU8825_CLASSG_RDAC_EN (0x1 << 1) 356#define NAU8825_CLASSG_EN (1 << 0) 357 358/* I2C_DEVICE_ID (0x58) */ 359#define NAU8825_GPIO2JD1 (1 << 7) 360#define NAU8825_SOFTWARE_ID_MASK 0x3 361#define NAU8825_SOFTWARE_ID_NAU8825 0x0 362 363/* BIAS_ADJ (0x66) */ 364#define NAU8825_BIAS_HPR_IMP (1 << 15) 365#define NAU8825_BIAS_HPL_IMP (1 << 14) 366#define NAU8825_BIAS_TESTDAC_SFT 8 367#define NAU8825_BIAS_TESTDAC_EN (0x3 << NAU8825_BIAS_TESTDAC_SFT) 368#define NAU8825_BIAS_TESTDACR_EN (0x2 << NAU8825_BIAS_TESTDAC_SFT) 369#define NAU8825_BIAS_TESTDACL_EN (0x1 << NAU8825_BIAS_TESTDAC_SFT) 370#define NAU8825_BIAS_VMID (1 << 6) 371#define NAU8825_BIAS_VMID_SEL_SFT 4 372#define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT) 373 374/* ANALOG_CONTROL_2 (0x6a) */ 375#define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12) 376#define NAU8825_DAC_CAPACITOR_MSB (1 << 1) 377#define NAU8825_DAC_CAPACITOR_LSB (1 << 0) 378 379/* ANALOG_ADC_2 (0x72) */ 380#define NAU8825_ADC_VREFSEL_MASK (0x3 << 8) 381#define NAU8825_ADC_VREFSEL_ANALOG (0 << 8) 382#define NAU8825_ADC_VREFSEL_VMID (1 << 8) 383#define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8) 384#define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8) 385#define NAU8825_POWERUP_ADCL (1 << 6) 386 387/* RDAC (0x73) */ 388#define NAU8825_RDAC_FS_BCLK_ENB (1 << 15) 389#define NAU8825_RDAC_EN_SFT 12 390#define NAU8825_RDAC_EN (0x3 << NAU8825_RDAC_EN_SFT) 391#define NAU8825_RDAC_CLK_EN_SFT 8 392#define NAU8825_RDAC_CLK_EN (0x3 << NAU8825_RDAC_CLK_EN_SFT) 393#define NAU8825_RDAC_CLK_DELAY_SFT 4 394#define NAU8825_RDAC_CLK_DELAY_MASK (0x7 << NAU8825_RDAC_CLK_DELAY_SFT) 395#define NAU8825_RDAC_VREF_SFT 2 396#define NAU8825_RDAC_VREF_MASK (0x3 << NAU8825_RDAC_VREF_SFT) 397 398/* MIC_BIAS (0x74) */ 399#define NAU8825_MICBIAS_JKSLV (1 << 14) 400#define NAU8825_MICBIAS_JKR2 (1 << 12) 401#define NAU8825_MICBIAS_POWERUP_SFT 8 402#define NAU8825_MICBIAS_VOLTAGE_SFT 0 403#define NAU8825_MICBIAS_VOLTAGE_MASK 0x7 404 405/* BOOST (0x76) */ 406#define NAU8825_PRECHARGE_DIS (1 << 13) 407#define NAU8825_GLOBAL_BIAS_EN (1 << 12) 408#define NAU8825_HP_BOOST_DIS (1 << 9) 409#define NAU8825_HP_BOOST_G_DIS (1 << 8) 410#define NAU8825_SHORT_SHUTDOWN_EN (1 << 6) 411 412/* POWER_UP_CONTROL (0x7f) */ 413#define NAU8825_POWERUP_INTEGR_R (1 << 5) 414#define NAU8825_POWERUP_INTEGR_L (1 << 4) 415#define NAU8825_POWERUP_DRV_IN_R (1 << 3) 416#define NAU8825_POWERUP_DRV_IN_L (1 << 2) 417#define NAU8825_POWERUP_HP_DRV_R (1 << 1) 418#define NAU8825_POWERUP_HP_DRV_L (1 << 0) 419 420/* CHARGE_PUMP (0x80) */ 421#define NAU8825_JAMNODCLOW (1 << 10) 422#define NAU8825_POWER_DOWN_DACR (1 << 9) 423#define NAU8825_POWER_DOWN_DACL (1 << 8) 424#define NAU8825_CHANRGE_PUMP_EN (1 << 5) 425 426 427/* System Clock Source */ 428enum { 429 NAU8825_CLK_DIS = 0, 430 NAU8825_CLK_MCLK, 431 NAU8825_CLK_INTERNAL, 432 NAU8825_CLK_FLL_MCLK, 433 NAU8825_CLK_FLL_BLK, 434 NAU8825_CLK_FLL_FS, 435}; 436 437/* Cross talk detection state */ 438enum { 439 NAU8825_XTALK_PREPARE = 0, 440 NAU8825_XTALK_HPR_R2L, 441 NAU8825_XTALK_HPL_R2L, 442 NAU8825_XTALK_IMM, 443 NAU8825_XTALK_DONE, 444}; 445 446struct nau8825 { 447 struct device *dev; 448 struct regmap *regmap; 449 struct snd_soc_dapm_context *dapm; 450 struct snd_soc_jack *jack; 451 struct clk *mclk; 452 struct work_struct xtalk_work; 453 struct semaphore xtalk_sem; 454 int irq; 455 int mclk_freq; /* 0 - mclk is disabled */ 456 int button_pressed; 457 int micbias_voltage; 458 int vref_impedance; 459 bool jkdet_enable; 460 bool jkdet_pull_enable; 461 bool jkdet_pull_up; 462 int jkdet_polarity; 463 int sar_threshold_num; 464 int sar_threshold[8]; 465 int sar_hysteresis; 466 int sar_voltage; 467 int sar_compare_time; 468 int sar_sampling_time; 469 int key_debounce; 470 int jack_insert_debounce; 471 int jack_eject_debounce; 472 int high_imped; 473 int xtalk_state; 474 int xtalk_event; 475 int xtalk_event_mask; 476 bool xtalk_protect; 477 int imp_rms[NAU8825_XTALK_IMM]; 478 int xtalk_enable; 479 bool xtalk_baktab_initialized; /* True if initialized. */ 480}; 481 482int nau8825_enable_jack_detect(struct snd_soc_component *component, 483 struct snd_soc_jack *jack); 484 485 486#endif /* __NAU8825_H__ */ 487