1// SPDX-License-Identifier: GPL-2.0 2// 3// mt6359.c -- mt6359 ALSA SoC audio codec driver 4// 5// Copyright (c) 2020 MediaTek Inc. 6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8#include <linux/delay.h> 9#include <linux/kthread.h> 10#include <linux/mfd/mt6397/core.h> 11#include <linux/module.h> 12#include <linux/of_device.h> 13#include <linux/platform_device.h> 14#include <linux/regulator/consumer.h> 15#include <linux/sched.h> 16#include <sound/soc.h> 17#include <sound/tlv.h> 18 19#include "mt6359.h" 20 21static void mt6359_set_playback_gpio(struct mt6359_priv *priv) 22{ 23 /* set gpio mosi mode, clk / data mosi */ 24 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe); 25 regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249); 26 27 /* sync mosi */ 28 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6); 29 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1); 30} 31 32static void mt6359_reset_playback_gpio(struct mt6359_priv *priv) 33{ 34 /* set pad_aud_*_mosi to GPIO mode and dir input 35 * reason: 36 * pad_aud_dat_mosi*, because the pin is used as boot strap 37 * don't clean clk/sync, for mtkaif protocol 2 38 */ 39 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8); 40 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0); 41} 42 43static void mt6359_set_capture_gpio(struct mt6359_priv *priv) 44{ 45 /* set gpio miso mode */ 46 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00); 47 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200); 48 49 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f); 50 regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009); 51} 52 53static void mt6359_reset_capture_gpio(struct mt6359_priv *priv) 54{ 55 /* set pad_aud_*_miso to GPIO mode and dir input 56 * reason: 57 * pad_aud_clk_miso, because when playback only the miso_clk 58 * will also have 26m, so will have power leak 59 * pad_aud_dat_miso*, because the pin is used as boot strap 60 */ 61 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00); 62 63 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f); 64 65 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 66 0x7 << 13, 0x0); 67 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1, 68 0x3 << 0, 0x0); 69} 70 71static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable) 72{ 73 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13, 74 RG_RSTB_DECODER_VA32_MASK_SFT, 75 (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT); 76} 77 78static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv) 79{ 80 switch (priv->mtkaif_protocol) { 81 case MT6359_MTKAIF_PROTOCOL_2_CLK_P2: 82 /* MTKAIF TX format setting */ 83 regmap_update_bits(priv->regmap, 84 MT6359_AFE_ADDA_MTKAIF_CFG0, 85 0xffff, 0x0210); 86 /* enable aud_pad TX fifos */ 87 regmap_update_bits(priv->regmap, 88 MT6359_AFE_AUD_PAD_TOP, 89 0xff00, 0x3800); 90 regmap_update_bits(priv->regmap, 91 MT6359_AFE_AUD_PAD_TOP, 92 0xff00, 0x3900); 93 break; 94 case MT6359_MTKAIF_PROTOCOL_2: 95 /* MTKAIF TX format setting */ 96 regmap_update_bits(priv->regmap, 97 MT6359_AFE_ADDA_MTKAIF_CFG0, 98 0xffff, 0x0210); 99 /* enable aud_pad TX fifos */ 100 regmap_update_bits(priv->regmap, 101 MT6359_AFE_AUD_PAD_TOP, 102 0xff00, 0x3100); 103 break; 104 case MT6359_MTKAIF_PROTOCOL_1: 105 default: 106 /* MTKAIF TX format setting */ 107 regmap_update_bits(priv->regmap, 108 MT6359_AFE_ADDA_MTKAIF_CFG0, 109 0xffff, 0x0000); 110 /* enable aud_pad TX fifos */ 111 regmap_update_bits(priv->regmap, 112 MT6359_AFE_AUD_PAD_TOP, 113 0xff00, 0x3100); 114 break; 115 } 116} 117 118static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv) 119{ 120 /* disable aud_pad TX fifos */ 121 regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP, 122 0xff00, 0x3000); 123} 124 125static void zcd_disable(struct mt6359_priv *priv) 126{ 127 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000); 128} 129 130static void hp_main_output_ramp(struct mt6359_priv *priv, bool up) 131{ 132 int i = 0, stage = 0; 133 int target = 7; 134 135 /* Enable/Reduce HPL/R main output stage step by step */ 136 for (i = 0; i <= target; i++) { 137 stage = up ? i : target - i; 138 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 139 RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT, 140 stage << RG_HPLOUTSTGCTRL_VAUDP32_SFT); 141 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 142 RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT, 143 stage << RG_HPROUTSTGCTRL_VAUDP32_SFT); 144 usleep_range(600, 650); 145 } 146} 147 148static void hp_aux_feedback_loop_gain_ramp(struct mt6359_priv *priv, bool up) 149{ 150 int i = 0, stage = 0; 151 int target = 0xf; 152 153 /* Enable/Reduce HP aux feedback loop gain step by step */ 154 for (i = 0; i <= target; i++) { 155 stage = up ? i : target - i; 156 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9, 157 0xf << 12, stage << 12); 158 usleep_range(600, 650); 159 } 160} 161 162static void hp_in_pair_current(struct mt6359_priv *priv, bool increase) 163{ 164 int i = 0, stage = 0; 165 int target = 0x3; 166 167 /* Set input diff pair bias select (Hi-Fi mode) */ 168 if (priv->hp_hifi_mode) { 169 /* Reduce HP aux feedback loop gain step by step */ 170 for (i = 0; i <= target; i++) { 171 stage = increase ? i : target - i; 172 regmap_update_bits(priv->regmap, 173 MT6359_AUDDEC_ANA_CON10, 174 0x3 << 3, stage << 3); 175 usleep_range(100, 150); 176 } 177 } 178} 179 180static void hp_pull_down(struct mt6359_priv *priv, bool enable) 181{ 182 int i; 183 184 if (enable) { 185 for (i = 0x0; i <= 0x7; i++) { 186 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2, 187 RG_HPPSHORT2VCM_VAUDP32_MASK_SFT, 188 i << RG_HPPSHORT2VCM_VAUDP32_SFT); 189 usleep_range(100, 150); 190 } 191 } else { 192 for (i = 0x7; i >= 0x0; i--) { 193 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2, 194 RG_HPPSHORT2VCM_VAUDP32_MASK_SFT, 195 i << RG_HPPSHORT2VCM_VAUDP32_SFT); 196 usleep_range(100, 150); 197 } 198 } 199} 200 201static bool is_valid_hp_pga_idx(int reg_idx) 202{ 203 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_22DB) || 204 reg_idx == DL_GAIN_N_40DB; 205} 206 207static void headset_volume_ramp(struct mt6359_priv *priv, 208 int from, int to) 209{ 210 int offset = 0, count = 1, reg_idx; 211 212 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) { 213 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", 214 __func__, from, to); 215 return; 216 } 217 218 dev_dbg(priv->dev, "%s(), from %d, to %d\n", __func__, from, to); 219 220 if (to > from) 221 offset = to - from; 222 else 223 offset = from - to; 224 225 while (offset > 0) { 226 if (to > from) 227 reg_idx = from + count; 228 else 229 reg_idx = from - count; 230 231 if (is_valid_hp_pga_idx(reg_idx)) { 232 regmap_update_bits(priv->regmap, 233 MT6359_ZCD_CON2, 234 DL_GAIN_REG_MASK, 235 (reg_idx << 7) | reg_idx); 236 usleep_range(600, 650); 237 } 238 offset--; 239 count++; 240 } 241} 242 243static int mt6359_put_volsw(struct snd_kcontrol *kcontrol, 244 struct snd_ctl_elem_value *ucontrol) 245{ 246 struct snd_soc_component *component = 247 snd_soc_kcontrol_component(kcontrol); 248 struct mt6359_priv *priv = snd_soc_component_get_drvdata(component); 249 struct soc_mixer_control *mc = 250 (struct soc_mixer_control *)kcontrol->private_value; 251 unsigned int reg; 252 int index = ucontrol->value.integer.value[0]; 253 int ret; 254 255 ret = snd_soc_put_volsw(kcontrol, ucontrol); 256 if (ret < 0) 257 return ret; 258 259 switch (mc->reg) { 260 case MT6359_ZCD_CON2: 261 regmap_read(priv->regmap, MT6359_ZCD_CON2, ®); 262 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 263 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; 264 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 265 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; 266 break; 267 case MT6359_ZCD_CON1: 268 regmap_read(priv->regmap, MT6359_ZCD_CON1, ®); 269 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = 270 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK; 271 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = 272 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK; 273 break; 274 case MT6359_ZCD_CON3: 275 regmap_read(priv->regmap, MT6359_ZCD_CON3, ®); 276 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] = 277 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 278 break; 279 case MT6359_AUDENC_ANA_CON0: 280 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, ®); 281 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 282 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK; 283 break; 284 case MT6359_AUDENC_ANA_CON1: 285 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, ®); 286 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 287 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK; 288 break; 289 case MT6359_AUDENC_ANA_CON2: 290 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, ®); 291 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] = 292 (reg >> RG_AUDPREAMP3GAIN_SFT) & RG_AUDPREAMP3GAIN_MASK; 293 break; 294 } 295 296 dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n", 297 __func__, kcontrol->id.name, mc->reg, reg, index); 298 299 return ret; 300} 301 302/* MUX */ 303 304/* LOL MUX */ 305static const char * const lo_in_mux_map[] = { 306 "Open", "Playback_L_DAC", "Playback", "Test Mode" 307}; 308 309static SOC_ENUM_SINGLE_DECL(lo_in_mux_map_enum, SND_SOC_NOPM, 0, lo_in_mux_map); 310 311static const struct snd_kcontrol_new lo_in_mux_control = 312 SOC_DAPM_ENUM("LO Select", lo_in_mux_map_enum); 313 314/*HP MUX */ 315static const char * const hp_in_mux_map[] = { 316 "Open", 317 "LoudSPK Playback", 318 "Audio Playback", 319 "Test Mode", 320 "HP Impedance", 321}; 322 323static SOC_ENUM_SINGLE_DECL(hp_in_mux_map_enum, 324 SND_SOC_NOPM, 325 0, 326 hp_in_mux_map); 327 328static const struct snd_kcontrol_new hp_in_mux_control = 329 SOC_DAPM_ENUM("HP Select", hp_in_mux_map_enum); 330 331/* RCV MUX */ 332static const char * const rcv_in_mux_map[] = { 333 "Open", "Mute", "Voice Playback", "Test Mode" 334}; 335 336static SOC_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, 337 SND_SOC_NOPM, 338 0, 339 rcv_in_mux_map); 340 341static const struct snd_kcontrol_new rcv_in_mux_control = 342 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); 343 344/* DAC In MUX */ 345static const char * const dac_in_mux_map[] = { 346 "Normal Path", "Sgen" 347}; 348 349static int dac_in_mux_map_value[] = { 350 0x0, 0x1, 351}; 352 353static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, 354 MT6359_AFE_TOP_CON0, 355 DL_SINE_ON_SFT, 356 DL_SINE_ON_MASK, 357 dac_in_mux_map, 358 dac_in_mux_map_value); 359 360static const struct snd_kcontrol_new dac_in_mux_control = 361 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); 362 363/* AIF Out MUX */ 364static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, 365 MT6359_AFE_TOP_CON0, 366 UL_SINE_ON_SFT, 367 UL_SINE_ON_MASK, 368 dac_in_mux_map, 369 dac_in_mux_map_value); 370 371static const struct snd_kcontrol_new aif_out_mux_control = 372 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); 373 374static SOC_VALUE_ENUM_SINGLE_DECL(aif2_out_mux_map_enum, 375 MT6359_AFE_TOP_CON0, 376 ADDA6_UL_SINE_ON_SFT, 377 ADDA6_UL_SINE_ON_MASK, 378 dac_in_mux_map, 379 dac_in_mux_map_value); 380 381static const struct snd_kcontrol_new aif2_out_mux_control = 382 SOC_DAPM_ENUM("AIF Out Select", aif2_out_mux_map_enum); 383 384static const char * const ul_src_mux_map[] = { 385 "AMIC", 386 "DMIC", 387}; 388 389static int ul_src_mux_map_value[] = { 390 UL_SRC_MUX_AMIC, 391 UL_SRC_MUX_DMIC, 392}; 393 394static SOC_VALUE_ENUM_SINGLE_DECL(ul_src_mux_map_enum, 395 MT6359_AFE_UL_SRC_CON0_L, 396 UL_SDM_3_LEVEL_CTL_SFT, 397 UL_SDM_3_LEVEL_CTL_MASK, 398 ul_src_mux_map, 399 ul_src_mux_map_value); 400 401static const struct snd_kcontrol_new ul_src_mux_control = 402 SOC_DAPM_ENUM("UL_SRC_MUX Select", ul_src_mux_map_enum); 403 404static SOC_VALUE_ENUM_SINGLE_DECL(ul2_src_mux_map_enum, 405 MT6359_AFE_ADDA6_UL_SRC_CON0_L, 406 ADDA6_UL_SDM_3_LEVEL_CTL_SFT, 407 ADDA6_UL_SDM_3_LEVEL_CTL_MASK, 408 ul_src_mux_map, 409 ul_src_mux_map_value); 410 411static const struct snd_kcontrol_new ul2_src_mux_control = 412 SOC_DAPM_ENUM("UL_SRC_MUX Select", ul2_src_mux_map_enum); 413 414static const char * const miso_mux_map[] = { 415 "UL1_CH1", 416 "UL1_CH2", 417 "UL2_CH1", 418 "UL2_CH2", 419}; 420 421static int miso_mux_map_value[] = { 422 MISO_MUX_UL1_CH1, 423 MISO_MUX_UL1_CH2, 424 MISO_MUX_UL2_CH1, 425 MISO_MUX_UL2_CH2, 426}; 427 428static SOC_VALUE_ENUM_SINGLE_DECL(miso0_mux_map_enum, 429 MT6359_AFE_MTKAIF_MUX_CFG, 430 RG_ADDA_CH1_SEL_SFT, 431 RG_ADDA_CH1_SEL_MASK, 432 miso_mux_map, 433 miso_mux_map_value); 434 435static const struct snd_kcontrol_new miso0_mux_control = 436 SOC_DAPM_ENUM("MISO_MUX Select", miso0_mux_map_enum); 437 438static SOC_VALUE_ENUM_SINGLE_DECL(miso1_mux_map_enum, 439 MT6359_AFE_MTKAIF_MUX_CFG, 440 RG_ADDA_CH2_SEL_SFT, 441 RG_ADDA_CH2_SEL_MASK, 442 miso_mux_map, 443 miso_mux_map_value); 444 445static const struct snd_kcontrol_new miso1_mux_control = 446 SOC_DAPM_ENUM("MISO_MUX Select", miso1_mux_map_enum); 447 448static SOC_VALUE_ENUM_SINGLE_DECL(miso2_mux_map_enum, 449 MT6359_AFE_MTKAIF_MUX_CFG, 450 RG_ADDA6_CH1_SEL_SFT, 451 RG_ADDA6_CH1_SEL_MASK, 452 miso_mux_map, 453 miso_mux_map_value); 454 455static const struct snd_kcontrol_new miso2_mux_control = 456 SOC_DAPM_ENUM("MISO_MUX Select", miso2_mux_map_enum); 457 458static const char * const dmic_mux_map[] = { 459 "DMIC_DATA0", 460 "DMIC_DATA1_L", 461 "DMIC_DATA1_L_1", 462 "DMIC_DATA1_R", 463}; 464 465static int dmic_mux_map_value[] = { 466 DMIC_MUX_DMIC_DATA0, 467 DMIC_MUX_DMIC_DATA1_L, 468 DMIC_MUX_DMIC_DATA1_L_1, 469 DMIC_MUX_DMIC_DATA1_R, 470}; 471 472static SOC_VALUE_ENUM_SINGLE_DECL(dmic0_mux_map_enum, 473 MT6359_AFE_MIC_ARRAY_CFG, 474 RG_DMIC_ADC1_SOURCE_SEL_SFT, 475 RG_DMIC_ADC1_SOURCE_SEL_MASK, 476 dmic_mux_map, 477 dmic_mux_map_value); 478 479static const struct snd_kcontrol_new dmic0_mux_control = 480 SOC_DAPM_ENUM("DMIC_MUX Select", dmic0_mux_map_enum); 481 482/* ul1 ch2 use RG_DMIC_ADC3_SOURCE_SEL */ 483static SOC_VALUE_ENUM_SINGLE_DECL(dmic1_mux_map_enum, 484 MT6359_AFE_MIC_ARRAY_CFG, 485 RG_DMIC_ADC3_SOURCE_SEL_SFT, 486 RG_DMIC_ADC3_SOURCE_SEL_MASK, 487 dmic_mux_map, 488 dmic_mux_map_value); 489 490static const struct snd_kcontrol_new dmic1_mux_control = 491 SOC_DAPM_ENUM("DMIC_MUX Select", dmic1_mux_map_enum); 492 493/* ul2 ch1 use RG_DMIC_ADC2_SOURCE_SEL */ 494static SOC_VALUE_ENUM_SINGLE_DECL(dmic2_mux_map_enum, 495 MT6359_AFE_MIC_ARRAY_CFG, 496 RG_DMIC_ADC2_SOURCE_SEL_SFT, 497 RG_DMIC_ADC2_SOURCE_SEL_MASK, 498 dmic_mux_map, 499 dmic_mux_map_value); 500 501static const struct snd_kcontrol_new dmic2_mux_control = 502 SOC_DAPM_ENUM("DMIC_MUX Select", dmic2_mux_map_enum); 503 504/* ADC L MUX */ 505static const char * const adc_left_mux_map[] = { 506 "Idle", "AIN0", "Left Preamplifier", "Idle_1" 507}; 508 509static int adc_mux_map_value[] = { 510 ADC_MUX_IDLE, 511 ADC_MUX_AIN0, 512 ADC_MUX_PREAMPLIFIER, 513 ADC_MUX_IDLE1, 514}; 515 516static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, 517 MT6359_AUDENC_ANA_CON0, 518 RG_AUDADCLINPUTSEL_SFT, 519 RG_AUDADCLINPUTSEL_MASK, 520 adc_left_mux_map, 521 adc_mux_map_value); 522 523static const struct snd_kcontrol_new adc_left_mux_control = 524 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); 525 526/* ADC R MUX */ 527static const char * const adc_right_mux_map[] = { 528 "Idle", "AIN0", "Right Preamplifier", "Idle_1" 529}; 530 531static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, 532 MT6359_AUDENC_ANA_CON1, 533 RG_AUDADCRINPUTSEL_SFT, 534 RG_AUDADCRINPUTSEL_MASK, 535 adc_right_mux_map, 536 adc_mux_map_value); 537 538static const struct snd_kcontrol_new adc_right_mux_control = 539 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); 540 541/* ADC 3 MUX */ 542static const char * const adc_3_mux_map[] = { 543 "Idle", "AIN0", "Preamplifier", "Idle_1" 544}; 545 546static SOC_VALUE_ENUM_SINGLE_DECL(adc_3_mux_map_enum, 547 MT6359_AUDENC_ANA_CON2, 548 RG_AUDADC3INPUTSEL_SFT, 549 RG_AUDADC3INPUTSEL_MASK, 550 adc_3_mux_map, 551 adc_mux_map_value); 552 553static const struct snd_kcontrol_new adc_3_mux_control = 554 SOC_DAPM_ENUM("ADC 3 Select", adc_3_mux_map_enum); 555 556static const char * const pga_l_mux_map[] = { 557 "None", "AIN0", "AIN1" 558}; 559 560static int pga_l_mux_map_value[] = { 561 PGA_L_MUX_NONE, 562 PGA_L_MUX_AIN0, 563 PGA_L_MUX_AIN1 564}; 565 566static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, 567 MT6359_AUDENC_ANA_CON0, 568 RG_AUDPREAMPLINPUTSEL_SFT, 569 RG_AUDPREAMPLINPUTSEL_MASK, 570 pga_l_mux_map, 571 pga_l_mux_map_value); 572 573static const struct snd_kcontrol_new pga_left_mux_control = 574 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); 575 576static const char * const pga_r_mux_map[] = { 577 "None", "AIN2", "AIN3", "AIN0" 578}; 579 580static int pga_r_mux_map_value[] = { 581 PGA_R_MUX_NONE, 582 PGA_R_MUX_AIN2, 583 PGA_R_MUX_AIN3, 584 PGA_R_MUX_AIN0 585}; 586 587static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, 588 MT6359_AUDENC_ANA_CON1, 589 RG_AUDPREAMPRINPUTSEL_SFT, 590 RG_AUDPREAMPRINPUTSEL_MASK, 591 pga_r_mux_map, 592 pga_r_mux_map_value); 593 594static const struct snd_kcontrol_new pga_right_mux_control = 595 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); 596 597static const char * const pga_3_mux_map[] = { 598 "None", "AIN3", "AIN2" 599}; 600 601static int pga_3_mux_map_value[] = { 602 PGA_3_MUX_NONE, 603 PGA_3_MUX_AIN3, 604 PGA_3_MUX_AIN2 605}; 606 607static SOC_VALUE_ENUM_SINGLE_DECL(pga_3_mux_map_enum, 608 MT6359_AUDENC_ANA_CON2, 609 RG_AUDPREAMP3INPUTSEL_SFT, 610 RG_AUDPREAMP3INPUTSEL_MASK, 611 pga_3_mux_map, 612 pga_3_mux_map_value); 613 614static const struct snd_kcontrol_new pga_3_mux_control = 615 SOC_DAPM_ENUM("PGA 3 Select", pga_3_mux_map_enum); 616 617static int mt_sgen_event(struct snd_soc_dapm_widget *w, 618 struct snd_kcontrol *kcontrol, 619 int event) 620{ 621 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 622 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 623 624 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 625 626 switch (event) { 627 case SND_SOC_DAPM_PRE_PMU: 628 /* sdm audio fifo clock power on */ 629 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006); 630 /* scrambler clock on enable */ 631 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1); 632 /* sdm power on */ 633 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003); 634 /* sdm fifo enable */ 635 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b); 636 637 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG0, 638 0xff3f, 639 0x0000); 640 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG1, 641 0xffff, 642 0x0001); 643 break; 644 case SND_SOC_DAPM_POST_PMD: 645 /* DL scrambler disabling sequence */ 646 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000); 647 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0); 648 break; 649 default: 650 break; 651 } 652 653 return 0; 654} 655 656static void mtk_hp_enable(struct mt6359_priv *priv) 657{ 658 if (priv->hp_hifi_mode) { 659 /* Set HP DR bias current optimization, 010: 6uA */ 660 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11, 661 DRBIAS_HP_MASK_SFT, 662 DRBIAS_6UA << DRBIAS_HP_SFT); 663 /* Set HP & ZCD bias current optimization */ 664 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 665 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 666 IBIAS_ZCD_MASK_SFT, 667 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT); 668 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 669 IBIAS_HP_MASK_SFT, 670 IBIAS_5UA << IBIAS_HP_SFT); 671 } else { 672 /* Set HP DR bias current optimization, 001: 5uA */ 673 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11, 674 DRBIAS_HP_MASK_SFT, 675 DRBIAS_5UA << DRBIAS_HP_SFT); 676 /* Set HP & ZCD bias current optimization */ 677 /* 00: ZCD: 3uA, HP/HS/LO: 4uA */ 678 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 679 IBIAS_ZCD_MASK_SFT, 680 IBIAS_ZCD_3UA << IBIAS_ZCD_SFT); 681 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 682 IBIAS_HP_MASK_SFT, 683 IBIAS_4UA << IBIAS_HP_SFT); 684 } 685 686 /* HP damp circuit enable */ 687 /* Enable HPRN/HPLN output 4K to VCM */ 688 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087); 689 690 /* HP Feedback Cap select 2'b00: 15pF */ 691 /* for >= 96KHz sampling rate: 2'b01: 10.5pF */ 692 if (priv->dl_rate[MT6359_AIF_1] >= 96000) 693 regmap_update_bits(priv->regmap, 694 MT6359_AUDDEC_ANA_CON4, 695 RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT, 696 0x1 << RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT); 697 else 698 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000); 699 700 /* Set HPP/N STB enhance circuits */ 701 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133); 702 703 /* Enable HP aux output stage */ 704 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c); 705 /* Enable HP aux feedback loop */ 706 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c); 707 /* Enable HP aux CMFB loop */ 708 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00); 709 /* Enable HP driver bias circuits */ 710 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0); 711 /* Enable HP driver core circuits */ 712 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0); 713 /* Short HP main output to HP aux output stage */ 714 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc); 715 716 /* Increase HP input pair current to HPM step by step */ 717 hp_in_pair_current(priv, true); 718 719 /* Enable HP main CMFB loop */ 720 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00); 721 /* Disable HP aux CMFB loop */ 722 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200); 723 724 /* Enable HP main output stage */ 725 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff); 726 /* Enable HPR/L main output stage step by step */ 727 hp_main_output_ramp(priv, true); 728 729 /* Reduce HP aux feedback loop gain */ 730 hp_aux_feedback_loop_gain_ramp(priv, true); 731 /* Disable HP aux feedback loop */ 732 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf); 733 734 /* apply volume setting */ 735 headset_volume_ramp(priv, 736 DL_GAIN_N_22DB, 737 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 738 739 /* Disable HP aux output stage */ 740 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3); 741 /* Unshort HP main output to HP aux output stage */ 742 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703); 743 usleep_range(100, 120); 744 745 /* Enable AUD_CLK */ 746 mt6359_set_decoder_clk(priv, true); 747 748 /* Enable Audio DAC */ 749 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff); 750 if (priv->hp_hifi_mode) { 751 /* Enable low-noise mode of DAC */ 752 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201); 753 } else { 754 /* Disable low-noise mode of DAC */ 755 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200); 756 } 757 usleep_range(100, 120); 758 759 /* Switch HPL MUX to audio DAC */ 760 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff); 761 /* Switch HPR MUX to audio DAC */ 762 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff); 763 764 /* Disable Pull-down HPL/R to AVSS28_AUD */ 765 hp_pull_down(priv, false); 766} 767 768static void mtk_hp_disable(struct mt6359_priv *priv) 769{ 770 /* Pull-down HPL/R to AVSS28_AUD */ 771 hp_pull_down(priv, true); 772 773 /* HPR/HPL mux to open */ 774 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 775 0x0f00, 0x0000); 776 777 /* Disable low-noise mode of DAC */ 778 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9, 779 0x0001, 0x0000); 780 781 /* Disable Audio DAC */ 782 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 783 0x000f, 0x0000); 784 785 /* Disable AUD_CLK */ 786 mt6359_set_decoder_clk(priv, false); 787 788 /* Short HP main output to HP aux output stage */ 789 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3); 790 /* Enable HP aux output stage */ 791 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf); 792 793 /* decrease HPL/R gain to normal gain step by step */ 794 headset_volume_ramp(priv, 795 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 796 DL_GAIN_N_22DB); 797 798 /* Enable HP aux feedback loop */ 799 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff); 800 801 /* Reduce HP aux feedback loop gain */ 802 hp_aux_feedback_loop_gain_ramp(priv, false); 803 804 /* decrease HPR/L main output stage step by step */ 805 hp_main_output_ramp(priv, false); 806 807 /* Disable HP main output stage */ 808 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0); 809 810 /* Enable HP aux CMFB loop */ 811 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01); 812 813 /* Disable HP main CMFB loop */ 814 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01); 815 816 /* Decrease HP input pair current to 2'b00 step by step */ 817 hp_in_pair_current(priv, false); 818 819 /* Unshort HP main output to HP aux output stage */ 820 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 821 0x3 << 6, 0x0); 822 823 /* Disable HP driver core circuits */ 824 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 825 0x3 << 4, 0x0); 826 827 /* Disable HP driver bias circuits */ 828 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 829 0x3 << 6, 0x0); 830 831 /* Disable HP aux CMFB loop */ 832 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201); 833 834 /* Disable HP aux feedback loop */ 835 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 836 0x3 << 4, 0x0); 837 838 /* Disable HP aux output stage */ 839 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 840 0x3 << 2, 0x0); 841} 842 843static int mt_hp_event(struct snd_soc_dapm_widget *w, 844 struct snd_kcontrol *kcontrol, 845 int event) 846{ 847 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 848 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 849 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 850 int device = DEVICE_HP; 851 852 dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", 853 __func__, event, priv->dev_counter[device], mux); 854 855 switch (event) { 856 case SND_SOC_DAPM_PRE_PMU: 857 priv->dev_counter[device]++; 858 if (mux == HP_MUX_HP) 859 mtk_hp_enable(priv); 860 break; 861 case SND_SOC_DAPM_PRE_PMD: 862 priv->dev_counter[device]--; 863 if (mux == HP_MUX_HP) 864 mtk_hp_disable(priv); 865 break; 866 default: 867 break; 868 } 869 870 return 0; 871} 872 873static int mt_rcv_event(struct snd_soc_dapm_widget *w, 874 struct snd_kcontrol *kcontrol, 875 int event) 876{ 877 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 878 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 879 880 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 881 __func__, event, dapm_kcontrol_get_value(w->kcontrols[0])); 882 883 switch (event) { 884 case SND_SOC_DAPM_PRE_PMU: 885 /* Disable handset short-circuit protection */ 886 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010); 887 888 /* Set RCV DR bias current optimization, 010: 6uA */ 889 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11, 890 DRBIAS_HS_MASK_SFT, 891 DRBIAS_6UA << DRBIAS_HS_SFT); 892 /* Set RCV & ZCD bias current optimization */ 893 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 894 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 895 IBIAS_ZCD_MASK_SFT, 896 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT); 897 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 898 IBIAS_HS_MASK_SFT, 899 IBIAS_5UA << IBIAS_HS_SFT); 900 901 /* Set HS STB enhance circuits */ 902 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090); 903 904 /* Set HS output stage (3'b111 = 8x) */ 905 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000); 906 907 /* Enable HS driver bias circuits */ 908 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092); 909 /* Enable HS driver core circuits */ 910 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093); 911 912 /* Set HS gain to normal gain step by step */ 913 regmap_write(priv->regmap, MT6359_ZCD_CON3, 914 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]); 915 916 /* Enable AUD_CLK */ 917 mt6359_set_decoder_clk(priv, true); 918 919 /* Enable Audio DAC */ 920 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009); 921 /* Enable low-noise mode of DAC */ 922 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001); 923 /* Switch HS MUX to audio DAC */ 924 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b); 925 break; 926 case SND_SOC_DAPM_PRE_PMD: 927 /* HS mux to open */ 928 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6, 929 RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT, 930 RCV_MUX_OPEN); 931 932 /* Disable Audio DAC */ 933 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 934 0x000f, 0x0000); 935 936 /* Disable AUD_CLK */ 937 mt6359_set_decoder_clk(priv, false); 938 939 /* decrease HS gain to minimum gain step by step */ 940 regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB); 941 942 /* Disable HS driver core circuits */ 943 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6, 944 RG_AUDHSPWRUP_VAUDP32_MASK_SFT, 0x0); 945 946 /* Disable HS driver bias circuits */ 947 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6, 948 RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0); 949 break; 950 default: 951 break; 952 } 953 954 return 0; 955} 956 957static int mt_lo_event(struct snd_soc_dapm_widget *w, 958 struct snd_kcontrol *kcontrol, 959 int event) 960{ 961 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 962 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 963 964 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 965 __func__, event, dapm_kcontrol_get_value(w->kcontrols[0])); 966 967 switch (event) { 968 case SND_SOC_DAPM_PRE_PMU: 969 /* Disable handset short-circuit protection */ 970 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010); 971 972 /* Set LO DR bias current optimization, 010: 6uA */ 973 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11, 974 DRBIAS_LO_MASK_SFT, 975 DRBIAS_6UA << DRBIAS_LO_SFT); 976 /* Set LO & ZCD bias current optimization */ 977 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 978 if (priv->dev_counter[DEVICE_HP] == 0) 979 regmap_update_bits(priv->regmap, 980 MT6359_AUDDEC_ANA_CON12, 981 IBIAS_ZCD_MASK_SFT, 982 IBIAS_ZCD_4UA << IBIAS_ZCD_SFT); 983 984 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12, 985 IBIAS_LO_MASK_SFT, 986 IBIAS_5UA << IBIAS_LO_SFT); 987 988 /* Set LO STB enhance circuits */ 989 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110); 990 991 /* Enable LO driver bias circuits */ 992 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112); 993 /* Enable LO driver core circuits */ 994 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113); 995 996 /* Set LO gain to normal gain step by step */ 997 regmap_write(priv->regmap, MT6359_ZCD_CON1, 998 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]); 999 1000 /* Enable AUD_CLK */ 1001 mt6359_set_decoder_clk(priv, true); 1002 1003 /* Enable Audio DAC (3rd DAC) */ 1004 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113); 1005 /* Enable low-noise mode of DAC */ 1006 if (priv->dev_counter[DEVICE_HP] == 0) 1007 regmap_write(priv->regmap, 1008 MT6359_AUDDEC_ANA_CON9, 0x0001); 1009 /* Switch LOL MUX to audio 3rd DAC */ 1010 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b); 1011 break; 1012 case SND_SOC_DAPM_PRE_PMD: 1013 /* Switch LOL MUX to open */ 1014 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7, 1015 RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT, 1016 LO_MUX_OPEN); 1017 1018 /* Disable Audio DAC */ 1019 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 1020 0x000f, 0x0000); 1021 1022 /* Disable AUD_CLK */ 1023 mt6359_set_decoder_clk(priv, false); 1024 1025 /* decrease LO gain to minimum gain step by step */ 1026 regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB); 1027 1028 /* Disable LO driver core circuits */ 1029 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7, 1030 RG_AUDLOLPWRUP_VAUDP32_MASK_SFT, 0x0); 1031 1032 /* Disable LO driver bias circuits */ 1033 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7, 1034 RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0); 1035 break; 1036 default: 1037 break; 1038 } 1039 1040 return 0; 1041} 1042 1043static int mt_adc_clk_gen_event(struct snd_soc_dapm_widget *w, 1044 struct snd_kcontrol *kcontrol, 1045 int event) 1046{ 1047 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1048 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1049 1050 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event); 1051 1052 switch (event) { 1053 case SND_SOC_DAPM_POST_PMU: 1054 /* ADC CLK from CLKGEN (6.5MHz) */ 1055 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1056 RG_AUDADCCLKRSTB_MASK_SFT, 1057 0x1 << RG_AUDADCCLKRSTB_SFT); 1058 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1059 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0); 1060 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1061 RG_AUDADCCLKSEL_MASK_SFT, 0x0); 1062 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1063 RG_AUDADCCLKGENMODE_MASK_SFT, 1064 0x1 << RG_AUDADCCLKGENMODE_SFT); 1065 break; 1066 case SND_SOC_DAPM_PRE_PMD: 1067 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1068 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0); 1069 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1070 RG_AUDADCCLKSEL_MASK_SFT, 0x0); 1071 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1072 RG_AUDADCCLKGENMODE_MASK_SFT, 0x0); 1073 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5, 1074 RG_AUDADCCLKRSTB_MASK_SFT, 0x0); 1075 break; 1076 default: 1077 break; 1078 } 1079 1080 return 0; 1081} 1082 1083static int mt_dcc_clk_event(struct snd_soc_dapm_widget *w, 1084 struct snd_kcontrol *kcontrol, 1085 int event) 1086{ 1087 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1088 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1089 1090 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event); 1091 1092 switch (event) { 1093 case SND_SOC_DAPM_PRE_PMU: 1094 /* DCC 50k CLK (from 26M) */ 1095 /* MT6359_AFE_DCCLK_CFG0, bit 3 for dm ck swap */ 1096 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1097 0xfff7, 0x2062); 1098 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1099 0xfff7, 0x2060); 1100 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1101 0xfff7, 0x2061); 1102 1103 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100); 1104 break; 1105 case SND_SOC_DAPM_POST_PMD: 1106 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1107 0xfff7, 0x2060); 1108 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0, 1109 0xfff7, 0x2062); 1110 break; 1111 default: 1112 break; 1113 } 1114 1115 return 0; 1116} 1117 1118static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w, 1119 struct snd_kcontrol *kcontrol, 1120 int event) 1121{ 1122 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1123 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1124 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0]; 1125 1126 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", 1127 __func__, event, mic_type); 1128 1129 switch (event) { 1130 case SND_SOC_DAPM_PRE_PMU: 1131 switch (mic_type) { 1132 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1133 regmap_update_bits(priv->regmap, 1134 MT6359_AUDENC_ANA_CON15, 1135 0xff00, 0x7700); 1136 break; 1137 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1138 regmap_update_bits(priv->regmap, 1139 MT6359_AUDENC_ANA_CON15, 1140 0xff00, 0x1100); 1141 break; 1142 default: 1143 regmap_update_bits(priv->regmap, 1144 MT6359_AUDENC_ANA_CON15, 1145 0xff00, 0x0000); 1146 break; 1147 } 1148 1149 /* DMIC enable */ 1150 regmap_write(priv->regmap, 1151 MT6359_AUDENC_ANA_CON14, 0x0004); 1152 /* MISBIAS0 = 1P9V */ 1153 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15, 1154 RG_AUDMICBIAS0VREF_MASK_SFT, 1155 MIC_BIAS_1P9 << RG_AUDMICBIAS0VREF_SFT); 1156 /* normal power select */ 1157 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15, 1158 RG_AUDMICBIAS0LOWPEN_MASK_SFT, 1159 0 << RG_AUDMICBIAS0LOWPEN_SFT); 1160 break; 1161 case SND_SOC_DAPM_POST_PMD: 1162 /* Disable MICBIAS0, MISBIAS0 = 1P7V */ 1163 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000); 1164 break; 1165 default: 1166 break; 1167 } 1168 1169 return 0; 1170} 1171 1172static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w, 1173 struct snd_kcontrol *kcontrol, 1174 int event) 1175{ 1176 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1177 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1178 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1]; 1179 1180 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", 1181 __func__, event, mic_type); 1182 1183 switch (event) { 1184 case SND_SOC_DAPM_PRE_PMU: 1185 /* MISBIAS1 = 2P6V */ 1186 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE) 1187 regmap_write(priv->regmap, 1188 MT6359_AUDENC_ANA_CON16, 0x0160); 1189 else 1190 regmap_write(priv->regmap, 1191 MT6359_AUDENC_ANA_CON16, 0x0060); 1192 1193 /* normal power select */ 1194 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON16, 1195 RG_AUDMICBIAS1LOWPEN_MASK_SFT, 1196 0 << RG_AUDMICBIAS1LOWPEN_SFT); 1197 break; 1198 default: 1199 break; 1200 } 1201 1202 return 0; 1203} 1204 1205static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w, 1206 struct snd_kcontrol *kcontrol, 1207 int event) 1208{ 1209 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1210 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1211 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2]; 1212 1213 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", 1214 __func__, event, mic_type); 1215 1216 switch (event) { 1217 case SND_SOC_DAPM_PRE_PMU: 1218 switch (mic_type) { 1219 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1220 regmap_update_bits(priv->regmap, 1221 MT6359_AUDENC_ANA_CON17, 1222 0xff00, 0x7700); 1223 break; 1224 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1225 regmap_update_bits(priv->regmap, 1226 MT6359_AUDENC_ANA_CON17, 1227 0xff00, 0x1100); 1228 break; 1229 default: 1230 regmap_update_bits(priv->regmap, 1231 MT6359_AUDENC_ANA_CON17, 1232 0xff00, 0x0000); 1233 break; 1234 } 1235 1236 /* MISBIAS2 = 1P9V */ 1237 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17, 1238 RG_AUDMICBIAS2VREF_MASK_SFT, 1239 MIC_BIAS_1P9 << RG_AUDMICBIAS2VREF_SFT); 1240 /* normal power select */ 1241 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17, 1242 RG_AUDMICBIAS2LOWPEN_MASK_SFT, 1243 0 << RG_AUDMICBIAS2LOWPEN_SFT); 1244 break; 1245 case SND_SOC_DAPM_POST_PMD: 1246 /* Disable MICBIAS2, MISBIAS0 = 1P7V */ 1247 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000); 1248 break; 1249 default: 1250 break; 1251 } 1252 1253 return 0; 1254} 1255 1256static int mt_mtkaif_tx_event(struct snd_soc_dapm_widget *w, 1257 struct snd_kcontrol *kcontrol, 1258 int event) 1259{ 1260 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1261 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1262 1263 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1264 1265 switch (event) { 1266 case SND_SOC_DAPM_PRE_PMU: 1267 mt6359_mtkaif_tx_enable(priv); 1268 break; 1269 case SND_SOC_DAPM_POST_PMD: 1270 mt6359_mtkaif_tx_disable(priv); 1271 break; 1272 default: 1273 break; 1274 } 1275 1276 return 0; 1277} 1278 1279static int mt_ul_src_dmic_event(struct snd_soc_dapm_widget *w, 1280 struct snd_kcontrol *kcontrol, 1281 int event) 1282{ 1283 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1284 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1285 1286 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1287 1288 switch (event) { 1289 case SND_SOC_DAPM_PRE_PMU: 1290 /* UL dmic setting */ 1291 if (priv->dmic_one_wire_mode) 1292 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H, 1293 0x0400); 1294 else 1295 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H, 1296 0x0080); 1297 /* default one wire, 3.25M */ 1298 regmap_update_bits(priv->regmap, MT6359_AFE_UL_SRC_CON0_L, 1299 0xfffc, 0x0000); 1300 break; 1301 case SND_SOC_DAPM_POST_PMD: 1302 regmap_write(priv->regmap, 1303 MT6359_AFE_UL_SRC_CON0_H, 0x0000); 1304 break; 1305 default: 1306 break; 1307 } 1308 1309 return 0; 1310} 1311 1312static int mt_ul_src_34_dmic_event(struct snd_soc_dapm_widget *w, 1313 struct snd_kcontrol *kcontrol, 1314 int event) 1315{ 1316 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1317 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1318 1319 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1320 1321 switch (event) { 1322 case SND_SOC_DAPM_PRE_PMU: 1323 /* default two wire, 3.25M */ 1324 regmap_write(priv->regmap, 1325 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0080); 1326 regmap_update_bits(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L, 1327 0xfffc, 0x0000); 1328 break; 1329 case SND_SOC_DAPM_POST_PMD: 1330 regmap_write(priv->regmap, 1331 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0000); 1332 break; 1333 default: 1334 break; 1335 } 1336 1337 return 0; 1338} 1339 1340static int mt_adc_l_event(struct snd_soc_dapm_widget *w, 1341 struct snd_kcontrol *kcontrol, 1342 int event) 1343{ 1344 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1345 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1346 1347 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1348 1349 switch (event) { 1350 case SND_SOC_DAPM_POST_PMU: 1351 usleep_range(100, 120); 1352 /* Audio L preamplifier DCC precharge off */ 1353 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1354 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 1355 0x0); 1356 break; 1357 default: 1358 break; 1359 } 1360 1361 return 0; 1362} 1363 1364static int mt_adc_r_event(struct snd_soc_dapm_widget *w, 1365 struct snd_kcontrol *kcontrol, 1366 int event) 1367{ 1368 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1369 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1370 1371 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1372 1373 switch (event) { 1374 case SND_SOC_DAPM_POST_PMU: 1375 usleep_range(100, 120); 1376 /* Audio R preamplifier DCC precharge off */ 1377 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1378 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 1379 0x0); 1380 break; 1381 default: 1382 break; 1383 } 1384 1385 return 0; 1386} 1387 1388static int mt_adc_3_event(struct snd_soc_dapm_widget *w, 1389 struct snd_kcontrol *kcontrol, 1390 int event) 1391{ 1392 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1393 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1394 1395 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 1396 1397 switch (event) { 1398 case SND_SOC_DAPM_POST_PMU: 1399 usleep_range(100, 120); 1400 /* Audio R preamplifier DCC precharge off */ 1401 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1402 RG_AUDPREAMP3DCPRECHARGE_MASK_SFT, 1403 0x0); 1404 break; 1405 default: 1406 break; 1407 } 1408 1409 return 0; 1410} 1411 1412static int mt_pga_l_mux_event(struct snd_soc_dapm_widget *w, 1413 struct snd_kcontrol *kcontrol, 1414 int event) 1415{ 1416 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1417 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1418 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1419 1420 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux); 1421 priv->mux_select[MUX_PGA_L] = mux >> RG_AUDPREAMPLINPUTSEL_SFT; 1422 return 0; 1423} 1424 1425static int mt_pga_r_mux_event(struct snd_soc_dapm_widget *w, 1426 struct snd_kcontrol *kcontrol, 1427 int event) 1428{ 1429 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1430 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1431 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1432 1433 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux); 1434 priv->mux_select[MUX_PGA_R] = mux >> RG_AUDPREAMPRINPUTSEL_SFT; 1435 return 0; 1436} 1437 1438static int mt_pga_3_mux_event(struct snd_soc_dapm_widget *w, 1439 struct snd_kcontrol *kcontrol, 1440 int event) 1441{ 1442 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1443 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1444 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1445 1446 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux); 1447 priv->mux_select[MUX_PGA_3] = mux >> RG_AUDPREAMP3INPUTSEL_SFT; 1448 return 0; 1449} 1450 1451static int mt_pga_l_event(struct snd_soc_dapm_widget *w, 1452 struct snd_kcontrol *kcontrol, 1453 int event) 1454{ 1455 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1456 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1457 int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; 1458 unsigned int mux_pga = priv->mux_select[MUX_PGA_L]; 1459 unsigned int mic_type; 1460 1461 switch (mux_pga) { 1462 case PGA_L_MUX_AIN0: 1463 mic_type = priv->mux_select[MUX_MIC_TYPE_0]; 1464 break; 1465 case PGA_L_MUX_AIN1: 1466 mic_type = priv->mux_select[MUX_MIC_TYPE_1]; 1467 break; 1468 default: 1469 dev_err(priv->dev, "%s(), invalid pga mux %d\n", 1470 __func__, mux_pga); 1471 return -EINVAL; 1472 } 1473 1474 switch (event) { 1475 case SND_SOC_DAPM_PRE_PMU: 1476 if (IS_DCC_BASE(mic_type)) { 1477 /* Audio L preamplifier DCC precharge */ 1478 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1479 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 1480 0x1 << RG_AUDPREAMPLDCPRECHARGE_SFT); 1481 } 1482 break; 1483 case SND_SOC_DAPM_POST_PMU: 1484 /* set mic pga gain */ 1485 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1486 RG_AUDPREAMPLGAIN_MASK_SFT, 1487 mic_gain_l << RG_AUDPREAMPLGAIN_SFT); 1488 1489 if (IS_DCC_BASE(mic_type)) { 1490 /* L preamplifier DCCEN */ 1491 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1492 RG_AUDPREAMPLDCCEN_MASK_SFT, 1493 0x1 << RG_AUDPREAMPLDCCEN_SFT); 1494 } 1495 break; 1496 case SND_SOC_DAPM_POST_PMD: 1497 /* L preamplifier DCCEN */ 1498 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0, 1499 RG_AUDPREAMPLDCCEN_MASK_SFT, 1500 0x0 << RG_AUDPREAMPLDCCEN_SFT); 1501 break; 1502 default: 1503 break; 1504 } 1505 1506 return 0; 1507} 1508 1509static int mt_pga_r_event(struct snd_soc_dapm_widget *w, 1510 struct snd_kcontrol *kcontrol, 1511 int event) 1512{ 1513 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1514 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1515 int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; 1516 unsigned int mux_pga = priv->mux_select[MUX_PGA_R]; 1517 unsigned int mic_type; 1518 1519 switch (mux_pga) { 1520 case PGA_R_MUX_AIN0: 1521 mic_type = priv->mux_select[MUX_MIC_TYPE_0]; 1522 break; 1523 case PGA_R_MUX_AIN2: 1524 case PGA_R_MUX_AIN3: 1525 mic_type = priv->mux_select[MUX_MIC_TYPE_2]; 1526 break; 1527 default: 1528 dev_err(priv->dev, "%s(), invalid pga mux %d\n", 1529 __func__, mux_pga); 1530 return -EINVAL; 1531 } 1532 1533 switch (event) { 1534 case SND_SOC_DAPM_PRE_PMU: 1535 if (IS_DCC_BASE(mic_type)) { 1536 /* Audio R preamplifier DCC precharge */ 1537 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1538 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 1539 0x1 << RG_AUDPREAMPRDCPRECHARGE_SFT); 1540 } 1541 break; 1542 case SND_SOC_DAPM_POST_PMU: 1543 /* set mic pga gain */ 1544 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1545 RG_AUDPREAMPRGAIN_MASK_SFT, 1546 mic_gain_r << RG_AUDPREAMPRGAIN_SFT); 1547 1548 if (IS_DCC_BASE(mic_type)) { 1549 /* R preamplifier DCCEN */ 1550 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1551 RG_AUDPREAMPRDCCEN_MASK_SFT, 1552 0x1 << RG_AUDPREAMPRDCCEN_SFT); 1553 } 1554 break; 1555 case SND_SOC_DAPM_POST_PMD: 1556 /* R preamplifier DCCEN */ 1557 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1, 1558 RG_AUDPREAMPRDCCEN_MASK_SFT, 1559 0x0 << RG_AUDPREAMPRDCCEN_SFT); 1560 break; 1561 default: 1562 break; 1563 } 1564 1565 return 0; 1566} 1567 1568static int mt_pga_3_event(struct snd_soc_dapm_widget *w, 1569 struct snd_kcontrol *kcontrol, 1570 int event) 1571{ 1572 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1573 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1574 int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3]; 1575 unsigned int mux_pga = priv->mux_select[MUX_PGA_3]; 1576 unsigned int mic_type; 1577 1578 switch (mux_pga) { 1579 case PGA_3_MUX_AIN2: 1580 case PGA_3_MUX_AIN3: 1581 mic_type = priv->mux_select[MUX_MIC_TYPE_2]; 1582 break; 1583 default: 1584 dev_err(priv->dev, "%s(), invalid pga mux %d\n", 1585 __func__, mux_pga); 1586 return -EINVAL; 1587 } 1588 1589 switch (event) { 1590 case SND_SOC_DAPM_PRE_PMU: 1591 if (IS_DCC_BASE(mic_type)) { 1592 /* Audio 3 preamplifier DCC precharge */ 1593 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1594 RG_AUDPREAMP3DCPRECHARGE_MASK_SFT, 1595 0x1 << RG_AUDPREAMP3DCPRECHARGE_SFT); 1596 } 1597 break; 1598 case SND_SOC_DAPM_POST_PMU: 1599 /* set mic pga gain */ 1600 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1601 RG_AUDPREAMP3GAIN_MASK_SFT, 1602 mic_gain_3 << RG_AUDPREAMP3GAIN_SFT); 1603 1604 if (IS_DCC_BASE(mic_type)) { 1605 /* 3 preamplifier DCCEN */ 1606 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1607 RG_AUDPREAMP3DCCEN_MASK_SFT, 1608 0x1 << RG_AUDPREAMP3DCCEN_SFT); 1609 } 1610 break; 1611 case SND_SOC_DAPM_POST_PMD: 1612 /* 3 preamplifier DCCEN */ 1613 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2, 1614 RG_AUDPREAMP3DCCEN_MASK_SFT, 1615 0x0 << RG_AUDPREAMP3DCCEN_SFT); 1616 break; 1617 default: 1618 break; 1619 } 1620 1621 return 0; 1622} 1623 1624/* It is based on hw's control sequenece to add some delay when PMU/PMD */ 1625static int mt_delay_250_event(struct snd_soc_dapm_widget *w, 1626 struct snd_kcontrol *kcontrol, 1627 int event) 1628{ 1629 switch (event) { 1630 case SND_SOC_DAPM_POST_PMU: 1631 case SND_SOC_DAPM_PRE_PMD: 1632 usleep_range(250, 270); 1633 break; 1634 default: 1635 break; 1636 } 1637 1638 return 0; 1639} 1640 1641static int mt_delay_100_event(struct snd_soc_dapm_widget *w, 1642 struct snd_kcontrol *kcontrol, 1643 int event) 1644{ 1645 switch (event) { 1646 case SND_SOC_DAPM_POST_PMU: 1647 case SND_SOC_DAPM_PRE_PMD: 1648 usleep_range(100, 120); 1649 break; 1650 default: 1651 break; 1652 } 1653 1654 return 0; 1655} 1656 1657static int mt_hp_pull_down_event(struct snd_soc_dapm_widget *w, 1658 struct snd_kcontrol *kcontrol, 1659 int event) 1660{ 1661 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1662 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1663 1664 switch (event) { 1665 case SND_SOC_DAPM_PRE_PMU: 1666 hp_pull_down(priv, true); 1667 break; 1668 case SND_SOC_DAPM_POST_PMD: 1669 hp_pull_down(priv, false); 1670 break; 1671 default: 1672 break; 1673 } 1674 1675 return 0; 1676} 1677 1678static int mt_hp_mute_event(struct snd_soc_dapm_widget *w, 1679 struct snd_kcontrol *kcontrol, 1680 int event) 1681{ 1682 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1683 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1684 1685 switch (event) { 1686 case SND_SOC_DAPM_PRE_PMU: 1687 /* Set HPR/HPL gain to -22dB */ 1688 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_22DB_REG); 1689 break; 1690 case SND_SOC_DAPM_POST_PMD: 1691 /* Set HPL/HPR gain to mute */ 1692 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_40DB_REG); 1693 break; 1694 default: 1695 break; 1696 } 1697 1698 return 0; 1699} 1700 1701static int mt_hp_damp_event(struct snd_soc_dapm_widget *w, 1702 struct snd_kcontrol *kcontrol, 1703 int event) 1704{ 1705 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1706 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1707 1708 switch (event) { 1709 case SND_SOC_DAPM_POST_PMD: 1710 /* Disable HP damping circuit & HPN 4K load */ 1711 /* reset CMFB PW level */ 1712 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000); 1713 break; 1714 default: 1715 break; 1716 } 1717 1718 return 0; 1719} 1720 1721static int mt_esd_resist_event(struct snd_soc_dapm_widget *w, 1722 struct snd_kcontrol *kcontrol, 1723 int event) 1724{ 1725 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1726 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1727 1728 switch (event) { 1729 case SND_SOC_DAPM_PRE_PMU: 1730 /* Reduce ESD resistance of AU_REFN */ 1731 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2, 1732 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 1733 0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT); 1734 usleep_range(250, 270); 1735 break; 1736 case SND_SOC_DAPM_POST_PMD: 1737 /* Increase ESD resistance of AU_REFN */ 1738 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2, 1739 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 0x0); 1740 break; 1741 default: 1742 break; 1743 } 1744 1745 return 0; 1746} 1747 1748static int mt_sdm_event(struct snd_soc_dapm_widget *w, 1749 struct snd_kcontrol *kcontrol, 1750 int event) 1751{ 1752 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1753 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1754 1755 switch (event) { 1756 case SND_SOC_DAPM_PRE_PMU: 1757 /* sdm audio fifo clock power on */ 1758 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2, 1759 0xfffd, 0x0006); 1760 /* scrambler clock on enable */ 1761 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1); 1762 /* sdm power on */ 1763 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2, 1764 0xfffd, 0x0003); 1765 /* sdm fifo enable */ 1766 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2, 1767 0xfffd, 0x000B); 1768 break; 1769 case SND_SOC_DAPM_POST_PMD: 1770 /* DL scrambler disabling sequence */ 1771 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2, 1772 0xfffd, 0x0000); 1773 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0); 1774 break; 1775 default: 1776 break; 1777 } 1778 1779 return 0; 1780} 1781 1782static int mt_sdm_3rd_event(struct snd_soc_dapm_widget *w, 1783 struct snd_kcontrol *kcontrol, 1784 int event) 1785{ 1786 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1787 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1788 1789 switch (event) { 1790 case SND_SOC_DAPM_PRE_PMU: 1791 /* sdm audio fifo clock power on */ 1792 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006); 1793 /* scrambler clock on enable */ 1794 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1); 1795 /* sdm power on */ 1796 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003); 1797 /* sdm fifo enable */ 1798 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b); 1799 break; 1800 case SND_SOC_DAPM_POST_PMD: 1801 /* DL scrambler disabling sequence */ 1802 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000); 1803 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0); 1804 break; 1805 default: 1806 break; 1807 } 1808 1809 return 0; 1810} 1811 1812static int mt_ncp_event(struct snd_soc_dapm_widget *w, 1813 struct snd_kcontrol *kcontrol, 1814 int event) 1815{ 1816 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1817 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1818 1819 switch (event) { 1820 case SND_SOC_DAPM_PRE_PMU: 1821 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800); 1822 break; 1823 default: 1824 break; 1825 } 1826 1827 return 0; 1828} 1829 1830/* DAPM Widgets */ 1831static const struct snd_soc_dapm_widget mt6359_dapm_widgets[] = { 1832 /* Global Supply*/ 1833 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF, 1834 MT6359_DCXO_CW12, 1835 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0), 1836 SND_SOC_DAPM_SUPPLY_S("LDO_VAUD18", SUPPLY_SEQ_LDO_VAUD18, 1837 MT6359_LDO_VAUD18_CON0, 1838 RG_LDO_VAUD18_EN_SFT, 0, NULL, 0), 1839 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB, 1840 MT6359_AUDDEC_ANA_CON13, 1841 RG_AUDGLB_PWRDN_VA32_SFT, 1, NULL, 0), 1842 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ, 1843 MT6359_AUDENC_ANA_CON23, 1844 RG_CLKSQ_EN_SFT, 0, NULL, SND_SOC_DAPM_PRE_PMU), 1845 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK, 1846 MT6359_AUD_TOP_CKPDN_CON0, 1847 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0), 1848 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK, 1849 MT6359_AUD_TOP_CKPDN_CON0, 1850 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0), 1851 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST, 1852 MT6359_AUD_TOP_CKPDN_CON0, 1853 RG_AUD_CK_PDN_SFT, 1, mt_delay_250_event, 1854 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1855 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK, 1856 MT6359_AUD_TOP_CKPDN_CON0, 1857 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0), 1858 /* Digital Clock */ 1859 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST, 1860 MT6359_AUDIO_TOP_CON0, 1861 PDN_AFE_CTL_SFT, 1, 1862 mt_delay_250_event, 1863 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1864 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP, 1865 MT6359_AUDIO_TOP_CON0, 1866 PDN_DAC_CTL_SFT, 1, NULL, 0), 1867 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 1868 MT6359_AUDIO_TOP_CON0, 1869 PDN_ADC_CTL_SFT, 1, NULL, 0), 1870 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADDA6_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 1871 MT6359_AUDIO_TOP_CON0, 1872 PDN_ADDA6_ADC_CTL_SFT, 1, NULL, 0), 1873 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP, 1874 MT6359_AUDIO_TOP_CON0, 1875 PDN_I2S_DL_CTL_SFT, 1, NULL, 0), 1876 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP, 1877 MT6359_AUDIO_TOP_CON0, 1878 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0), 1879 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP, 1880 MT6359_AUDIO_TOP_CON0, 1881 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0), 1882 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP, 1883 MT6359_AUDIO_TOP_CON0, 1884 PDN_RESERVED_SFT, 1, NULL, 0), 1885 1886 SND_SOC_DAPM_SUPPLY_S("SDM", SUPPLY_SEQ_DL_SDM, 1887 SND_SOC_NOPM, 0, 0, 1888 mt_sdm_event, 1889 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1890 SND_SOC_DAPM_SUPPLY_S("SDM_3RD", SUPPLY_SEQ_DL_SDM, 1891 SND_SOC_NOPM, 0, 0, 1892 mt_sdm_3rd_event, 1893 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1894 1895 /* ch123 share SDM FIFO CLK */ 1896 SND_SOC_DAPM_SUPPLY_S("SDM_FIFO_CLK", SUPPLY_SEQ_DL_SDM_FIFO_CLK, 1897 MT6359_AFUNC_AUD_CON2, 1898 CCI_AFIFO_CLK_PWDB_SFT, 0, 1899 NULL, 0), 1900 1901 SND_SOC_DAPM_SUPPLY_S("NCP", SUPPLY_SEQ_DL_NCP, 1902 MT6359_AFE_NCP_CFG0, 1903 RG_NCP_ON_SFT, 0, 1904 mt_ncp_event, 1905 SND_SOC_DAPM_PRE_PMU), 1906 1907 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, 1908 0, 0, NULL, 0), 1909 SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_1_2", SND_SOC_NOPM, 1910 0, 0, NULL, 0), 1911 SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_3", SND_SOC_NOPM, 1912 0, 0, NULL, 0), 1913 1914 /* AFE ON */ 1915 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE, 1916 MT6359_AFE_UL_DL_CON0, AFE_ON_SFT, 0, 1917 NULL, 0), 1918 1919 /* AIF Rx*/ 1920 SND_SOC_DAPM_AIF_IN("AIF_RX", "AIF1 Playback", 0, 1921 SND_SOC_NOPM, 0, 0), 1922 1923 SND_SOC_DAPM_AIF_IN("AIF2_RX", "AIF2 Playback", 0, 1924 SND_SOC_NOPM, 0, 0), 1925 1926 SND_SOC_DAPM_SUPPLY_S("AFE_DL_SRC", SUPPLY_SEQ_DL_SRC, 1927 MT6359_AFE_DL_SRC2_CON0_L, 1928 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 1929 NULL, 0), 1930 1931 /* DL Supply */ 1932 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, 1933 0, 0, NULL, 0), 1934 1935 SND_SOC_DAPM_SUPPLY_S("ESD_RESIST", SUPPLY_SEQ_DL_ESD_RESIST, 1936 SND_SOC_NOPM, 1937 0, 0, 1938 mt_esd_resist_event, 1939 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1940 SND_SOC_DAPM_SUPPLY_S("LDO", SUPPLY_SEQ_DL_LDO, 1941 MT6359_AUDDEC_ANA_CON14, 1942 RG_LCLDO_DEC_EN_VA32_SFT, 0, 1943 NULL, 0), 1944 SND_SOC_DAPM_SUPPLY_S("LDO_REMOTE", SUPPLY_SEQ_DL_LDO_REMOTE_SENSE, 1945 MT6359_AUDDEC_ANA_CON14, 1946 RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT, 0, 1947 NULL, 0), 1948 SND_SOC_DAPM_SUPPLY_S("NV_REGULATOR", SUPPLY_SEQ_DL_NV, 1949 MT6359_AUDDEC_ANA_CON14, 1950 RG_NVREG_EN_VAUDP32_SFT, 0, 1951 mt_delay_100_event, SND_SOC_DAPM_POST_PMU), 1952 SND_SOC_DAPM_SUPPLY_S("IBIST", SUPPLY_SEQ_DL_IBIST, 1953 MT6359_AUDDEC_ANA_CON12, 1954 RG_AUDIBIASPWRDN_VAUDP32_SFT, 1, 1955 NULL, 0), 1956 1957 /* DAC */ 1958 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), 1959 1960 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 1961 1962 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 1963 1964 SND_SOC_DAPM_DAC("DAC_3RD", NULL, SND_SOC_NOPM, 0, 0), 1965 1966 /* Headphone */ 1967 SND_SOC_DAPM_MUX_E("HP Mux", SND_SOC_NOPM, 0, 0, 1968 &hp_in_mux_control, 1969 mt_hp_event, 1970 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1971 1972 SND_SOC_DAPM_SUPPLY("HP_Supply", SND_SOC_NOPM, 1973 0, 0, NULL, 0), 1974 SND_SOC_DAPM_SUPPLY_S("HP_PULL_DOWN", SUPPLY_SEQ_HP_PULL_DOWN, 1975 SND_SOC_NOPM, 1976 0, 0, 1977 mt_hp_pull_down_event, 1978 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1979 SND_SOC_DAPM_SUPPLY_S("HP_MUTE", SUPPLY_SEQ_HP_MUTE, 1980 SND_SOC_NOPM, 1981 0, 0, 1982 mt_hp_mute_event, 1983 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1984 SND_SOC_DAPM_SUPPLY_S("HP_DAMP", SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB, 1985 SND_SOC_NOPM, 1986 0, 0, 1987 mt_hp_damp_event, 1988 SND_SOC_DAPM_POST_PMD), 1989 1990 /* Receiver */ 1991 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0, 1992 &rcv_in_mux_control, 1993 mt_rcv_event, 1994 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1995 1996 /* LOL */ 1997 SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0, 1998 &lo_in_mux_control, 1999 mt_lo_event, 2000 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 2001 2002 /* Outputs */ 2003 SND_SOC_DAPM_OUTPUT("Receiver"), 2004 SND_SOC_DAPM_OUTPUT("Headphone L"), 2005 SND_SOC_DAPM_OUTPUT("Headphone R"), 2006 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"), 2007 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"), 2008 SND_SOC_DAPM_OUTPUT("LINEOUT L"), 2009 2010 /* SGEN */ 2011 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6359_AFE_SGEN_CFG0, 2012 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0), 2013 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6359_AFE_SGEN_CFG0, 2014 SGEN_MUTE_SW_CTL_SFT, 1, 2015 mt_sgen_event, 2016 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2017 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6359_AFE_DL_SRC2_CON0_L, 2018 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0), 2019 2020 SND_SOC_DAPM_INPUT("SGEN DL"), 2021 2022 /* Uplinks */ 2023 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 2024 SND_SOC_NOPM, 0, 0), 2025 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 2026 SND_SOC_NOPM, 0, 0), 2027 2028 SND_SOC_DAPM_SUPPLY_S("ADC_CLKGEN", SUPPLY_SEQ_ADC_CLKGEN, 2029 SND_SOC_NOPM, 0, 0, 2030 mt_adc_clk_gen_event, 2031 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2032 2033 SND_SOC_DAPM_SUPPLY_S("DCC_CLK", SUPPLY_SEQ_DCC_CLK, 2034 SND_SOC_NOPM, 0, 0, 2035 mt_dcc_clk_event, 2036 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2037 2038 /* Uplinks MUX */ 2039 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, 2040 &aif_out_mux_control), 2041 2042 SND_SOC_DAPM_MUX("AIF2 Out Mux", SND_SOC_NOPM, 0, 0, 2043 &aif2_out_mux_control), 2044 2045 SND_SOC_DAPM_SUPPLY("AIFTX_Supply", SND_SOC_NOPM, 0, 0, NULL, 0), 2046 2047 SND_SOC_DAPM_SUPPLY_S("MTKAIF_TX", SUPPLY_SEQ_UL_MTKAIF, 2048 SND_SOC_NOPM, 0, 0, 2049 mt_mtkaif_tx_event, 2050 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2051 2052 SND_SOC_DAPM_SUPPLY_S("UL_SRC", SUPPLY_SEQ_UL_SRC, 2053 MT6359_AFE_UL_SRC_CON0_L, 2054 UL_SRC_ON_TMP_CTL_SFT, 0, 2055 NULL, 0), 2056 2057 SND_SOC_DAPM_SUPPLY_S("UL_SRC_DMIC", SUPPLY_SEQ_UL_SRC_DMIC, 2058 SND_SOC_NOPM, 0, 0, 2059 mt_ul_src_dmic_event, 2060 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2061 2062 SND_SOC_DAPM_SUPPLY_S("UL_SRC_34", SUPPLY_SEQ_UL_SRC, 2063 MT6359_AFE_ADDA6_UL_SRC_CON0_L, 2064 ADDA6_UL_SRC_ON_TMP_CTL_SFT, 0, 2065 NULL, 0), 2066 2067 SND_SOC_DAPM_SUPPLY_S("UL_SRC_34_DMIC", SUPPLY_SEQ_UL_SRC_DMIC, 2068 SND_SOC_NOPM, 0, 0, 2069 mt_ul_src_34_dmic_event, 2070 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2071 2072 SND_SOC_DAPM_MUX("MISO0_MUX", SND_SOC_NOPM, 0, 0, &miso0_mux_control), 2073 SND_SOC_DAPM_MUX("MISO1_MUX", SND_SOC_NOPM, 0, 0, &miso1_mux_control), 2074 SND_SOC_DAPM_MUX("MISO2_MUX", SND_SOC_NOPM, 0, 0, &miso2_mux_control), 2075 2076 SND_SOC_DAPM_MUX("UL_SRC_MUX", SND_SOC_NOPM, 0, 0, 2077 &ul_src_mux_control), 2078 SND_SOC_DAPM_MUX("UL2_SRC_MUX", SND_SOC_NOPM, 0, 0, 2079 &ul2_src_mux_control), 2080 2081 SND_SOC_DAPM_MUX("DMIC0_MUX", SND_SOC_NOPM, 0, 0, &dmic0_mux_control), 2082 SND_SOC_DAPM_MUX("DMIC1_MUX", SND_SOC_NOPM, 0, 0, &dmic1_mux_control), 2083 SND_SOC_DAPM_MUX("DMIC2_MUX", SND_SOC_NOPM, 0, 0, &dmic2_mux_control), 2084 2085 SND_SOC_DAPM_MUX_E("ADC_L_Mux", SND_SOC_NOPM, 0, 0, 2086 &adc_left_mux_control, NULL, 0), 2087 SND_SOC_DAPM_MUX_E("ADC_R_Mux", SND_SOC_NOPM, 0, 0, 2088 &adc_right_mux_control, NULL, 0), 2089 SND_SOC_DAPM_MUX_E("ADC_3_Mux", SND_SOC_NOPM, 0, 0, 2090 &adc_3_mux_control, NULL, 0), 2091 2092 SND_SOC_DAPM_ADC("ADC_L", NULL, SND_SOC_NOPM, 0, 0), 2093 SND_SOC_DAPM_ADC("ADC_R", NULL, SND_SOC_NOPM, 0, 0), 2094 SND_SOC_DAPM_ADC("ADC_3", NULL, SND_SOC_NOPM, 0, 0), 2095 2096 SND_SOC_DAPM_SUPPLY_S("ADC_L_EN", SUPPLY_SEQ_UL_ADC, 2097 MT6359_AUDENC_ANA_CON0, 2098 RG_AUDADCLPWRUP_SFT, 0, 2099 mt_adc_l_event, 2100 SND_SOC_DAPM_POST_PMU), 2101 SND_SOC_DAPM_SUPPLY_S("ADC_R_EN", SUPPLY_SEQ_UL_ADC, 2102 MT6359_AUDENC_ANA_CON1, 2103 RG_AUDADCRPWRUP_SFT, 0, 2104 mt_adc_r_event, 2105 SND_SOC_DAPM_POST_PMU), 2106 SND_SOC_DAPM_SUPPLY_S("ADC_3_EN", SUPPLY_SEQ_UL_ADC, 2107 MT6359_AUDENC_ANA_CON2, 2108 RG_AUDADC3PWRUP_SFT, 0, 2109 mt_adc_3_event, 2110 SND_SOC_DAPM_POST_PMU), 2111 2112 SND_SOC_DAPM_MUX_E("PGA_L_Mux", SND_SOC_NOPM, 0, 0, 2113 &pga_left_mux_control, 2114 mt_pga_l_mux_event, 2115 SND_SOC_DAPM_WILL_PMU), 2116 SND_SOC_DAPM_MUX_E("PGA_R_Mux", SND_SOC_NOPM, 0, 0, 2117 &pga_right_mux_control, 2118 mt_pga_r_mux_event, 2119 SND_SOC_DAPM_WILL_PMU), 2120 SND_SOC_DAPM_MUX_E("PGA_3_Mux", SND_SOC_NOPM, 0, 0, 2121 &pga_3_mux_control, 2122 mt_pga_3_mux_event, 2123 SND_SOC_DAPM_WILL_PMU), 2124 2125 SND_SOC_DAPM_PGA("PGA_L", SND_SOC_NOPM, 0, 0, NULL, 0), 2126 SND_SOC_DAPM_PGA("PGA_R", SND_SOC_NOPM, 0, 0, NULL, 0), 2127 SND_SOC_DAPM_PGA("PGA_3", SND_SOC_NOPM, 0, 0, NULL, 0), 2128 2129 SND_SOC_DAPM_SUPPLY_S("PGA_L_EN", SUPPLY_SEQ_UL_PGA, 2130 MT6359_AUDENC_ANA_CON0, 2131 RG_AUDPREAMPLON_SFT, 0, 2132 mt_pga_l_event, 2133 SND_SOC_DAPM_PRE_PMU | 2134 SND_SOC_DAPM_POST_PMU | 2135 SND_SOC_DAPM_POST_PMD), 2136 SND_SOC_DAPM_SUPPLY_S("PGA_R_EN", SUPPLY_SEQ_UL_PGA, 2137 MT6359_AUDENC_ANA_CON1, 2138 RG_AUDPREAMPRON_SFT, 0, 2139 mt_pga_r_event, 2140 SND_SOC_DAPM_PRE_PMU | 2141 SND_SOC_DAPM_POST_PMU | 2142 SND_SOC_DAPM_POST_PMD), 2143 SND_SOC_DAPM_SUPPLY_S("PGA_3_EN", SUPPLY_SEQ_UL_PGA, 2144 MT6359_AUDENC_ANA_CON2, 2145 RG_AUDPREAMP3ON_SFT, 0, 2146 mt_pga_3_event, 2147 SND_SOC_DAPM_PRE_PMU | 2148 SND_SOC_DAPM_POST_PMU | 2149 SND_SOC_DAPM_POST_PMD), 2150 2151 /* UL input */ 2152 SND_SOC_DAPM_INPUT("AIN0"), 2153 SND_SOC_DAPM_INPUT("AIN1"), 2154 SND_SOC_DAPM_INPUT("AIN2"), 2155 SND_SOC_DAPM_INPUT("AIN3"), 2156 2157 SND_SOC_DAPM_INPUT("AIN0_DMIC"), 2158 SND_SOC_DAPM_INPUT("AIN2_DMIC"), 2159 SND_SOC_DAPM_INPUT("AIN3_DMIC"), 2160 2161 /* mic bias */ 2162 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_0", SUPPLY_SEQ_MIC_BIAS, 2163 MT6359_AUDENC_ANA_CON15, 2164 RG_AUDPWDBMICBIAS0_SFT, 0, 2165 mt_mic_bias_0_event, 2166 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2167 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_1", SUPPLY_SEQ_MIC_BIAS, 2168 MT6359_AUDENC_ANA_CON16, 2169 RG_AUDPWDBMICBIAS1_SFT, 0, 2170 mt_mic_bias_1_event, 2171 SND_SOC_DAPM_PRE_PMU), 2172 SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_2", SUPPLY_SEQ_MIC_BIAS, 2173 MT6359_AUDENC_ANA_CON17, 2174 RG_AUDPWDBMICBIAS2_SFT, 0, 2175 mt_mic_bias_2_event, 2176 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2177 2178 /* dmic */ 2179 SND_SOC_DAPM_SUPPLY_S("DMIC_0", SUPPLY_SEQ_DMIC, 2180 MT6359_AUDENC_ANA_CON13, 2181 RG_AUDDIGMICEN_SFT, 0, 2182 NULL, 0), 2183 SND_SOC_DAPM_SUPPLY_S("DMIC_1", SUPPLY_SEQ_DMIC, 2184 MT6359_AUDENC_ANA_CON14, 2185 RG_AUDDIGMIC1EN_SFT, 0, 2186 NULL, 0), 2187}; 2188 2189static int mt_dcc_clk_connect(struct snd_soc_dapm_widget *source, 2190 struct snd_soc_dapm_widget *sink) 2191{ 2192 struct snd_soc_dapm_widget *w = sink; 2193 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 2194 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2195 2196 if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) || 2197 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) || 2198 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2])) 2199 return 1; 2200 else 2201 return 0; 2202} 2203 2204static const struct snd_soc_dapm_route mt6359_dapm_routes[] = { 2205 /* Capture */ 2206 {"AIFTX_Supply", NULL, "CLK_BUF"}, 2207 {"AIFTX_Supply", NULL, "LDO_VAUD18"}, 2208 {"AIFTX_Supply", NULL, "AUDGLB"}, 2209 {"AIFTX_Supply", NULL, "CLKSQ Audio"}, 2210 {"AIFTX_Supply", NULL, "AUD_CK"}, 2211 {"AIFTX_Supply", NULL, "AUDIF_CK"}, 2212 {"AIFTX_Supply", NULL, "AUDIO_TOP_AFE_CTL"}, 2213 {"AIFTX_Supply", NULL, "AUDIO_TOP_PWR_CLK"}, 2214 {"AIFTX_Supply", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2215 {"AIFTX_Supply", NULL, "AUDIO_TOP_I2S_DL"}, 2216 /* 2217 * *_ADC_CTL should enable only if UL_SRC in use, 2218 * but dm ck may be needed even UL_SRC_x not in use 2219 */ 2220 {"AIFTX_Supply", NULL, "AUDIO_TOP_ADC_CTL"}, 2221 {"AIFTX_Supply", NULL, "AUDIO_TOP_ADDA6_ADC_CTL"}, 2222 {"AIFTX_Supply", NULL, "AFE_ON"}, 2223 2224 /* ul ch 12 */ 2225 {"AIF1TX", NULL, "AIF Out Mux"}, 2226 {"AIF1TX", NULL, "AIFTX_Supply"}, 2227 {"AIF1TX", NULL, "MTKAIF_TX"}, 2228 2229 {"AIF2TX", NULL, "AIF2 Out Mux"}, 2230 {"AIF2TX", NULL, "AIFTX_Supply"}, 2231 {"AIF2TX", NULL, "MTKAIF_TX"}, 2232 2233 {"AIF Out Mux", "Normal Path", "MISO0_MUX"}, 2234 {"AIF Out Mux", "Normal Path", "MISO1_MUX"}, 2235 {"AIF2 Out Mux", "Normal Path", "MISO2_MUX"}, 2236 2237 {"MISO0_MUX", "UL1_CH1", "UL_SRC_MUX"}, 2238 {"MISO0_MUX", "UL1_CH2", "UL_SRC_MUX"}, 2239 {"MISO0_MUX", "UL2_CH1", "UL2_SRC_MUX"}, 2240 {"MISO0_MUX", "UL2_CH2", "UL2_SRC_MUX"}, 2241 2242 {"MISO1_MUX", "UL1_CH1", "UL_SRC_MUX"}, 2243 {"MISO1_MUX", "UL1_CH2", "UL_SRC_MUX"}, 2244 {"MISO1_MUX", "UL2_CH1", "UL2_SRC_MUX"}, 2245 {"MISO1_MUX", "UL2_CH2", "UL2_SRC_MUX"}, 2246 2247 {"MISO2_MUX", "UL1_CH1", "UL_SRC_MUX"}, 2248 {"MISO2_MUX", "UL1_CH2", "UL_SRC_MUX"}, 2249 {"MISO2_MUX", "UL2_CH1", "UL2_SRC_MUX"}, 2250 {"MISO2_MUX", "UL2_CH2", "UL2_SRC_MUX"}, 2251 2252 {"UL_SRC_MUX", "AMIC", "ADC_L"}, 2253 {"UL_SRC_MUX", "AMIC", "ADC_R"}, 2254 {"UL_SRC_MUX", "DMIC", "DMIC0_MUX"}, 2255 {"UL_SRC_MUX", "DMIC", "DMIC1_MUX"}, 2256 {"UL_SRC_MUX", NULL, "UL_SRC"}, 2257 2258 {"UL2_SRC_MUX", "AMIC", "ADC_3"}, 2259 {"UL2_SRC_MUX", "DMIC", "DMIC2_MUX"}, 2260 {"UL2_SRC_MUX", NULL, "UL_SRC_34"}, 2261 2262 {"DMIC0_MUX", "DMIC_DATA0", "AIN0_DMIC"}, 2263 {"DMIC0_MUX", "DMIC_DATA1_L", "AIN2_DMIC"}, 2264 {"DMIC0_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"}, 2265 {"DMIC0_MUX", "DMIC_DATA1_R", "AIN3_DMIC"}, 2266 {"DMIC1_MUX", "DMIC_DATA0", "AIN0_DMIC"}, 2267 {"DMIC1_MUX", "DMIC_DATA1_L", "AIN2_DMIC"}, 2268 {"DMIC1_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"}, 2269 {"DMIC1_MUX", "DMIC_DATA1_R", "AIN3_DMIC"}, 2270 {"DMIC2_MUX", "DMIC_DATA0", "AIN0_DMIC"}, 2271 {"DMIC2_MUX", "DMIC_DATA1_L", "AIN2_DMIC"}, 2272 {"DMIC2_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"}, 2273 {"DMIC2_MUX", "DMIC_DATA1_R", "AIN3_DMIC"}, 2274 2275 {"DMIC0_MUX", NULL, "UL_SRC_DMIC"}, 2276 {"DMIC1_MUX", NULL, "UL_SRC_DMIC"}, 2277 {"DMIC2_MUX", NULL, "UL_SRC_34_DMIC"}, 2278 2279 {"AIN0_DMIC", NULL, "DMIC_0"}, 2280 {"AIN2_DMIC", NULL, "DMIC_1"}, 2281 {"AIN3_DMIC", NULL, "DMIC_1"}, 2282 {"AIN0_DMIC", NULL, "MIC_BIAS_0"}, 2283 {"AIN2_DMIC", NULL, "MIC_BIAS_2"}, 2284 {"AIN3_DMIC", NULL, "MIC_BIAS_2"}, 2285 2286 /* adc */ 2287 {"ADC_L", NULL, "ADC_L_Mux"}, 2288 {"ADC_L", NULL, "ADC_CLKGEN"}, 2289 {"ADC_L", NULL, "ADC_L_EN"}, 2290 {"ADC_R", NULL, "ADC_R_Mux"}, 2291 {"ADC_R", NULL, "ADC_CLKGEN"}, 2292 {"ADC_R", NULL, "ADC_R_EN"}, 2293 /* 2294 * amic fifo ch1/2 clk from ADC_L, 2295 * enable ADC_L even use ADC_R only 2296 */ 2297 {"ADC_R", NULL, "ADC_L_EN"}, 2298 {"ADC_3", NULL, "ADC_3_Mux"}, 2299 {"ADC_3", NULL, "ADC_CLKGEN"}, 2300 {"ADC_3", NULL, "ADC_3_EN"}, 2301 2302 {"ADC_L_Mux", "Left Preamplifier", "PGA_L"}, 2303 {"ADC_R_Mux", "Right Preamplifier", "PGA_R"}, 2304 {"ADC_3_Mux", "Preamplifier", "PGA_3"}, 2305 2306 {"PGA_L", NULL, "PGA_L_Mux"}, 2307 {"PGA_L", NULL, "PGA_L_EN"}, 2308 {"PGA_R", NULL, "PGA_R_Mux"}, 2309 {"PGA_R", NULL, "PGA_R_EN"}, 2310 {"PGA_3", NULL, "PGA_3_Mux"}, 2311 {"PGA_3", NULL, "PGA_3_EN"}, 2312 2313 {"PGA_L", NULL, "DCC_CLK", mt_dcc_clk_connect}, 2314 {"PGA_R", NULL, "DCC_CLK", mt_dcc_clk_connect}, 2315 {"PGA_3", NULL, "DCC_CLK", mt_dcc_clk_connect}, 2316 2317 {"PGA_L_Mux", "AIN0", "AIN0"}, 2318 {"PGA_L_Mux", "AIN1", "AIN1"}, 2319 2320 {"PGA_R_Mux", "AIN0", "AIN0"}, 2321 {"PGA_R_Mux", "AIN2", "AIN2"}, 2322 {"PGA_R_Mux", "AIN3", "AIN3"}, 2323 2324 {"PGA_3_Mux", "AIN2", "AIN2"}, 2325 {"PGA_3_Mux", "AIN3", "AIN3"}, 2326 2327 {"AIN0", NULL, "MIC_BIAS_0"}, 2328 {"AIN1", NULL, "MIC_BIAS_1"}, 2329 {"AIN2", NULL, "MIC_BIAS_0"}, 2330 {"AIN2", NULL, "MIC_BIAS_2"}, 2331 {"AIN3", NULL, "MIC_BIAS_2"}, 2332 2333 /* DL Supply */ 2334 {"DL Power Supply", NULL, "CLK_BUF"}, 2335 {"DL Power Supply", NULL, "LDO_VAUD18"}, 2336 {"DL Power Supply", NULL, "AUDGLB"}, 2337 {"DL Power Supply", NULL, "CLKSQ Audio"}, 2338 {"DL Power Supply", NULL, "AUDNCP_CK"}, 2339 {"DL Power Supply", NULL, "ZCD13M_CK"}, 2340 {"DL Power Supply", NULL, "AUD_CK"}, 2341 {"DL Power Supply", NULL, "AUDIF_CK"}, 2342 {"DL Power Supply", NULL, "ESD_RESIST"}, 2343 {"DL Power Supply", NULL, "LDO"}, 2344 {"DL Power Supply", NULL, "LDO_REMOTE"}, 2345 {"DL Power Supply", NULL, "NV_REGULATOR"}, 2346 {"DL Power Supply", NULL, "IBIST"}, 2347 2348 /* DL Digital Supply */ 2349 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, 2350 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, 2351 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, 2352 {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2353 {"DL Digital Clock", NULL, "SDM_FIFO_CLK"}, 2354 {"DL Digital Clock", NULL, "NCP"}, 2355 {"DL Digital Clock", NULL, "AFE_ON"}, 2356 {"DL Digital Clock", NULL, "AFE_DL_SRC"}, 2357 2358 {"DL Digital Clock CH_1_2", NULL, "DL Digital Clock"}, 2359 {"DL Digital Clock CH_1_2", NULL, "SDM"}, 2360 2361 {"DL Digital Clock CH_3", NULL, "DL Digital Clock"}, 2362 {"DL Digital Clock CH_3", NULL, "SDM_3RD"}, 2363 2364 {"AIF_RX", NULL, "DL Digital Clock CH_1_2"}, 2365 2366 {"AIF2_RX", NULL, "DL Digital Clock CH_3"}, 2367 2368 /* DL Path */ 2369 {"DAC In Mux", "Normal Path", "AIF_RX"}, 2370 {"DAC In Mux", "Sgen", "SGEN DL"}, 2371 {"SGEN DL", NULL, "SGEN DL SRC"}, 2372 {"SGEN DL", NULL, "SGEN MUTE"}, 2373 {"SGEN DL", NULL, "SGEN DL Enable"}, 2374 {"SGEN DL", NULL, "DL Digital Clock CH_1_2"}, 2375 {"SGEN DL", NULL, "DL Digital Clock CH_3"}, 2376 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"}, 2377 2378 {"DACL", NULL, "DAC In Mux"}, 2379 {"DACL", NULL, "DL Power Supply"}, 2380 2381 {"DACR", NULL, "DAC In Mux"}, 2382 {"DACR", NULL, "DL Power Supply"}, 2383 2384 /* DAC 3RD */ 2385 {"DAC In Mux", "Normal Path", "AIF2_RX"}, 2386 {"DAC_3RD", NULL, "DAC In Mux"}, 2387 {"DAC_3RD", NULL, "DL Power Supply"}, 2388 2389 /* Lineout Path */ 2390 {"LOL Mux", "Playback", "DAC_3RD"}, 2391 {"LINEOUT L", NULL, "LOL Mux"}, 2392 2393 /* Headphone Path */ 2394 {"HP_Supply", NULL, "HP_PULL_DOWN"}, 2395 {"HP_Supply", NULL, "HP_MUTE"}, 2396 {"HP_Supply", NULL, "HP_DAMP"}, 2397 {"HP Mux", NULL, "HP_Supply"}, 2398 2399 {"HP Mux", "Audio Playback", "DACL"}, 2400 {"HP Mux", "Audio Playback", "DACR"}, 2401 {"HP Mux", "HP Impedance", "DACL"}, 2402 {"HP Mux", "HP Impedance", "DACR"}, 2403 {"HP Mux", "LoudSPK Playback", "DACL"}, 2404 {"HP Mux", "LoudSPK Playback", "DACR"}, 2405 2406 {"Headphone L", NULL, "HP Mux"}, 2407 {"Headphone R", NULL, "HP Mux"}, 2408 {"Headphone L Ext Spk Amp", NULL, "HP Mux"}, 2409 {"Headphone R Ext Spk Amp", NULL, "HP Mux"}, 2410 2411 /* Receiver Path */ 2412 {"RCV Mux", "Voice Playback", "DACL"}, 2413 {"Receiver", NULL, "RCV Mux"}, 2414}; 2415 2416static int mt6359_codec_dai_hw_params(struct snd_pcm_substream *substream, 2417 struct snd_pcm_hw_params *params, 2418 struct snd_soc_dai *dai) 2419{ 2420 struct snd_soc_component *cmpnt = dai->component; 2421 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2422 unsigned int rate = params_rate(params); 2423 int id = dai->id; 2424 2425 dev_dbg(priv->dev, "%s(), id %d, substream->stream %d, rate %d, number %d\n", 2426 __func__, id, substream->stream, rate, substream->number); 2427 2428 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2429 priv->dl_rate[id] = rate; 2430 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2431 priv->ul_rate[id] = rate; 2432 2433 return 0; 2434} 2435 2436static int mt6359_codec_dai_startup(struct snd_pcm_substream *substream, 2437 struct snd_soc_dai *dai) 2438{ 2439 struct snd_soc_component *cmpnt = dai->component; 2440 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2441 2442 dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream); 2443 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2444 mt6359_set_playback_gpio(priv); 2445 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2446 mt6359_set_capture_gpio(priv); 2447 2448 return 0; 2449} 2450 2451static void mt6359_codec_dai_shutdown(struct snd_pcm_substream *substream, 2452 struct snd_soc_dai *dai) 2453{ 2454 struct snd_soc_component *cmpnt = dai->component; 2455 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2456 2457 dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream); 2458 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2459 mt6359_reset_playback_gpio(priv); 2460 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2461 mt6359_reset_capture_gpio(priv); 2462} 2463 2464static const struct snd_soc_dai_ops mt6359_codec_dai_ops = { 2465 .hw_params = mt6359_codec_dai_hw_params, 2466 .startup = mt6359_codec_dai_startup, 2467 .shutdown = mt6359_codec_dai_shutdown, 2468}; 2469 2470#define MT6359_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\ 2471 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\ 2472 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\ 2473 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\ 2474 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\ 2475 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE) 2476 2477static struct snd_soc_dai_driver mt6359_dai_driver[] = { 2478 { 2479 .id = MT6359_AIF_1, 2480 .name = "mt6359-snd-codec-aif1", 2481 .playback = { 2482 .stream_name = "AIF1 Playback", 2483 .channels_min = 1, 2484 .channels_max = 2, 2485 .rates = SNDRV_PCM_RATE_8000_48000 | 2486 SNDRV_PCM_RATE_96000 | 2487 SNDRV_PCM_RATE_192000, 2488 .formats = MT6359_FORMATS, 2489 }, 2490 .capture = { 2491 .stream_name = "AIF1 Capture", 2492 .channels_min = 1, 2493 .channels_max = 2, 2494 .rates = SNDRV_PCM_RATE_8000 | 2495 SNDRV_PCM_RATE_16000 | 2496 SNDRV_PCM_RATE_32000 | 2497 SNDRV_PCM_RATE_48000 | 2498 SNDRV_PCM_RATE_96000 | 2499 SNDRV_PCM_RATE_192000, 2500 .formats = MT6359_FORMATS, 2501 }, 2502 .ops = &mt6359_codec_dai_ops, 2503 }, 2504 { 2505 .id = MT6359_AIF_2, 2506 .name = "mt6359-snd-codec-aif2", 2507 .playback = { 2508 .stream_name = "AIF2 Playback", 2509 .channels_min = 1, 2510 .channels_max = 2, 2511 .rates = SNDRV_PCM_RATE_8000_48000 | 2512 SNDRV_PCM_RATE_96000 | 2513 SNDRV_PCM_RATE_192000, 2514 .formats = MT6359_FORMATS, 2515 }, 2516 .capture = { 2517 .stream_name = "AIF2 Capture", 2518 .channels_min = 1, 2519 .channels_max = 2, 2520 .rates = SNDRV_PCM_RATE_8000 | 2521 SNDRV_PCM_RATE_16000 | 2522 SNDRV_PCM_RATE_32000 | 2523 SNDRV_PCM_RATE_48000, 2524 .formats = MT6359_FORMATS, 2525 }, 2526 .ops = &mt6359_codec_dai_ops, 2527 }, 2528}; 2529 2530static int mt6359_codec_init_reg(struct snd_soc_component *cmpnt) 2531{ 2532 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2533 2534 /* enable clk buf */ 2535 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12, 2536 0x1 << RG_XO_AUDIO_EN_M_SFT, 2537 0x1 << RG_XO_AUDIO_EN_M_SFT); 2538 2539 /* set those not controlled by dapm widget */ 2540 2541 /* audio clk source from internal dcxo */ 2542 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23, 2543 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 2544 0x0); 2545 2546 /* Disable HeadphoneL/HeadphoneR short circuit protection */ 2547 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 2548 RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT, 2549 0x1 << RG_AUDHPLSCDISABLE_VAUDP32_SFT); 2550 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0, 2551 RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT, 2552 0x1 << RG_AUDHPRSCDISABLE_VAUDP32_SFT); 2553 /* Disable voice short circuit protection */ 2554 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6, 2555 RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT, 2556 0x1 << RG_AUDHSSCDISABLE_VAUDP32_SFT); 2557 /* disable LO buffer left short circuit protection */ 2558 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7, 2559 RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT, 2560 0x1 << RG_AUDLOLSCDISABLE_VAUDP32_SFT); 2561 2562 /* set gpio */ 2563 mt6359_reset_playback_gpio(priv); 2564 mt6359_reset_capture_gpio(priv); 2565 2566 /* hp hifi mode, default normal mode */ 2567 priv->hp_hifi_mode = 0; 2568 2569 /* Disable AUD_ZCD */ 2570 zcd_disable(priv); 2571 2572 /* disable clk buf */ 2573 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12, 2574 0x1 << RG_XO_AUDIO_EN_M_SFT, 2575 0x0 << RG_XO_AUDIO_EN_M_SFT); 2576 2577 return 0; 2578} 2579 2580static int mt6359_codec_probe(struct snd_soc_component *cmpnt) 2581{ 2582 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2583 2584 snd_soc_component_init_regmap(cmpnt, priv->regmap); 2585 2586 return mt6359_codec_init_reg(cmpnt); 2587} 2588 2589static void mt6359_codec_remove(struct snd_soc_component *cmpnt) 2590{ 2591 snd_soc_component_exit_regmap(cmpnt); 2592} 2593 2594static const DECLARE_TLV_DB_SCALE(hp_playback_tlv, -2200, 100, 0); 2595static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); 2596static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0); 2597 2598static const struct snd_kcontrol_new mt6359_snd_controls[] = { 2599 /* dl pga gain */ 2600 SOC_DOUBLE_EXT_TLV("Headset Volume", 2601 MT6359_ZCD_CON2, 0, 7, 0x1E, 0, 2602 snd_soc_get_volsw, mt6359_put_volsw, 2603 hp_playback_tlv), 2604 SOC_DOUBLE_EXT_TLV("Lineout Volume", 2605 MT6359_ZCD_CON1, 0, 7, 0x12, 0, 2606 snd_soc_get_volsw, mt6359_put_volsw, playback_tlv), 2607 SOC_SINGLE_EXT_TLV("Handset Volume", 2608 MT6359_ZCD_CON3, 0, 0x12, 0, 2609 snd_soc_get_volsw, mt6359_put_volsw, playback_tlv), 2610 2611 /* ul pga gain */ 2612 SOC_SINGLE_EXT_TLV("PGA1 Volume", 2613 MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0, 2614 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv), 2615 SOC_SINGLE_EXT_TLV("PGA2 Volume", 2616 MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0, 2617 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv), 2618 SOC_SINGLE_EXT_TLV("PGA3 Volume", 2619 MT6359_AUDENC_ANA_CON2, RG_AUDPREAMP3GAIN_SFT, 4, 0, 2620 snd_soc_get_volsw, mt6359_put_volsw, capture_tlv), 2621}; 2622 2623static const struct snd_soc_component_driver mt6359_soc_component_driver = { 2624 .name = CODEC_MT6359_NAME, 2625 .probe = mt6359_codec_probe, 2626 .remove = mt6359_codec_remove, 2627 .controls = mt6359_snd_controls, 2628 .num_controls = ARRAY_SIZE(mt6359_snd_controls), 2629 .dapm_widgets = mt6359_dapm_widgets, 2630 .num_dapm_widgets = ARRAY_SIZE(mt6359_dapm_widgets), 2631 .dapm_routes = mt6359_dapm_routes, 2632 .num_dapm_routes = ARRAY_SIZE(mt6359_dapm_routes), 2633}; 2634 2635static int mt6359_parse_dt(struct mt6359_priv *priv) 2636{ 2637 int ret; 2638 struct device *dev = priv->dev; 2639 struct device_node *np; 2640 2641 np = of_get_child_by_name(dev->parent->of_node, "mt6359codec"); 2642 if (!np) 2643 return -EINVAL; 2644 2645 ret = of_property_read_u32(np, "mediatek,dmic-mode", 2646 &priv->dmic_one_wire_mode); 2647 if (ret) { 2648 dev_warn(priv->dev, "%s() failed to read dmic-mode\n", 2649 __func__); 2650 priv->dmic_one_wire_mode = 0; 2651 } 2652 2653 ret = of_property_read_u32(np, "mediatek,mic-type-0", 2654 &priv->mux_select[MUX_MIC_TYPE_0]); 2655 if (ret) { 2656 dev_warn(priv->dev, "%s() failed to read mic-type-0\n", 2657 __func__); 2658 priv->mux_select[MUX_MIC_TYPE_0] = MIC_TYPE_MUX_IDLE; 2659 } 2660 2661 ret = of_property_read_u32(np, "mediatek,mic-type-1", 2662 &priv->mux_select[MUX_MIC_TYPE_1]); 2663 if (ret) { 2664 dev_warn(priv->dev, "%s() failed to read mic-type-1\n", 2665 __func__); 2666 priv->mux_select[MUX_MIC_TYPE_1] = MIC_TYPE_MUX_IDLE; 2667 } 2668 2669 ret = of_property_read_u32(np, "mediatek,mic-type-2", 2670 &priv->mux_select[MUX_MIC_TYPE_2]); 2671 if (ret) { 2672 dev_warn(priv->dev, "%s() failed to read mic-type-2\n", 2673 __func__); 2674 priv->mux_select[MUX_MIC_TYPE_2] = MIC_TYPE_MUX_IDLE; 2675 } 2676 2677 return 0; 2678} 2679 2680static int mt6359_platform_driver_probe(struct platform_device *pdev) 2681{ 2682 struct mt6359_priv *priv; 2683 int ret; 2684 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 2685 2686 dev_dbg(&pdev->dev, "%s(), dev name %s\n", 2687 __func__, dev_name(&pdev->dev)); 2688 2689 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2690 if (!priv) 2691 return -ENOMEM; 2692 2693 priv->regmap = mt6397->regmap; 2694 if (IS_ERR(priv->regmap)) 2695 return PTR_ERR(priv->regmap); 2696 2697 dev_set_drvdata(&pdev->dev, priv); 2698 priv->dev = &pdev->dev; 2699 2700 priv->avdd_reg = devm_regulator_get(&pdev->dev, "vaud18"); 2701 if (IS_ERR(priv->avdd_reg)) { 2702 dev_err(&pdev->dev, "%s(), have no vaud18 supply: %ld", 2703 __func__, PTR_ERR(priv->avdd_reg)); 2704 return PTR_ERR(priv->avdd_reg); 2705 } 2706 2707 ret = regulator_enable(priv->avdd_reg); 2708 if (ret) { 2709 dev_err(&pdev->dev, "%s(), failed to enable regulator!\n", 2710 __func__); 2711 return ret; 2712 } 2713 2714 ret = mt6359_parse_dt(priv); 2715 if (ret) { 2716 dev_warn(&pdev->dev, "%s() failed to parse dts\n", __func__); 2717 return ret; 2718 } 2719 2720 return devm_snd_soc_register_component(&pdev->dev, 2721 &mt6359_soc_component_driver, 2722 mt6359_dai_driver, 2723 ARRAY_SIZE(mt6359_dai_driver)); 2724} 2725 2726static int mt6359_platform_driver_remove(struct platform_device *pdev) 2727{ 2728 struct mt6359_priv *priv = dev_get_drvdata(&pdev->dev); 2729 int ret; 2730 2731 dev_dbg(&pdev->dev, "%s(), dev name %s\n", 2732 __func__, dev_name(&pdev->dev)); 2733 2734 ret = regulator_disable(priv->avdd_reg); 2735 if (ret) { 2736 dev_err(&pdev->dev, "%s(), failed to disable regulator!\n", 2737 __func__); 2738 return ret; 2739 } 2740 2741 return 0; 2742} 2743 2744static struct platform_driver mt6359_platform_driver = { 2745 .driver = { 2746 .name = "mt6359-sound", 2747 }, 2748 .probe = mt6359_platform_driver_probe, 2749 .remove = mt6359_platform_driver_remove, 2750}; 2751 2752module_platform_driver(mt6359_platform_driver) 2753 2754/* Module information */ 2755MODULE_DESCRIPTION("MT6359 ALSA SoC codec driver"); 2756MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 2757MODULE_AUTHOR("Eason Yen <eason.yen@mediatek.com>"); 2758MODULE_LICENSE("GPL v2"); 2759