1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * lm49453.c - LM49453 ALSA Soc Audio driver 4 * 5 * Copyright (c) 2012 Texas Instruments, Inc 6 * 7 * Initially based on sound/soc/codecs/wm8350.c 8 */ 9 10#include <linux/module.h> 11#include <linux/moduleparam.h> 12#include <linux/kernel.h> 13#include <linux/init.h> 14#include <linux/delay.h> 15#include <linux/pm.h> 16#include <linux/i2c.h> 17#include <linux/regmap.h> 18#include <linux/slab.h> 19#include <sound/core.h> 20#include <sound/pcm.h> 21#include <sound/pcm_params.h> 22#include <sound/soc.h> 23#include <sound/soc-dapm.h> 24#include <sound/tlv.h> 25#include <sound/jack.h> 26#include <sound/initval.h> 27#include <asm/div64.h> 28#include "lm49453.h" 29 30static const struct reg_default lm49453_reg_defs[] = { 31 { 0, 0x00 }, 32 { 1, 0x00 }, 33 { 2, 0x00 }, 34 { 3, 0x00 }, 35 { 4, 0x00 }, 36 { 5, 0x00 }, 37 { 6, 0x00 }, 38 { 7, 0x00 }, 39 { 8, 0x00 }, 40 { 9, 0x00 }, 41 { 10, 0x00 }, 42 { 11, 0x00 }, 43 { 12, 0x00 }, 44 { 13, 0x00 }, 45 { 14, 0x00 }, 46 { 15, 0x00 }, 47 { 16, 0x00 }, 48 { 17, 0x00 }, 49 { 18, 0x00 }, 50 { 19, 0x00 }, 51 { 20, 0x00 }, 52 { 21, 0x00 }, 53 { 22, 0x00 }, 54 { 23, 0x00 }, 55 { 32, 0x00 }, 56 { 33, 0x00 }, 57 { 35, 0x00 }, 58 { 36, 0x00 }, 59 { 37, 0x00 }, 60 { 46, 0x00 }, 61 { 48, 0x00 }, 62 { 49, 0x00 }, 63 { 51, 0x00 }, 64 { 56, 0x00 }, 65 { 58, 0x00 }, 66 { 59, 0x00 }, 67 { 60, 0x00 }, 68 { 61, 0x00 }, 69 { 62, 0x00 }, 70 { 63, 0x00 }, 71 { 64, 0x00 }, 72 { 65, 0x00 }, 73 { 66, 0x00 }, 74 { 67, 0x00 }, 75 { 68, 0x00 }, 76 { 69, 0x00 }, 77 { 70, 0x00 }, 78 { 71, 0x00 }, 79 { 72, 0x00 }, 80 { 73, 0x00 }, 81 { 74, 0x00 }, 82 { 75, 0x00 }, 83 { 76, 0x00 }, 84 { 77, 0x00 }, 85 { 78, 0x00 }, 86 { 79, 0x00 }, 87 { 80, 0x00 }, 88 { 81, 0x00 }, 89 { 82, 0x00 }, 90 { 83, 0x00 }, 91 { 85, 0x00 }, 92 { 85, 0x00 }, 93 { 86, 0x00 }, 94 { 87, 0x00 }, 95 { 88, 0x00 }, 96 { 89, 0x00 }, 97 { 90, 0x00 }, 98 { 91, 0x00 }, 99 { 92, 0x00 }, 100 { 93, 0x00 }, 101 { 94, 0x00 }, 102 { 95, 0x00 }, 103 { 96, 0x01 }, 104 { 97, 0x00 }, 105 { 98, 0x00 }, 106 { 99, 0x00 }, 107 { 100, 0x00 }, 108 { 101, 0x00 }, 109 { 102, 0x00 }, 110 { 103, 0x01 }, 111 { 104, 0x01 }, 112 { 105, 0x00 }, 113 { 106, 0x01 }, 114 { 107, 0x00 }, 115 { 108, 0x00 }, 116 { 109, 0x00 }, 117 { 110, 0x00 }, 118 { 111, 0x02 }, 119 { 112, 0x02 }, 120 { 113, 0x00 }, 121 { 121, 0x80 }, 122 { 122, 0xBB }, 123 { 123, 0x80 }, 124 { 124, 0xBB }, 125 { 128, 0x00 }, 126 { 130, 0x00 }, 127 { 131, 0x00 }, 128 { 132, 0x00 }, 129 { 133, 0x0A }, 130 { 134, 0x0A }, 131 { 135, 0x0A }, 132 { 136, 0x0F }, 133 { 137, 0x00 }, 134 { 138, 0x73 }, 135 { 139, 0x33 }, 136 { 140, 0x73 }, 137 { 141, 0x33 }, 138 { 142, 0x73 }, 139 { 143, 0x33 }, 140 { 144, 0x73 }, 141 { 145, 0x33 }, 142 { 146, 0x73 }, 143 { 147, 0x33 }, 144 { 148, 0x73 }, 145 { 149, 0x33 }, 146 { 150, 0x73 }, 147 { 151, 0x33 }, 148 { 152, 0x00 }, 149 { 153, 0x00 }, 150 { 154, 0x00 }, 151 { 155, 0x00 }, 152 { 176, 0x00 }, 153 { 177, 0x00 }, 154 { 178, 0x00 }, 155 { 179, 0x00 }, 156 { 180, 0x00 }, 157 { 181, 0x00 }, 158 { 182, 0x00 }, 159 { 183, 0x00 }, 160 { 184, 0x00 }, 161 { 185, 0x00 }, 162 { 186, 0x00 }, 163 { 187, 0x00 }, 164 { 188, 0x00 }, 165 { 189, 0x00 }, 166 { 208, 0x06 }, 167 { 209, 0x00 }, 168 { 210, 0x08 }, 169 { 211, 0x54 }, 170 { 212, 0x14 }, 171 { 213, 0x0d }, 172 { 214, 0x0d }, 173 { 215, 0x14 }, 174 { 216, 0x60 }, 175 { 221, 0x00 }, 176 { 222, 0x00 }, 177 { 223, 0x00 }, 178 { 224, 0x00 }, 179 { 248, 0x00 }, 180 { 249, 0x00 }, 181 { 250, 0x00 }, 182 { 255, 0x00 }, 183}; 184 185/* codec private data */ 186struct lm49453_priv { 187 struct regmap *regmap; 188}; 189 190/* capture path controls */ 191 192static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"}; 193 194static SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5, 195 lm49453_mic2mode_text); 196 197static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"}; 198 199static SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum, 200 LM49453_P0_DIGITAL_MIC1_CONFIG_REG, 7, 201 lm49453_dmic_cfg_text); 202 203static SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum, 204 LM49453_P0_DIGITAL_MIC2_CONFIG_REG, 7, 205 lm49453_dmic_cfg_text); 206 207/* MUX Controls */ 208static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" }; 209 210static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" }; 211 212static SOC_ENUM_SINGLE_DECL(lm49453_adcl_enum, 213 LM49453_P0_ANALOG_MIXER_ADC_REG, 0, 214 lm49453_adcl_mux_text); 215 216static SOC_ENUM_SINGLE_DECL(lm49453_adcr_enum, 217 LM49453_P0_ANALOG_MIXER_ADC_REG, 1, 218 lm49453_adcr_mux_text); 219 220static const struct snd_kcontrol_new lm49453_adcl_mux_control = 221 SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum); 222 223static const struct snd_kcontrol_new lm49453_adcr_mux_control = 224 SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum); 225 226static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = { 227SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0), 228SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0), 229SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0), 230SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0), 231SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0), 232SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0), 233SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0), 234SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0), 235SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0), 236SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0), 237SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0), 238SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0), 239SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0), 240SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0), 241SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0), 242SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0), 243SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0), 244}; 245 246static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = { 247SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0), 248SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0), 249SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0), 250SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0), 251SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0), 252SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0), 253SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0), 254SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0), 255SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0), 256SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0), 257SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0), 258SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0), 259SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0), 260SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0), 261SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0), 262SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0), 263SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0), 264}; 265 266static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = { 267SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0), 268SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0), 269SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0), 270SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0), 271SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0), 272SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0), 273SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0), 274SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0), 275SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0), 276SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0), 277SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0), 278SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0), 279SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0), 280SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0), 281SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0), 282SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0), 283SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0), 284}; 285 286static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = { 287SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0), 288SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0), 289SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0), 290SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0), 291SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0), 292SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0), 293SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0), 294SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0), 295SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0), 296SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0), 297SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0), 298SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0), 299SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0), 300SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0), 301SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0), 302SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0), 303SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0), 304}; 305 306static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = { 307SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0), 308SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0), 309SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0), 310SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0), 311SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0), 312SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0), 313SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0), 314SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0), 315SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0), 316SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0), 317SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0), 318SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0), 319SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0), 320SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0), 321SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0), 322SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0), 323SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0), 324}; 325 326static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = { 327SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0), 328SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0), 329SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0), 330SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0), 331SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0), 332SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0), 333SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0), 334SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0), 335SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0), 336SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0), 337SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0), 338SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0), 339SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0), 340SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0), 341SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0), 342SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0), 343SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0), 344}; 345 346static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = { 347SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0), 348SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0), 349SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0), 350SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0), 351SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0), 352SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0), 353SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0), 354SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0), 355SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0), 356SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0), 357SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0), 358SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0), 359SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0), 360SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0), 361SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0), 362SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0), 363SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0), 364}; 365 366static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = { 367SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0), 368SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0), 369SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0), 370SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0), 371SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0), 372SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0), 373SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0), 374SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0), 375SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0), 376SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0), 377SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0), 378SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0), 379SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0), 380SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0), 381SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0), 382SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0), 383SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0), 384}; 385 386static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = { 387SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0), 388SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0), 389SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0), 390SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0), 391SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0), 392SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0), 393SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0), 394SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0), 395}; 396 397static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = { 398SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0), 399SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0), 400SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0), 401SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0), 402SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0), 403SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0), 404SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0), 405SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0), 406}; 407 408static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = { 409SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0), 410SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0), 411SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0), 412SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0), 413SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0), 414SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0), 415SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0), 416}; 417 418static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = { 419SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0), 420SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0), 421SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0), 422SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0), 423SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0), 424SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0), 425SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0), 426}; 427 428static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = { 429SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0), 430SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0), 431SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0), 432SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0), 433SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0), 434SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0), 435SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0), 436}; 437 438static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = { 439SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0), 440SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0), 441SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0), 442SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0), 443SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0), 444SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0), 445SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0), 446}; 447 448static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = { 449SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0), 450SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0), 451SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0), 452SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0), 453SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0), 454SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0), 455SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0), 456}; 457 458static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = { 459SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0), 460SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0), 461SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0), 462SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0), 463SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0), 464SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0), 465SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0), 466}; 467 468static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = { 469SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0), 470SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0), 471SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0), 472SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0), 473SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0), 474SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0), 475SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0), 476SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0), 477}; 478 479static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = { 480SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0), 481SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0), 482SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0), 483SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0), 484SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0), 485SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0), 486SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0), 487SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0), 488}; 489 490/* TLV Declarations */ 491static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1); 492static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1); 493static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0); 494static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0); 495 496static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = { 497/* Sidetone supports mono only */ 498SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG, 499 0, 0x3F, 0, stn_tlv), 500SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG, 501 0, 0x3F, 0, stn_tlv), 502SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG, 503 0, 0x3F, 0, stn_tlv), 504SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG, 505 0, 0x3F, 0, stn_tlv), 506SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG, 507 0, 0x3F, 0, stn_tlv), 508SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG, 509 0, 0x3F, 0, stn_tlv), 510}; 511 512static const struct snd_kcontrol_new lm49453_snd_controls[] = { 513 /* mic1 and mic2 supports mono only */ 514 SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv), 515 SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv), 516 517 SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63, 518 0, adc_dac_tlv), 519 SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63, 520 0, adc_dac_tlv), 521 522 SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG, 523 LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv), 524 SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG, 525 LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv), 526 527 SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum), 528 SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum), 529 SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum), 530 531 /* Capture path filter enable */ 532 SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG, 533 0, 1, 0), 534 SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG, 535 1, 1, 0), 536 SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG, 537 2, 1, 0), 538 539 SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG, 540 LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv), 541 SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG, 542 LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv), 543 SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG, 544 LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv), 545 SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG, 546 LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv), 547 548 SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG, 549 0, 63, 0, adc_dac_tlv), 550 551 SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG, 552 0, 3, 0, port_tlv), 553 SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG, 554 2, 3, 0, port_tlv), 555 SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG, 556 4, 3, 0, port_tlv), 557 SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG, 558 6, 3, 0, port_tlv), 559 SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG, 560 0, 3, 0, port_tlv), 561 SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG, 562 2, 3, 0, port_tlv), 563 SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG, 564 4, 3, 0, port_tlv), 565 SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG, 566 6, 3, 0, port_tlv), 567 568 SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG, 569 0, 3, 0, port_tlv), 570 SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG, 571 2, 3, 0, port_tlv), 572 573 SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG, 574 1, 1, 0), 575 SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG, 576 1, 1, 0), 577 SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG, 578 2, 1, 0), 579 SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG, 580 2, 1, 0) 581 582}; 583 584/* DAPM widgets */ 585static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = { 586 587 /* All end points HP,EP, LS, Lineout and Haptic */ 588 SND_SOC_DAPM_OUTPUT("HPOUTL"), 589 SND_SOC_DAPM_OUTPUT("HPOUTR"), 590 SND_SOC_DAPM_OUTPUT("EPOUT"), 591 SND_SOC_DAPM_OUTPUT("LSOUTL"), 592 SND_SOC_DAPM_OUTPUT("LSOUTR"), 593 SND_SOC_DAPM_OUTPUT("LOOUTR"), 594 SND_SOC_DAPM_OUTPUT("LOOUTL"), 595 SND_SOC_DAPM_OUTPUT("HAOUTL"), 596 SND_SOC_DAPM_OUTPUT("HAOUTR"), 597 598 SND_SOC_DAPM_INPUT("AMIC1"), 599 SND_SOC_DAPM_INPUT("AMIC2"), 600 SND_SOC_DAPM_INPUT("DMIC1DAT"), 601 SND_SOC_DAPM_INPUT("DMIC2DAT"), 602 SND_SOC_DAPM_INPUT("AUXL"), 603 SND_SOC_DAPM_INPUT("AUXR"), 604 605 SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 606 SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 607 SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 608 SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 609 SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 610 SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 611 SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 612 SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 613 SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 614 SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0), 615 616 SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0), 617 SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0), 618 619 /* playback path driver enables */ 620 SND_SOC_DAPM_OUT_DRV("Headset Switch", 621 LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0), 622 SND_SOC_DAPM_OUT_DRV("Earpiece Switch", 623 LM49453_P0_EP_REG, 0, 0, NULL, 0), 624 SND_SOC_DAPM_OUT_DRV("Speaker Left Switch", 625 LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0), 626 SND_SOC_DAPM_OUT_DRV("Speaker Right Switch", 627 LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0), 628 SND_SOC_DAPM_OUT_DRV("Haptic Left Switch", 629 LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0), 630 SND_SOC_DAPM_OUT_DRV("Haptic Right Switch", 631 LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0), 632 633 /* DAC */ 634 SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0), 635 SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0), 636 SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0), 637 SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0), 638 SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0), 639 SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0), 640 SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0), 641 SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0), 642 643 644 SND_SOC_DAPM_PGA("AUXL Input", 645 LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0), 646 SND_SOC_DAPM_PGA("AUXR Input", 647 LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0), 648 649 SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0), 650 651 /* ADC */ 652 SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0), 653 SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0), 654 SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0), 655 SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0), 656 657 SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0), 658 SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0), 659 660 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0, 661 &lm49453_adcl_mux_control), 662 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, 663 &lm49453_adcr_mux_control), 664 665 SND_SOC_DAPM_MUX("Mic1 Input", 666 SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control), 667 668 SND_SOC_DAPM_MUX("Mic2 Input", 669 SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control), 670 671 /* AIF */ 672 SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0, 673 LM49453_P0_PULL_CONFIG1_REG, 2, 0), 674 SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0, 675 LM49453_P0_PULL_CONFIG1_REG, 6, 0), 676 677 SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0, 678 LM49453_P0_PULL_CONFIG1_REG, 3, 0), 679 SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0, 680 LM49453_P0_PULL_CONFIG1_REG, 7, 0), 681 682 /* Port1 TX controls */ 683 SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 684 SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 685 SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 686 SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 687 SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 688 SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 689 SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 690 SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 691 692 /* Port2 TX controls */ 693 SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 694 SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0), 695 696 /* Sidetone Mixer */ 697 SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0, 698 lm49453_sidetone_mixer_controls, 699 ARRAY_SIZE(lm49453_sidetone_mixer_controls)), 700 701 /* DAC MIXERS */ 702 SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0, 703 lm49453_headset_left_mixer, 704 ARRAY_SIZE(lm49453_headset_left_mixer)), 705 SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0, 706 lm49453_headset_right_mixer, 707 ARRAY_SIZE(lm49453_headset_right_mixer)), 708 SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0, 709 lm49453_lineout_left_mixer, 710 ARRAY_SIZE(lm49453_lineout_left_mixer)), 711 SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0, 712 lm49453_lineout_right_mixer, 713 ARRAY_SIZE(lm49453_lineout_right_mixer)), 714 SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0, 715 lm49453_speaker_left_mixer, 716 ARRAY_SIZE(lm49453_speaker_left_mixer)), 717 SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0, 718 lm49453_speaker_right_mixer, 719 ARRAY_SIZE(lm49453_speaker_right_mixer)), 720 SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0, 721 lm49453_haptic_left_mixer, 722 ARRAY_SIZE(lm49453_haptic_left_mixer)), 723 SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0, 724 lm49453_haptic_right_mixer, 725 ARRAY_SIZE(lm49453_haptic_right_mixer)), 726 727 /* Capture Mixer */ 728 SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0, 729 lm49453_port1_tx1_mixer, 730 ARRAY_SIZE(lm49453_port1_tx1_mixer)), 731 SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0, 732 lm49453_port1_tx2_mixer, 733 ARRAY_SIZE(lm49453_port1_tx2_mixer)), 734 SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0, 735 lm49453_port1_tx3_mixer, 736 ARRAY_SIZE(lm49453_port1_tx3_mixer)), 737 SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0, 738 lm49453_port1_tx4_mixer, 739 ARRAY_SIZE(lm49453_port1_tx4_mixer)), 740 SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0, 741 lm49453_port1_tx5_mixer, 742 ARRAY_SIZE(lm49453_port1_tx5_mixer)), 743 SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0, 744 lm49453_port1_tx6_mixer, 745 ARRAY_SIZE(lm49453_port1_tx6_mixer)), 746 SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0, 747 lm49453_port1_tx7_mixer, 748 ARRAY_SIZE(lm49453_port1_tx7_mixer)), 749 SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0, 750 lm49453_port1_tx8_mixer, 751 ARRAY_SIZE(lm49453_port1_tx8_mixer)), 752 753 SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0, 754 lm49453_port2_tx1_mixer, 755 ARRAY_SIZE(lm49453_port2_tx1_mixer)), 756 SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0, 757 lm49453_port2_tx2_mixer, 758 ARRAY_SIZE(lm49453_port2_tx2_mixer)), 759}; 760 761static const struct snd_soc_dapm_route lm49453_audio_map[] = { 762 /* Port SDI mapping */ 763 { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" }, 764 { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" }, 765 { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" }, 766 { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" }, 767 { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" }, 768 { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" }, 769 { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" }, 770 { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" }, 771 772 { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" }, 773 { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" }, 774 775 /* HP mapping */ 776 { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" }, 777 { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" }, 778 { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" }, 779 { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" }, 780 { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" }, 781 { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" }, 782 { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" }, 783 { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" }, 784 785 { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" }, 786 { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" }, 787 788 { "HPL Mixer", "ADCL Switch", "ADC Left" }, 789 { "HPL Mixer", "ADCR Switch", "ADC Right" }, 790 { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" }, 791 { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" }, 792 { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" }, 793 { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" }, 794 { "HPL Mixer", "Sidetone Switch", "Sidetone" }, 795 796 { "HPL DAC", NULL, "HPL Mixer" }, 797 798 { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" }, 799 { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" }, 800 { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" }, 801 { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" }, 802 { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" }, 803 { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" }, 804 { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" }, 805 { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" }, 806 807 /* Port 2 */ 808 { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" }, 809 { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" }, 810 811 { "HPR Mixer", "ADCL Switch", "ADC Left" }, 812 { "HPR Mixer", "ADCR Switch", "ADC Right" }, 813 { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" }, 814 { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" }, 815 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" }, 816 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" }, 817 { "HPR Mixer", "Sidetone Switch", "Sidetone" }, 818 819 { "HPR DAC", NULL, "HPR Mixer" }, 820 821 { "HPOUTL", "Headset Switch", "HPL DAC"}, 822 { "HPOUTR", "Headset Switch", "HPR DAC"}, 823 824 /* EP map */ 825 { "EPOUT", "Earpiece Switch", "HPL DAC" }, 826 827 /* Speaker map */ 828 { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" }, 829 { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" }, 830 { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" }, 831 { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" }, 832 { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" }, 833 { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" }, 834 { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" }, 835 { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" }, 836 837 /* Port 2 */ 838 { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" }, 839 { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" }, 840 841 { "LSL Mixer", "ADCL Switch", "ADC Left" }, 842 { "LSL Mixer", "ADCR Switch", "ADC Right" }, 843 { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" }, 844 { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" }, 845 { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" }, 846 { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" }, 847 { "LSL Mixer", "Sidetone Switch", "Sidetone" }, 848 849 { "LSL DAC", NULL, "LSL Mixer" }, 850 851 { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" }, 852 { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" }, 853 { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" }, 854 { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" }, 855 { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" }, 856 { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" }, 857 { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" }, 858 { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" }, 859 860 /* Port 2 */ 861 { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" }, 862 { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" }, 863 864 { "LSR Mixer", "ADCL Switch", "ADC Left" }, 865 { "LSR Mixer", "ADCR Switch", "ADC Right" }, 866 { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" }, 867 { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" }, 868 { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" }, 869 { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" }, 870 { "LSR Mixer", "Sidetone Switch", "Sidetone" }, 871 872 { "LSR DAC", NULL, "LSR Mixer" }, 873 874 { "LSOUTL", "Speaker Left Switch", "LSL DAC"}, 875 { "LSOUTR", "Speaker Left Switch", "LSR DAC"}, 876 877 /* Haptic map */ 878 { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" }, 879 { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" }, 880 { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" }, 881 { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" }, 882 { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" }, 883 { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" }, 884 { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" }, 885 { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" }, 886 887 /* Port 2 */ 888 { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" }, 889 { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" }, 890 891 { "HAL Mixer", "ADCL Switch", "ADC Left" }, 892 { "HAL Mixer", "ADCR Switch", "ADC Right" }, 893 { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" }, 894 { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" }, 895 { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" }, 896 { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" }, 897 { "HAL Mixer", "Sidetone Switch", "Sidetone" }, 898 899 { "HAL DAC", NULL, "HAL Mixer" }, 900 901 { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" }, 902 { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" }, 903 { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" }, 904 { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" }, 905 { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" }, 906 { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" }, 907 { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" }, 908 { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" }, 909 910 /* Port 2 */ 911 { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" }, 912 { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" }, 913 914 { "HAR Mixer", "ADCL Switch", "ADC Left" }, 915 { "HAR Mixer", "ADCR Switch", "ADC Right" }, 916 { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" }, 917 { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" }, 918 { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" }, 919 { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" }, 920 { "HAR Mixer", "Sideton Switch", "Sidetone" }, 921 922 { "HAR DAC", NULL, "HAR Mixer" }, 923 924 { "HAOUTL", "Haptic Left Switch", "HAL DAC" }, 925 { "HAOUTR", "Haptic Right Switch", "HAR DAC" }, 926 927 /* Lineout map */ 928 { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" }, 929 { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" }, 930 { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" }, 931 { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" }, 932 { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" }, 933 { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" }, 934 { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" }, 935 { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" }, 936 937 /* Port 2 */ 938 { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" }, 939 { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" }, 940 941 { "LOL Mixer", "ADCL Switch", "ADC Left" }, 942 { "LOL Mixer", "ADCR Switch", "ADC Right" }, 943 { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" }, 944 { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" }, 945 { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" }, 946 { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" }, 947 { "LOL Mixer", "Sidetone Switch", "Sidetone" }, 948 949 { "LOL DAC", NULL, "LOL Mixer" }, 950 951 { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" }, 952 { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" }, 953 { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" }, 954 { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" }, 955 { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" }, 956 { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" }, 957 { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" }, 958 { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" }, 959 960 /* Port 2 */ 961 { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" }, 962 { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" }, 963 964 { "LOR Mixer", "ADCL Switch", "ADC Left" }, 965 { "LOR Mixer", "ADCR Switch", "ADC Right" }, 966 { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" }, 967 { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" }, 968 { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" }, 969 { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" }, 970 { "LOR Mixer", "Sidetone Switch", "Sidetone" }, 971 972 { "LOR DAC", NULL, "LOR Mixer" }, 973 974 { "LOOUTL", NULL, "LOL DAC" }, 975 { "LOOUTR", NULL, "LOR DAC" }, 976 977 /* TX map */ 978 /* Port1 mappings */ 979 { "Port1_1 Mixer", "ADCL Switch", "ADC Left" }, 980 { "Port1_1 Mixer", "ADCR Switch", "ADC Right" }, 981 { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 982 { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 983 { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 984 { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 985 986 { "Port1_2 Mixer", "ADCL Switch", "ADC Left" }, 987 { "Port1_2 Mixer", "ADCR Switch", "ADC Right" }, 988 { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 989 { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 990 { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 991 { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 992 993 { "Port1_3 Mixer", "ADCL Switch", "ADC Left" }, 994 { "Port1_3 Mixer", "ADCR Switch", "ADC Right" }, 995 { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 996 { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 997 { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 998 { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 999 1000 { "Port1_4 Mixer", "ADCL Switch", "ADC Left" }, 1001 { "Port1_4 Mixer", "ADCR Switch", "ADC Right" }, 1002 { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 1003 { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 1004 { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 1005 { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 1006 1007 { "Port1_5 Mixer", "ADCL Switch", "ADC Left" }, 1008 { "Port1_5 Mixer", "ADCR Switch", "ADC Right" }, 1009 { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 1010 { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 1011 { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 1012 { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 1013 1014 { "Port1_6 Mixer", "ADCL Switch", "ADC Left" }, 1015 { "Port1_6 Mixer", "ADCR Switch", "ADC Right" }, 1016 { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 1017 { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 1018 { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 1019 { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 1020 1021 { "Port1_7 Mixer", "ADCL Switch", "ADC Left" }, 1022 { "Port1_7 Mixer", "ADCR Switch", "ADC Right" }, 1023 { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 1024 { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 1025 { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 1026 { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 1027 1028 { "Port1_8 Mixer", "ADCL Switch", "ADC Left" }, 1029 { "Port1_8 Mixer", "ADCR Switch", "ADC Right" }, 1030 { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 1031 { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 1032 { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 1033 { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 1034 1035 { "Port2_1 Mixer", "ADCL Switch", "ADC Left" }, 1036 { "Port2_1 Mixer", "ADCR Switch", "ADC Right" }, 1037 { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 1038 { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 1039 { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 1040 { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 1041 1042 { "Port2_2 Mixer", "ADCL Switch", "ADC Left" }, 1043 { "Port2_2 Mixer", "ADCR Switch", "ADC Right" }, 1044 { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" }, 1045 { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" }, 1046 { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" }, 1047 { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" }, 1048 1049 { "P1_1_TX", NULL, "Port1_1 Mixer" }, 1050 { "P1_2_TX", NULL, "Port1_2 Mixer" }, 1051 { "P1_3_TX", NULL, "Port1_3 Mixer" }, 1052 { "P1_4_TX", NULL, "Port1_4 Mixer" }, 1053 { "P1_5_TX", NULL, "Port1_5 Mixer" }, 1054 { "P1_6_TX", NULL, "Port1_6 Mixer" }, 1055 { "P1_7_TX", NULL, "Port1_7 Mixer" }, 1056 { "P1_8_TX", NULL, "Port1_8 Mixer" }, 1057 1058 { "P2_1_TX", NULL, "Port2_1 Mixer" }, 1059 { "P2_2_TX", NULL, "Port2_2 Mixer" }, 1060 1061 { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"}, 1062 { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"}, 1063 { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"}, 1064 { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"}, 1065 { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"}, 1066 { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"}, 1067 { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"}, 1068 { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"}, 1069 1070 { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"}, 1071 { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"}, 1072 1073 { "Mic1 Input", NULL, "AMIC1" }, 1074 { "Mic2 Input", NULL, "AMIC2" }, 1075 1076 { "AUXL Input", NULL, "AUXL" }, 1077 { "AUXR Input", NULL, "AUXR" }, 1078 1079 /* AUX connections */ 1080 { "ADCL Mux", "Aux_L", "AUXL Input" }, 1081 { "ADCL Mux", "MIC1", "Mic1 Input" }, 1082 1083 { "ADCR Mux", "Aux_R", "AUXR Input" }, 1084 { "ADCR Mux", "MIC2", "Mic2 Input" }, 1085 1086 /* ADC connection */ 1087 { "ADC Left", NULL, "ADCL Mux"}, 1088 { "ADC Right", NULL, "ADCR Mux"}, 1089 1090 { "DMIC1 Left", NULL, "DMIC1DAT"}, 1091 { "DMIC1 Right", NULL, "DMIC1DAT"}, 1092 { "DMIC2 Left", NULL, "DMIC2DAT"}, 1093 { "DMIC2 Right", NULL, "DMIC2DAT"}, 1094 1095 /* Sidetone map */ 1096 { "Sidetone Mixer", NULL, "ADC Left" }, 1097 { "Sidetone Mixer", NULL, "ADC Right" }, 1098 { "Sidetone Mixer", NULL, "DMIC1 Left" }, 1099 { "Sidetone Mixer", NULL, "DMIC1 Right" }, 1100 { "Sidetone Mixer", NULL, "DMIC2 Left" }, 1101 { "Sidetone Mixer", NULL, "DMIC2 Right" }, 1102 1103 { "Sidetone", "Sidetone Switch", "Sidetone Mixer" }, 1104}; 1105 1106static int lm49453_hw_params(struct snd_pcm_substream *substream, 1107 struct snd_pcm_hw_params *params, 1108 struct snd_soc_dai *dai) 1109{ 1110 struct snd_soc_component *component = dai->component; 1111 u16 clk_div = 0; 1112 1113 /* Setting DAC clock dividers based on substream sample rate. */ 1114 switch (params_rate(params)) { 1115 case 8000: 1116 case 16000: 1117 case 32000: 1118 case 24000: 1119 case 48000: 1120 clk_div = 256; 1121 break; 1122 case 11025: 1123 case 22050: 1124 case 44100: 1125 clk_div = 216; 1126 break; 1127 case 96000: 1128 clk_div = 127; 1129 break; 1130 default: 1131 return -EINVAL; 1132 } 1133 1134 snd_soc_component_write(component, LM49453_P0_ADC_CLK_DIV_REG, clk_div); 1135 snd_soc_component_write(component, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div); 1136 1137 return 0; 1138} 1139 1140static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1141{ 1142 struct snd_soc_component *component = codec_dai->component; 1143 1144 u16 aif_val; 1145 int mode = 0; 1146 int clk_phase = 0; 1147 int clk_shift = 0; 1148 1149 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1150 case SND_SOC_DAIFMT_CBS_CFS: 1151 aif_val = 0; 1152 break; 1153 case SND_SOC_DAIFMT_CBS_CFM: 1154 aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS; 1155 break; 1156 case SND_SOC_DAIFMT_CBM_CFS: 1157 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS; 1158 break; 1159 case SND_SOC_DAIFMT_CBM_CFM: 1160 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS | 1161 LM49453_AUDIO_PORT1_BASIC_SYNC_MS; 1162 break; 1163 default: 1164 return -EINVAL; 1165 } 1166 1167 1168 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1169 case SND_SOC_DAIFMT_I2S: 1170 break; 1171 case SND_SOC_DAIFMT_DSP_A: 1172 mode = 1; 1173 clk_phase = (1 << 5); 1174 clk_shift = 1; 1175 break; 1176 case SND_SOC_DAIFMT_DSP_B: 1177 mode = 1; 1178 clk_phase = (1 << 5); 1179 clk_shift = 0; 1180 break; 1181 default: 1182 return -EINVAL; 1183 } 1184 1185 snd_soc_component_update_bits(component, LM49453_P0_AUDIO_PORT1_BASIC_REG, 1186 LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5), 1187 (aif_val | mode | clk_phase)); 1188 1189 snd_soc_component_write(component, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift); 1190 1191 return 0; 1192} 1193 1194static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 1195 unsigned int freq, int dir) 1196{ 1197 struct snd_soc_component *component = dai->component; 1198 u16 pll_clk = 0; 1199 1200 switch (freq) { 1201 case 12288000: 1202 case 26000000: 1203 case 19200000: 1204 /* pll clk slection */ 1205 pll_clk = 0; 1206 break; 1207 case 48000: 1208 case 32576: 1209 /* fll clk slection */ 1210 pll_clk = BIT(4); 1211 return 0; 1212 default: 1213 return -EINVAL; 1214 } 1215 1216 snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk); 1217 1218 return 0; 1219} 1220 1221static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute, int direction) 1222{ 1223 snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0), 1224 (mute ? (BIT(1)|BIT(0)) : 0)); 1225 return 0; 1226} 1227 1228static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute, int direction) 1229{ 1230 snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2), 1231 (mute ? (BIT(3)|BIT(2)) : 0)); 1232 return 0; 1233} 1234 1235static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute, int direction) 1236{ 1237 snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4), 1238 (mute ? (BIT(5)|BIT(4)) : 0)); 1239 return 0; 1240} 1241 1242static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute, int direction) 1243{ 1244 snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(4), 1245 (mute ? BIT(4) : 0)); 1246 return 0; 1247} 1248 1249static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute, int direction) 1250{ 1251 snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6), 1252 (mute ? (BIT(7)|BIT(6)) : 0)); 1253 return 0; 1254} 1255 1256static int lm49453_set_bias_level(struct snd_soc_component *component, 1257 enum snd_soc_bias_level level) 1258{ 1259 struct lm49453_priv *lm49453 = snd_soc_component_get_drvdata(component); 1260 1261 switch (level) { 1262 case SND_SOC_BIAS_ON: 1263 case SND_SOC_BIAS_PREPARE: 1264 break; 1265 1266 case SND_SOC_BIAS_STANDBY: 1267 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 1268 regcache_sync(lm49453->regmap); 1269 1270 snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG, 1271 LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN); 1272 break; 1273 1274 case SND_SOC_BIAS_OFF: 1275 snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG, 1276 LM49453_PMC_SETUP_CHIP_EN, 0); 1277 break; 1278 } 1279 1280 return 0; 1281} 1282 1283/* Formates supported by LM49453 driver. */ 1284#define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1285 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1286 1287static const struct snd_soc_dai_ops lm49453_headset_dai_ops = { 1288 .hw_params = lm49453_hw_params, 1289 .set_sysclk = lm49453_set_dai_sysclk, 1290 .set_fmt = lm49453_set_dai_fmt, 1291 .mute_stream = lm49453_hp_mute, 1292 .no_capture_mute = 1, 1293}; 1294 1295static const struct snd_soc_dai_ops lm49453_speaker_dai_ops = { 1296 .hw_params = lm49453_hw_params, 1297 .set_sysclk = lm49453_set_dai_sysclk, 1298 .set_fmt = lm49453_set_dai_fmt, 1299 .mute_stream = lm49453_ls_mute, 1300 .no_capture_mute = 1, 1301}; 1302 1303static const struct snd_soc_dai_ops lm49453_haptic_dai_ops = { 1304 .hw_params = lm49453_hw_params, 1305 .set_sysclk = lm49453_set_dai_sysclk, 1306 .set_fmt = lm49453_set_dai_fmt, 1307 .mute_stream = lm49453_ha_mute, 1308 .no_capture_mute = 1, 1309}; 1310 1311static const struct snd_soc_dai_ops lm49453_ep_dai_ops = { 1312 .hw_params = lm49453_hw_params, 1313 .set_sysclk = lm49453_set_dai_sysclk, 1314 .set_fmt = lm49453_set_dai_fmt, 1315 .mute_stream = lm49453_ep_mute, 1316 .no_capture_mute = 1, 1317}; 1318 1319static const struct snd_soc_dai_ops lm49453_lineout_dai_ops = { 1320 .hw_params = lm49453_hw_params, 1321 .set_sysclk = lm49453_set_dai_sysclk, 1322 .set_fmt = lm49453_set_dai_fmt, 1323 .mute_stream = lm49453_lo_mute, 1324 .no_capture_mute = 1, 1325}; 1326 1327/* LM49453 dai structure. */ 1328static struct snd_soc_dai_driver lm49453_dai[] = { 1329 { 1330 .name = "LM49453 Headset", 1331 .playback = { 1332 .stream_name = "Headset", 1333 .channels_min = 2, 1334 .channels_max = 2, 1335 .rates = SNDRV_PCM_RATE_8000_192000, 1336 .formats = LM49453_FORMATS, 1337 }, 1338 .capture = { 1339 .stream_name = "Capture", 1340 .channels_min = 1, 1341 .channels_max = 5, 1342 .rates = SNDRV_PCM_RATE_8000_192000, 1343 .formats = LM49453_FORMATS, 1344 }, 1345 .ops = &lm49453_headset_dai_ops, 1346 .symmetric_rates = 1, 1347 }, 1348 { 1349 .name = "LM49453 Speaker", 1350 .playback = { 1351 .stream_name = "Speaker", 1352 .channels_min = 2, 1353 .channels_max = 2, 1354 .rates = SNDRV_PCM_RATE_8000_192000, 1355 .formats = LM49453_FORMATS, 1356 }, 1357 .ops = &lm49453_speaker_dai_ops, 1358 }, 1359 { 1360 .name = "LM49453 Haptic", 1361 .playback = { 1362 .stream_name = "Haptic", 1363 .channels_min = 2, 1364 .channels_max = 2, 1365 .rates = SNDRV_PCM_RATE_8000_192000, 1366 .formats = LM49453_FORMATS, 1367 }, 1368 .ops = &lm49453_haptic_dai_ops, 1369 }, 1370 { 1371 .name = "LM49453 Earpiece", 1372 .playback = { 1373 .stream_name = "Earpiece", 1374 .channels_min = 1, 1375 .channels_max = 1, 1376 .rates = SNDRV_PCM_RATE_8000_192000, 1377 .formats = LM49453_FORMATS, 1378 }, 1379 .ops = &lm49453_ep_dai_ops, 1380 }, 1381 { 1382 .name = "LM49453 line out", 1383 .playback = { 1384 .stream_name = "Lineout", 1385 .channels_min = 2, 1386 .channels_max = 2, 1387 .rates = SNDRV_PCM_RATE_8000_192000, 1388 .formats = LM49453_FORMATS, 1389 }, 1390 .ops = &lm49453_lineout_dai_ops, 1391 }, 1392}; 1393 1394static const struct snd_soc_component_driver soc_component_dev_lm49453 = { 1395 .set_bias_level = lm49453_set_bias_level, 1396 .controls = lm49453_snd_controls, 1397 .num_controls = ARRAY_SIZE(lm49453_snd_controls), 1398 .dapm_widgets = lm49453_dapm_widgets, 1399 .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets), 1400 .dapm_routes = lm49453_audio_map, 1401 .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map), 1402 .use_pmdown_time = 1, 1403 .endianness = 1, 1404 .non_legacy_dai_naming = 1, 1405}; 1406 1407static const struct regmap_config lm49453_regmap_config = { 1408 .reg_bits = 8, 1409 .val_bits = 8, 1410 1411 .max_register = LM49453_MAX_REGISTER, 1412 .reg_defaults = lm49453_reg_defs, 1413 .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs), 1414 .cache_type = REGCACHE_RBTREE, 1415}; 1416 1417static int lm49453_i2c_probe(struct i2c_client *i2c, 1418 const struct i2c_device_id *id) 1419{ 1420 struct lm49453_priv *lm49453; 1421 int ret = 0; 1422 1423 lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv), 1424 GFP_KERNEL); 1425 1426 if (lm49453 == NULL) 1427 return -ENOMEM; 1428 1429 i2c_set_clientdata(i2c, lm49453); 1430 1431 lm49453->regmap = devm_regmap_init_i2c(i2c, &lm49453_regmap_config); 1432 if (IS_ERR(lm49453->regmap)) { 1433 ret = PTR_ERR(lm49453->regmap); 1434 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1435 ret); 1436 return ret; 1437 } 1438 1439 ret = devm_snd_soc_register_component(&i2c->dev, 1440 &soc_component_dev_lm49453, 1441 lm49453_dai, ARRAY_SIZE(lm49453_dai)); 1442 if (ret < 0) 1443 dev_err(&i2c->dev, "Failed to register component: %d\n", ret); 1444 1445 return ret; 1446} 1447 1448static int lm49453_i2c_remove(struct i2c_client *client) 1449{ 1450 return 0; 1451} 1452 1453static const struct i2c_device_id lm49453_i2c_id[] = { 1454 { "lm49453", 0 }, 1455 { } 1456}; 1457MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id); 1458 1459static struct i2c_driver lm49453_i2c_driver = { 1460 .driver = { 1461 .name = "lm49453", 1462 }, 1463 .probe = lm49453_i2c_probe, 1464 .remove = lm49453_i2c_remove, 1465 .id_table = lm49453_i2c_id, 1466}; 1467 1468module_i2c_driver(lm49453_i2c_driver); 1469 1470MODULE_DESCRIPTION("ASoC LM49453 driver"); 1471MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com>"); 1472MODULE_LICENSE("GPL v2"); 1473