1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * es8328.c -- ES8328 ALSA SoC Audio driver 4 * 5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD 6 * 7 * Author: Sean Cross <xobs@kosagi.com> 8 */ 9 10#include <linux/clk.h> 11#include <linux/delay.h> 12#include <linux/of_device.h> 13#include <linux/module.h> 14#include <linux/pm.h> 15#include <linux/regmap.h> 16#include <linux/slab.h> 17#include <linux/regulator/consumer.h> 18#include <sound/core.h> 19#include <sound/initval.h> 20#include <sound/pcm.h> 21#include <sound/pcm_params.h> 22#include <sound/soc.h> 23#include <sound/tlv.h> 24#include "es8328.h" 25 26static const unsigned int rates_12288[] = { 27 8000, 12000, 16000, 24000, 32000, 48000, 96000, 28}; 29 30static const int ratios_12288[] = { 31 10, 7, 6, 4, 3, 2, 0, 32}; 33 34static const struct snd_pcm_hw_constraint_list constraints_12288 = { 35 .count = ARRAY_SIZE(rates_12288), 36 .list = rates_12288, 37}; 38 39static const unsigned int rates_11289[] = { 40 8018, 11025, 22050, 44100, 88200, 41}; 42 43static const int ratios_11289[] = { 44 9, 7, 4, 2, 0, 45}; 46 47static const struct snd_pcm_hw_constraint_list constraints_11289 = { 48 .count = ARRAY_SIZE(rates_11289), 49 .list = rates_11289, 50}; 51 52/* regulator supplies for sgtl5000, VDDD is an optional external supply */ 53enum sgtl5000_regulator_supplies { 54 DVDD, 55 AVDD, 56 PVDD, 57 HPVDD, 58 ES8328_SUPPLY_NUM 59}; 60 61/* vddd is optional supply */ 62static const char * const supply_names[ES8328_SUPPLY_NUM] = { 63 "DVDD", 64 "AVDD", 65 "PVDD", 66 "HPVDD", 67}; 68 69#define ES8328_RATES (SNDRV_PCM_RATE_192000 | \ 70 SNDRV_PCM_RATE_96000 | \ 71 SNDRV_PCM_RATE_88200 | \ 72 SNDRV_PCM_RATE_8000_48000) 73#define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 74 SNDRV_PCM_FMTBIT_S18_3LE | \ 75 SNDRV_PCM_FMTBIT_S20_3LE | \ 76 SNDRV_PCM_FMTBIT_S24_LE | \ 77 SNDRV_PCM_FMTBIT_S32_LE) 78 79struct es8328_priv { 80 struct regmap *regmap; 81 struct clk *clk; 82 int playback_fs; 83 bool deemph; 84 int mclkdiv2; 85 const struct snd_pcm_hw_constraint_list *sysclk_constraints; 86 const int *mclk_ratios; 87 bool master; 88 struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; 89}; 90 91/* 92 * ES8328 Controls 93 */ 94 95static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert", 96 "L + R Invert"}; 97static SOC_ENUM_SINGLE_DECL(adcpol, 98 ES8328_ADCCONTROL6, 6, adcpol_txt); 99 100static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0); 101static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0); 102static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 103static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0); 104 105static const struct { 106 int rate; 107 unsigned int val; 108} deemph_settings[] = { 109 { 0, ES8328_DACCONTROL6_DEEMPH_OFF }, 110 { 32000, ES8328_DACCONTROL6_DEEMPH_32k }, 111 { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k }, 112 { 48000, ES8328_DACCONTROL6_DEEMPH_48k }, 113}; 114 115static int es8328_set_deemph(struct snd_soc_component *component) 116{ 117 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 118 int val, i, best; 119 120 /* 121 * If we're using deemphasis select the nearest available sample 122 * rate. 123 */ 124 if (es8328->deemph) { 125 best = 0; 126 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) { 127 if (abs(deemph_settings[i].rate - es8328->playback_fs) < 128 abs(deemph_settings[best].rate - es8328->playback_fs)) 129 best = i; 130 } 131 132 val = deemph_settings[best].val; 133 } else { 134 val = ES8328_DACCONTROL6_DEEMPH_OFF; 135 } 136 137 dev_dbg(component->dev, "Set deemphasis %d\n", val); 138 139 return snd_soc_component_update_bits(component, ES8328_DACCONTROL6, 140 ES8328_DACCONTROL6_DEEMPH_MASK, val); 141} 142 143static int es8328_get_deemph(struct snd_kcontrol *kcontrol, 144 struct snd_ctl_elem_value *ucontrol) 145{ 146 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 147 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 148 149 ucontrol->value.integer.value[0] = es8328->deemph; 150 return 0; 151} 152 153static int es8328_put_deemph(struct snd_kcontrol *kcontrol, 154 struct snd_ctl_elem_value *ucontrol) 155{ 156 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 157 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 158 unsigned int deemph = ucontrol->value.integer.value[0]; 159 int ret; 160 161 if (deemph > 1) 162 return -EINVAL; 163 164 if (es8328->deemph == deemph) 165 return 0; 166 167 ret = es8328_set_deemph(component); 168 if (ret < 0) 169 return ret; 170 171 es8328->deemph = deemph; 172 173 return 1; 174} 175 176 177 178static const struct snd_kcontrol_new es8328_snd_controls[] = { 179 SOC_DOUBLE_R_TLV("Capture Digital Volume", 180 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9, 181 0, 0xc0, 1, dac_adc_tlv), 182 SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0), 183 184 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 185 es8328_get_deemph, es8328_put_deemph), 186 187 SOC_ENUM("Capture Polarity", adcpol), 188 189 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", 190 ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv), 191 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", 192 ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv), 193 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", 194 ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv), 195 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", 196 ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv), 197 198 SOC_DOUBLE_R_TLV("PCM Volume", 199 ES8328_LDACVOL, ES8328_RDACVOL, 200 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv), 201 202 SOC_DOUBLE_R_TLV("Output 1 Playback Volume", 203 ES8328_LOUT1VOL, ES8328_ROUT1VOL, 204 0, ES8328_OUT1VOL_MAX, 0, play_tlv), 205 206 SOC_DOUBLE_R_TLV("Output 2 Playback Volume", 207 ES8328_LOUT2VOL, ES8328_ROUT2VOL, 208 0, ES8328_OUT2VOL_MAX, 0, play_tlv), 209 210 SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1, 211 4, 0, 8, 0, mic_tlv), 212}; 213 214/* 215 * DAPM Controls 216 */ 217 218static const char * const es8328_line_texts[] = { 219 "Line 1", "Line 2", "PGA", "Differential"}; 220 221static const struct soc_enum es8328_lline_enum = 222 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3, 223 ARRAY_SIZE(es8328_line_texts), 224 es8328_line_texts); 225static const struct snd_kcontrol_new es8328_left_line_controls = 226 SOC_DAPM_ENUM("Route", es8328_lline_enum); 227 228static const struct soc_enum es8328_rline_enum = 229 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0, 230 ARRAY_SIZE(es8328_line_texts), 231 es8328_line_texts); 232static const struct snd_kcontrol_new es8328_right_line_controls = 233 SOC_DAPM_ENUM("Route", es8328_rline_enum); 234 235/* Left Mixer */ 236static const struct snd_kcontrol_new es8328_left_mixer_controls[] = { 237 SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0), 238 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0), 239 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0), 240 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0), 241}; 242 243/* Right Mixer */ 244static const struct snd_kcontrol_new es8328_right_mixer_controls[] = { 245 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0), 246 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0), 247 SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0), 248 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0), 249}; 250 251static const char * const es8328_pga_sel[] = { 252 "Line 1", "Line 2", "Line 3", "Differential"}; 253 254/* Left PGA Mux */ 255static const struct soc_enum es8328_lpga_enum = 256 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6, 257 ARRAY_SIZE(es8328_pga_sel), 258 es8328_pga_sel); 259static const struct snd_kcontrol_new es8328_left_pga_controls = 260 SOC_DAPM_ENUM("Route", es8328_lpga_enum); 261 262/* Right PGA Mux */ 263static const struct soc_enum es8328_rpga_enum = 264 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4, 265 ARRAY_SIZE(es8328_pga_sel), 266 es8328_pga_sel); 267static const struct snd_kcontrol_new es8328_right_pga_controls = 268 SOC_DAPM_ENUM("Route", es8328_rpga_enum); 269 270/* Differential Mux */ 271static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"}; 272static SOC_ENUM_SINGLE_DECL(diffmux, 273 ES8328_ADCCONTROL3, 7, es8328_diff_sel); 274static const struct snd_kcontrol_new es8328_diffmux_controls = 275 SOC_DAPM_ENUM("Route", diffmux); 276 277/* Mono ADC Mux */ 278static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)", 279 "Mono (Right)", "Digital Mono"}; 280static SOC_ENUM_SINGLE_DECL(monomux, 281 ES8328_ADCCONTROL3, 3, es8328_mono_mux); 282static const struct snd_kcontrol_new es8328_monomux_controls = 283 SOC_DAPM_ENUM("Route", monomux); 284 285static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = { 286 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, 287 &es8328_diffmux_controls), 288 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, 289 &es8328_monomux_controls), 290 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, 291 &es8328_monomux_controls), 292 293 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER, 294 ES8328_ADCPOWER_AINL_OFF, 1, 295 &es8328_left_pga_controls), 296 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER, 297 ES8328_ADCPOWER_AINR_OFF, 1, 298 &es8328_right_pga_controls), 299 300 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, 301 &es8328_left_line_controls), 302 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, 303 &es8328_right_line_controls), 304 305 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER, 306 ES8328_ADCPOWER_ADCR_OFF, 1), 307 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER, 308 ES8328_ADCPOWER_ADCL_OFF, 1), 309 310 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER, 311 ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0), 312 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER, 313 ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0), 314 315 SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER, 316 ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0), 317 SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER, 318 ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0), 319 320 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER, 321 ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0), 322 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER, 323 ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0), 324 325 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER, 326 ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0), 327 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER, 328 ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0), 329 330 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER, 331 ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0), 332 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER, 333 ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0), 334 335 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER, 336 ES8328_DACPOWER_RDAC_OFF, 1), 337 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER, 338 ES8328_DACPOWER_LDAC_OFF, 1), 339 340 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, 341 &es8328_left_mixer_controls[0], 342 ARRAY_SIZE(es8328_left_mixer_controls)), 343 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, 344 &es8328_right_mixer_controls[0], 345 ARRAY_SIZE(es8328_right_mixer_controls)), 346 347 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER, 348 ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0), 349 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER, 350 ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0), 351 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER, 352 ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0), 353 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER, 354 ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0), 355 356 SND_SOC_DAPM_OUTPUT("LOUT1"), 357 SND_SOC_DAPM_OUTPUT("ROUT1"), 358 SND_SOC_DAPM_OUTPUT("LOUT2"), 359 SND_SOC_DAPM_OUTPUT("ROUT2"), 360 361 SND_SOC_DAPM_INPUT("LINPUT1"), 362 SND_SOC_DAPM_INPUT("LINPUT2"), 363 SND_SOC_DAPM_INPUT("RINPUT1"), 364 SND_SOC_DAPM_INPUT("RINPUT2"), 365}; 366 367static const struct snd_soc_dapm_route es8328_dapm_routes[] = { 368 369 { "Left Line Mux", "Line 1", "LINPUT1" }, 370 { "Left Line Mux", "Line 2", "LINPUT2" }, 371 { "Left Line Mux", "PGA", "Left PGA Mux" }, 372 { "Left Line Mux", "Differential", "Differential Mux" }, 373 374 { "Right Line Mux", "Line 1", "RINPUT1" }, 375 { "Right Line Mux", "Line 2", "RINPUT2" }, 376 { "Right Line Mux", "PGA", "Right PGA Mux" }, 377 { "Right Line Mux", "Differential", "Differential Mux" }, 378 379 { "Left PGA Mux", "Line 1", "LINPUT1" }, 380 { "Left PGA Mux", "Line 2", "LINPUT2" }, 381 { "Left PGA Mux", "Differential", "Differential Mux" }, 382 383 { "Right PGA Mux", "Line 1", "RINPUT1" }, 384 { "Right PGA Mux", "Line 2", "RINPUT2" }, 385 { "Right PGA Mux", "Differential", "Differential Mux" }, 386 387 { "Differential Mux", "Line 1", "LINPUT1" }, 388 { "Differential Mux", "Line 1", "RINPUT1" }, 389 { "Differential Mux", "Line 2", "LINPUT2" }, 390 { "Differential Mux", "Line 2", "RINPUT2" }, 391 392 { "Left ADC Mux", "Stereo", "Left PGA Mux" }, 393 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" }, 394 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" }, 395 396 { "Right ADC Mux", "Stereo", "Right PGA Mux" }, 397 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" }, 398 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" }, 399 400 { "Left ADC", NULL, "Left ADC Mux" }, 401 { "Right ADC", NULL, "Right ADC Mux" }, 402 403 { "ADC DIG", NULL, "ADC STM" }, 404 { "ADC DIG", NULL, "ADC Vref" }, 405 { "ADC DIG", NULL, "ADC DLL" }, 406 407 { "Left ADC", NULL, "ADC DIG" }, 408 { "Right ADC", NULL, "ADC DIG" }, 409 410 { "Mic Bias", NULL, "Mic Bias Gen" }, 411 412 { "Left Line Mux", "Line 1", "LINPUT1" }, 413 { "Left Line Mux", "Line 2", "LINPUT2" }, 414 { "Left Line Mux", "PGA", "Left PGA Mux" }, 415 { "Left Line Mux", "Differential", "Differential Mux" }, 416 417 { "Right Line Mux", "Line 1", "RINPUT1" }, 418 { "Right Line Mux", "Line 2", "RINPUT2" }, 419 { "Right Line Mux", "PGA", "Right PGA Mux" }, 420 { "Right Line Mux", "Differential", "Differential Mux" }, 421 422 { "Left Out 1", NULL, "Left DAC" }, 423 { "Right Out 1", NULL, "Right DAC" }, 424 { "Left Out 2", NULL, "Left DAC" }, 425 { "Right Out 2", NULL, "Right DAC" }, 426 427 { "Left Mixer", "Playback Switch", "Left DAC" }, 428 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" }, 429 { "Left Mixer", "Right Playback Switch", "Right DAC" }, 430 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" }, 431 432 { "Right Mixer", "Left Playback Switch", "Left DAC" }, 433 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" }, 434 { "Right Mixer", "Playback Switch", "Right DAC" }, 435 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" }, 436 437 { "DAC DIG", NULL, "DAC STM" }, 438 { "DAC DIG", NULL, "DAC Vref" }, 439 { "DAC DIG", NULL, "DAC DLL" }, 440 441 { "Left DAC", NULL, "DAC DIG" }, 442 { "Right DAC", NULL, "DAC DIG" }, 443 444 { "Left Out 1", NULL, "Left Mixer" }, 445 { "LOUT1", NULL, "Left Out 1" }, 446 { "Right Out 1", NULL, "Right Mixer" }, 447 { "ROUT1", NULL, "Right Out 1" }, 448 449 { "Left Out 2", NULL, "Left Mixer" }, 450 { "LOUT2", NULL, "Left Out 2" }, 451 { "Right Out 2", NULL, "Right Mixer" }, 452 { "ROUT2", NULL, "Right Out 2" }, 453}; 454 455static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction) 456{ 457 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, 458 ES8328_DACCONTROL3_DACMUTE, 459 mute ? ES8328_DACCONTROL3_DACMUTE : 0); 460} 461 462static int es8328_startup(struct snd_pcm_substream *substream, 463 struct snd_soc_dai *dai) 464{ 465 struct snd_soc_component *component = dai->component; 466 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 467 468 if (es8328->master && es8328->sysclk_constraints) 469 snd_pcm_hw_constraint_list(substream->runtime, 0, 470 SNDRV_PCM_HW_PARAM_RATE, 471 es8328->sysclk_constraints); 472 473 return 0; 474} 475 476static int es8328_hw_params(struct snd_pcm_substream *substream, 477 struct snd_pcm_hw_params *params, 478 struct snd_soc_dai *dai) 479{ 480 struct snd_soc_component *component = dai->component; 481 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 482 int i; 483 int reg; 484 int wl; 485 int ratio; 486 487 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 488 reg = ES8328_DACCONTROL2; 489 else 490 reg = ES8328_ADCCONTROL5; 491 492 if (es8328->master) { 493 if (!es8328->sysclk_constraints) { 494 dev_err(component->dev, "No MCLK configured\n"); 495 return -EINVAL; 496 } 497 498 for (i = 0; i < es8328->sysclk_constraints->count; i++) 499 if (es8328->sysclk_constraints->list[i] == 500 params_rate(params)) 501 break; 502 503 if (i == es8328->sysclk_constraints->count) { 504 dev_err(component->dev, 505 "LRCLK %d unsupported with current clock\n", 506 params_rate(params)); 507 return -EINVAL; 508 } 509 ratio = es8328->mclk_ratios[i]; 510 } else { 511 ratio = 0; 512 es8328->mclkdiv2 = 0; 513 } 514 515 snd_soc_component_update_bits(component, ES8328_MASTERMODE, 516 ES8328_MASTERMODE_MCLKDIV2, 517 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); 518 519 switch (params_width(params)) { 520 case 16: 521 wl = 3; 522 break; 523 case 18: 524 wl = 2; 525 break; 526 case 20: 527 wl = 1; 528 break; 529 case 24: 530 wl = 0; 531 break; 532 case 32: 533 wl = 4; 534 break; 535 default: 536 return -EINVAL; 537 } 538 539 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 540 snd_soc_component_update_bits(component, ES8328_DACCONTROL1, 541 ES8328_DACCONTROL1_DACWL_MASK, 542 wl << ES8328_DACCONTROL1_DACWL_SHIFT); 543 544 es8328->playback_fs = params_rate(params); 545 es8328_set_deemph(component); 546 } else 547 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, 548 ES8328_ADCCONTROL4_ADCWL_MASK, 549 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT); 550 551 return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio); 552} 553 554static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, 555 int clk_id, unsigned int freq, int dir) 556{ 557 struct snd_soc_component *component = codec_dai->component; 558 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 559 int mclkdiv2 = 0; 560 561 switch (freq) { 562 case 0: 563 es8328->sysclk_constraints = NULL; 564 es8328->mclk_ratios = NULL; 565 break; 566 case 22579200: 567 mclkdiv2 = 1; 568 fallthrough; 569 case 11289600: 570 es8328->sysclk_constraints = &constraints_11289; 571 es8328->mclk_ratios = ratios_11289; 572 break; 573 case 24576000: 574 mclkdiv2 = 1; 575 fallthrough; 576 case 12288000: 577 es8328->sysclk_constraints = &constraints_12288; 578 es8328->mclk_ratios = ratios_12288; 579 break; 580 default: 581 return -EINVAL; 582 } 583 584 es8328->mclkdiv2 = mclkdiv2; 585 return 0; 586} 587 588static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, 589 unsigned int fmt) 590{ 591 struct snd_soc_component *component = codec_dai->component; 592 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 593 u8 dac_mode = 0; 594 u8 adc_mode = 0; 595 596 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 597 case SND_SOC_DAIFMT_CBM_CFM: 598 /* Master serial port mode, with BCLK generated automatically */ 599 snd_soc_component_update_bits(component, ES8328_MASTERMODE, 600 ES8328_MASTERMODE_MSC, 601 ES8328_MASTERMODE_MSC); 602 es8328->master = true; 603 break; 604 case SND_SOC_DAIFMT_CBS_CFS: 605 /* Slave serial port mode */ 606 snd_soc_component_update_bits(component, ES8328_MASTERMODE, 607 ES8328_MASTERMODE_MSC, 0); 608 es8328->master = false; 609 break; 610 default: 611 return -EINVAL; 612 } 613 614 /* interface format */ 615 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 616 case SND_SOC_DAIFMT_I2S: 617 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; 618 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S; 619 break; 620 case SND_SOC_DAIFMT_RIGHT_J: 621 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; 622 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST; 623 break; 624 case SND_SOC_DAIFMT_LEFT_J: 625 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; 626 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST; 627 break; 628 default: 629 return -EINVAL; 630 } 631 632 /* clock inversion */ 633 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) 634 return -EINVAL; 635 636 snd_soc_component_update_bits(component, ES8328_DACCONTROL1, 637 ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode); 638 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, 639 ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode); 640 641 return 0; 642} 643 644static int es8328_set_bias_level(struct snd_soc_component *component, 645 enum snd_soc_bias_level level) 646{ 647 switch (level) { 648 case SND_SOC_BIAS_ON: 649 break; 650 651 case SND_SOC_BIAS_PREPARE: 652 /* VREF, VMID=2x50k, digital enabled */ 653 snd_soc_component_write(component, ES8328_CHIPPOWER, 0); 654 snd_soc_component_update_bits(component, ES8328_CONTROL1, 655 ES8328_CONTROL1_VMIDSEL_MASK | 656 ES8328_CONTROL1_ENREF, 657 ES8328_CONTROL1_VMIDSEL_50k | 658 ES8328_CONTROL1_ENREF); 659 break; 660 661 case SND_SOC_BIAS_STANDBY: 662 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 663 snd_soc_component_update_bits(component, ES8328_CONTROL1, 664 ES8328_CONTROL1_VMIDSEL_MASK | 665 ES8328_CONTROL1_ENREF, 666 ES8328_CONTROL1_VMIDSEL_5k | 667 ES8328_CONTROL1_ENREF); 668 669 /* Charge caps */ 670 msleep(100); 671 } 672 673 snd_soc_component_write(component, ES8328_CONTROL2, 674 ES8328_CONTROL2_OVERCURRENT_ON | 675 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON); 676 677 /* VREF, VMID=2*500k, digital stopped */ 678 snd_soc_component_update_bits(component, ES8328_CONTROL1, 679 ES8328_CONTROL1_VMIDSEL_MASK | 680 ES8328_CONTROL1_ENREF, 681 ES8328_CONTROL1_VMIDSEL_500k | 682 ES8328_CONTROL1_ENREF); 683 break; 684 685 case SND_SOC_BIAS_OFF: 686 snd_soc_component_update_bits(component, ES8328_CONTROL1, 687 ES8328_CONTROL1_VMIDSEL_MASK | 688 ES8328_CONTROL1_ENREF, 689 0); 690 break; 691 } 692 return 0; 693} 694 695static const struct snd_soc_dai_ops es8328_dai_ops = { 696 .startup = es8328_startup, 697 .hw_params = es8328_hw_params, 698 .mute_stream = es8328_mute, 699 .set_sysclk = es8328_set_sysclk, 700 .set_fmt = es8328_set_dai_fmt, 701 .no_capture_mute = 1, 702}; 703 704static struct snd_soc_dai_driver es8328_dai = { 705 .name = "es8328-hifi-analog", 706 .playback = { 707 .stream_name = "Playback", 708 .channels_min = 2, 709 .channels_max = 2, 710 .rates = ES8328_RATES, 711 .formats = ES8328_FORMATS, 712 }, 713 .capture = { 714 .stream_name = "Capture", 715 .channels_min = 2, 716 .channels_max = 2, 717 .rates = ES8328_RATES, 718 .formats = ES8328_FORMATS, 719 }, 720 .ops = &es8328_dai_ops, 721 .symmetric_rates = 1, 722}; 723 724static int es8328_suspend(struct snd_soc_component *component) 725{ 726 struct es8328_priv *es8328; 727 int ret; 728 729 es8328 = snd_soc_component_get_drvdata(component); 730 731 clk_disable_unprepare(es8328->clk); 732 733 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 734 es8328->supplies); 735 if (ret) { 736 dev_err(component->dev, "unable to disable regulators\n"); 737 return ret; 738 } 739 return 0; 740} 741 742static int es8328_resume(struct snd_soc_component *component) 743{ 744 struct regmap *regmap = dev_get_regmap(component->dev, NULL); 745 struct es8328_priv *es8328; 746 int ret; 747 748 es8328 = snd_soc_component_get_drvdata(component); 749 750 ret = clk_prepare_enable(es8328->clk); 751 if (ret) { 752 dev_err(component->dev, "unable to enable clock\n"); 753 return ret; 754 } 755 756 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), 757 es8328->supplies); 758 if (ret) { 759 dev_err(component->dev, "unable to enable regulators\n"); 760 return ret; 761 } 762 763 regcache_mark_dirty(regmap); 764 ret = regcache_sync(regmap); 765 if (ret) { 766 dev_err(component->dev, "unable to sync regcache\n"); 767 return ret; 768 } 769 770 return 0; 771} 772 773static int es8328_component_probe(struct snd_soc_component *component) 774{ 775 struct es8328_priv *es8328; 776 int ret; 777 778 es8328 = snd_soc_component_get_drvdata(component); 779 780 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), 781 es8328->supplies); 782 if (ret) { 783 dev_err(component->dev, "unable to enable regulators\n"); 784 return ret; 785 } 786 787 /* Setup clocks */ 788 es8328->clk = devm_clk_get(component->dev, NULL); 789 if (IS_ERR(es8328->clk)) { 790 dev_err(component->dev, "codec clock missing or invalid\n"); 791 ret = PTR_ERR(es8328->clk); 792 goto clk_fail; 793 } 794 795 ret = clk_prepare_enable(es8328->clk); 796 if (ret) { 797 dev_err(component->dev, "unable to prepare codec clk\n"); 798 goto clk_fail; 799 } 800 801 return 0; 802 803clk_fail: 804 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 805 es8328->supplies); 806 return ret; 807} 808 809static void es8328_remove(struct snd_soc_component *component) 810{ 811 struct es8328_priv *es8328; 812 813 es8328 = snd_soc_component_get_drvdata(component); 814 815 if (es8328->clk) 816 clk_disable_unprepare(es8328->clk); 817 818 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 819 es8328->supplies); 820} 821 822const struct regmap_config es8328_regmap_config = { 823 .reg_bits = 8, 824 .val_bits = 8, 825 .max_register = ES8328_REG_MAX, 826 .cache_type = REGCACHE_RBTREE, 827 .use_single_read = true, 828 .use_single_write = true, 829}; 830EXPORT_SYMBOL_GPL(es8328_regmap_config); 831 832static const struct snd_soc_component_driver es8328_component_driver = { 833 .probe = es8328_component_probe, 834 .remove = es8328_remove, 835 .suspend = es8328_suspend, 836 .resume = es8328_resume, 837 .set_bias_level = es8328_set_bias_level, 838 .controls = es8328_snd_controls, 839 .num_controls = ARRAY_SIZE(es8328_snd_controls), 840 .dapm_widgets = es8328_dapm_widgets, 841 .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets), 842 .dapm_routes = es8328_dapm_routes, 843 .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes), 844 .suspend_bias_off = 1, 845 .idle_bias_on = 1, 846 .use_pmdown_time = 1, 847 .endianness = 1, 848 .non_legacy_dai_naming = 1, 849}; 850 851int es8328_probe(struct device *dev, struct regmap *regmap) 852{ 853 struct es8328_priv *es8328; 854 int ret; 855 int i; 856 857 if (IS_ERR(regmap)) 858 return PTR_ERR(regmap); 859 860 es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL); 861 if (es8328 == NULL) 862 return -ENOMEM; 863 864 es8328->regmap = regmap; 865 866 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) 867 es8328->supplies[i].supply = supply_names[i]; 868 869 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), 870 es8328->supplies); 871 if (ret) { 872 dev_err(dev, "unable to get regulators\n"); 873 return ret; 874 } 875 876 dev_set_drvdata(dev, es8328); 877 878 return devm_snd_soc_register_component(dev, 879 &es8328_component_driver, &es8328_dai, 1); 880} 881EXPORT_SYMBOL_GPL(es8328_probe); 882 883MODULE_DESCRIPTION("ASoC ES8328 driver"); 884MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); 885MODULE_LICENSE("GPL"); 886