1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * cs35l34.c -- CS35l34 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: Paul Handrigan <Paul.Handrigan@cirrus.com> 8 */ 9 10#include <linux/module.h> 11#include <linux/moduleparam.h> 12#include <linux/kernel.h> 13#include <linux/init.h> 14#include <linux/delay.h> 15#include <linux/i2c.h> 16#include <linux/slab.h> 17#include <linux/workqueue.h> 18#include <linux/platform_device.h> 19#include <linux/regulator/consumer.h> 20#include <linux/regulator/machine.h> 21#include <linux/pm_runtime.h> 22#include <linux/of_device.h> 23#include <linux/of_irq.h> 24#include <sound/core.h> 25#include <sound/pcm.h> 26#include <sound/pcm_params.h> 27#include <sound/soc.h> 28#include <sound/soc-dapm.h> 29#include <linux/gpio/consumer.h> 30#include <sound/initval.h> 31#include <sound/tlv.h> 32#include <sound/cs35l34.h> 33 34#include "cs35l34.h" 35 36#define PDN_DONE_ATTEMPTS 10 37#define CS35L34_START_DELAY 50 38 39struct cs35l34_private { 40 struct snd_soc_component *component; 41 struct cs35l34_platform_data pdata; 42 struct regmap *regmap; 43 struct regulator_bulk_data core_supplies[2]; 44 int num_core_supplies; 45 int mclk_int; 46 bool tdm_mode; 47 struct gpio_desc *reset_gpio; /* Active-low reset GPIO */ 48}; 49 50static const struct reg_default cs35l34_reg[] = { 51 {CS35L34_PWRCTL1, 0x01}, 52 {CS35L34_PWRCTL2, 0x19}, 53 {CS35L34_PWRCTL3, 0x01}, 54 {CS35L34_ADSP_CLK_CTL, 0x08}, 55 {CS35L34_MCLK_CTL, 0x11}, 56 {CS35L34_AMP_INP_DRV_CTL, 0x01}, 57 {CS35L34_AMP_DIG_VOL_CTL, 0x12}, 58 {CS35L34_AMP_DIG_VOL, 0x00}, 59 {CS35L34_AMP_ANLG_GAIN_CTL, 0x0F}, 60 {CS35L34_PROTECT_CTL, 0x06}, 61 {CS35L34_AMP_KEEP_ALIVE_CTL, 0x04}, 62 {CS35L34_BST_CVTR_V_CTL, 0x00}, 63 {CS35L34_BST_PEAK_I, 0x10}, 64 {CS35L34_BST_RAMP_CTL, 0x87}, 65 {CS35L34_BST_CONV_COEF_1, 0x24}, 66 {CS35L34_BST_CONV_COEF_2, 0x24}, 67 {CS35L34_BST_CONV_SLOPE_COMP, 0x4E}, 68 {CS35L34_BST_CONV_SW_FREQ, 0x08}, 69 {CS35L34_CLASS_H_CTL, 0x0D}, 70 {CS35L34_CLASS_H_HEADRM_CTL, 0x0D}, 71 {CS35L34_CLASS_H_RELEASE_RATE, 0x08}, 72 {CS35L34_CLASS_H_FET_DRIVE_CTL, 0x41}, 73 {CS35L34_CLASS_H_STATUS, 0x05}, 74 {CS35L34_VPBR_CTL, 0x0A}, 75 {CS35L34_VPBR_VOL_CTL, 0x90}, 76 {CS35L34_VPBR_TIMING_CTL, 0x6A}, 77 {CS35L34_PRED_MAX_ATTEN_SPK_LOAD, 0x95}, 78 {CS35L34_PRED_BROWNOUT_THRESH, 0x1C}, 79 {CS35L34_PRED_BROWNOUT_VOL_CTL, 0x00}, 80 {CS35L34_PRED_BROWNOUT_RATE_CTL, 0x10}, 81 {CS35L34_PRED_WAIT_CTL, 0x10}, 82 {CS35L34_PRED_ZVP_INIT_IMP_CTL, 0x08}, 83 {CS35L34_PRED_MAN_SAFE_VPI_CTL, 0x80}, 84 {CS35L34_VPBR_ATTEN_STATUS, 0x00}, 85 {CS35L34_PRED_BRWNOUT_ATT_STATUS, 0x00}, 86 {CS35L34_SPKR_MON_CTL, 0xC6}, 87 {CS35L34_ADSP_I2S_CTL, 0x00}, 88 {CS35L34_ADSP_TDM_CTL, 0x00}, 89 {CS35L34_TDM_TX_CTL_1_VMON, 0x00}, 90 {CS35L34_TDM_TX_CTL_2_IMON, 0x04}, 91 {CS35L34_TDM_TX_CTL_3_VPMON, 0x03}, 92 {CS35L34_TDM_TX_CTL_4_VBSTMON, 0x07}, 93 {CS35L34_TDM_TX_CTL_5_FLAG1, 0x08}, 94 {CS35L34_TDM_TX_CTL_6_FLAG2, 0x09}, 95 {CS35L34_TDM_TX_SLOT_EN_1, 0x00}, 96 {CS35L34_TDM_TX_SLOT_EN_2, 0x00}, 97 {CS35L34_TDM_TX_SLOT_EN_3, 0x00}, 98 {CS35L34_TDM_TX_SLOT_EN_4, 0x00}, 99 {CS35L34_TDM_RX_CTL_1_AUDIN, 0x40}, 100 {CS35L34_TDM_RX_CTL_3_ALIVE, 0x04}, 101 {CS35L34_MULT_DEV_SYNCH1, 0x00}, 102 {CS35L34_MULT_DEV_SYNCH2, 0x80}, 103 {CS35L34_PROT_RELEASE_CTL, 0x00}, 104 {CS35L34_DIAG_MODE_REG_LOCK, 0x00}, 105 {CS35L34_DIAG_MODE_CTL_1, 0x00}, 106 {CS35L34_DIAG_MODE_CTL_2, 0x00}, 107 {CS35L34_INT_MASK_1, 0xFF}, 108 {CS35L34_INT_MASK_2, 0xFF}, 109 {CS35L34_INT_MASK_3, 0xFF}, 110 {CS35L34_INT_MASK_4, 0xFF}, 111 {CS35L34_INT_STATUS_1, 0x30}, 112 {CS35L34_INT_STATUS_2, 0x05}, 113 {CS35L34_INT_STATUS_3, 0x00}, 114 {CS35L34_INT_STATUS_4, 0x00}, 115 {CS35L34_OTP_TRIM_STATUS, 0x00}, 116}; 117 118static bool cs35l34_volatile_register(struct device *dev, unsigned int reg) 119{ 120 switch (reg) { 121 case CS35L34_DEVID_AB: 122 case CS35L34_DEVID_CD: 123 case CS35L34_DEVID_E: 124 case CS35L34_FAB_ID: 125 case CS35L34_REV_ID: 126 case CS35L34_INT_STATUS_1: 127 case CS35L34_INT_STATUS_2: 128 case CS35L34_INT_STATUS_3: 129 case CS35L34_INT_STATUS_4: 130 case CS35L34_CLASS_H_STATUS: 131 case CS35L34_VPBR_ATTEN_STATUS: 132 case CS35L34_OTP_TRIM_STATUS: 133 return true; 134 default: 135 return false; 136 } 137} 138 139static bool cs35l34_readable_register(struct device *dev, unsigned int reg) 140{ 141 switch (reg) { 142 case CS35L34_DEVID_AB: 143 case CS35L34_DEVID_CD: 144 case CS35L34_DEVID_E: 145 case CS35L34_FAB_ID: 146 case CS35L34_REV_ID: 147 case CS35L34_PWRCTL1: 148 case CS35L34_PWRCTL2: 149 case CS35L34_PWRCTL3: 150 case CS35L34_ADSP_CLK_CTL: 151 case CS35L34_MCLK_CTL: 152 case CS35L34_AMP_INP_DRV_CTL: 153 case CS35L34_AMP_DIG_VOL_CTL: 154 case CS35L34_AMP_DIG_VOL: 155 case CS35L34_AMP_ANLG_GAIN_CTL: 156 case CS35L34_PROTECT_CTL: 157 case CS35L34_AMP_KEEP_ALIVE_CTL: 158 case CS35L34_BST_CVTR_V_CTL: 159 case CS35L34_BST_PEAK_I: 160 case CS35L34_BST_RAMP_CTL: 161 case CS35L34_BST_CONV_COEF_1: 162 case CS35L34_BST_CONV_COEF_2: 163 case CS35L34_BST_CONV_SLOPE_COMP: 164 case CS35L34_BST_CONV_SW_FREQ: 165 case CS35L34_CLASS_H_CTL: 166 case CS35L34_CLASS_H_HEADRM_CTL: 167 case CS35L34_CLASS_H_RELEASE_RATE: 168 case CS35L34_CLASS_H_FET_DRIVE_CTL: 169 case CS35L34_CLASS_H_STATUS: 170 case CS35L34_VPBR_CTL: 171 case CS35L34_VPBR_VOL_CTL: 172 case CS35L34_VPBR_TIMING_CTL: 173 case CS35L34_PRED_MAX_ATTEN_SPK_LOAD: 174 case CS35L34_PRED_BROWNOUT_THRESH: 175 case CS35L34_PRED_BROWNOUT_VOL_CTL: 176 case CS35L34_PRED_BROWNOUT_RATE_CTL: 177 case CS35L34_PRED_WAIT_CTL: 178 case CS35L34_PRED_ZVP_INIT_IMP_CTL: 179 case CS35L34_PRED_MAN_SAFE_VPI_CTL: 180 case CS35L34_VPBR_ATTEN_STATUS: 181 case CS35L34_PRED_BRWNOUT_ATT_STATUS: 182 case CS35L34_SPKR_MON_CTL: 183 case CS35L34_ADSP_I2S_CTL: 184 case CS35L34_ADSP_TDM_CTL: 185 case CS35L34_TDM_TX_CTL_1_VMON: 186 case CS35L34_TDM_TX_CTL_2_IMON: 187 case CS35L34_TDM_TX_CTL_3_VPMON: 188 case CS35L34_TDM_TX_CTL_4_VBSTMON: 189 case CS35L34_TDM_TX_CTL_5_FLAG1: 190 case CS35L34_TDM_TX_CTL_6_FLAG2: 191 case CS35L34_TDM_TX_SLOT_EN_1: 192 case CS35L34_TDM_TX_SLOT_EN_2: 193 case CS35L34_TDM_TX_SLOT_EN_3: 194 case CS35L34_TDM_TX_SLOT_EN_4: 195 case CS35L34_TDM_RX_CTL_1_AUDIN: 196 case CS35L34_TDM_RX_CTL_3_ALIVE: 197 case CS35L34_MULT_DEV_SYNCH1: 198 case CS35L34_MULT_DEV_SYNCH2: 199 case CS35L34_PROT_RELEASE_CTL: 200 case CS35L34_DIAG_MODE_REG_LOCK: 201 case CS35L34_DIAG_MODE_CTL_1: 202 case CS35L34_DIAG_MODE_CTL_2: 203 case CS35L34_INT_MASK_1: 204 case CS35L34_INT_MASK_2: 205 case CS35L34_INT_MASK_3: 206 case CS35L34_INT_MASK_4: 207 case CS35L34_INT_STATUS_1: 208 case CS35L34_INT_STATUS_2: 209 case CS35L34_INT_STATUS_3: 210 case CS35L34_INT_STATUS_4: 211 case CS35L34_OTP_TRIM_STATUS: 212 return true; 213 default: 214 return false; 215 } 216} 217 218static bool cs35l34_precious_register(struct device *dev, unsigned int reg) 219{ 220 switch (reg) { 221 case CS35L34_INT_STATUS_1: 222 case CS35L34_INT_STATUS_2: 223 case CS35L34_INT_STATUS_3: 224 case CS35L34_INT_STATUS_4: 225 return true; 226 default: 227 return false; 228 } 229} 230 231static int cs35l34_sdin_event(struct snd_soc_dapm_widget *w, 232 struct snd_kcontrol *kcontrol, int event) 233{ 234 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 235 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component); 236 int ret; 237 238 switch (event) { 239 case SND_SOC_DAPM_PRE_PMU: 240 if (priv->tdm_mode) 241 regmap_update_bits(priv->regmap, CS35L34_PWRCTL3, 242 CS35L34_PDN_TDM, 0x00); 243 244 ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1, 245 CS35L34_PDN_ALL, 0); 246 if (ret < 0) { 247 dev_err(component->dev, "Cannot set Power bits %d\n", ret); 248 return ret; 249 } 250 usleep_range(5000, 5100); 251 break; 252 case SND_SOC_DAPM_POST_PMD: 253 if (priv->tdm_mode) { 254 regmap_update_bits(priv->regmap, CS35L34_PWRCTL3, 255 CS35L34_PDN_TDM, CS35L34_PDN_TDM); 256 } 257 ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1, 258 CS35L34_PDN_ALL, CS35L34_PDN_ALL); 259 break; 260 default: 261 pr_err("Invalid event = 0x%x\n", event); 262 } 263 return 0; 264} 265 266static int cs35l34_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 267 unsigned int rx_mask, int slots, int slot_width) 268{ 269 struct snd_soc_component *component = dai->component; 270 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component); 271 unsigned int reg, bit_pos; 272 int slot, slot_num; 273 274 if (slot_width != 8) 275 return -EINVAL; 276 277 priv->tdm_mode = true; 278 /* scan rx_mask for aud slot */ 279 slot = ffs(rx_mask) - 1; 280 if (slot >= 0) 281 snd_soc_component_update_bits(component, CS35L34_TDM_RX_CTL_1_AUDIN, 282 CS35L34_X_LOC, slot); 283 284 /* scan tx_mask: vmon(2 slots); imon (2 slots); vpmon (1 slot) 285 * vbstmon (1 slot) 286 */ 287 slot = ffs(tx_mask) - 1; 288 slot_num = 0; 289 290 /* disable vpmon/vbstmon: enable later if set in tx_mask */ 291 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON, 292 CS35L34_X_STATE | CS35L34_X_LOC, 293 CS35L34_X_STATE | CS35L34_X_LOC); 294 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_4_VBSTMON, 295 CS35L34_X_STATE | CS35L34_X_LOC, 296 CS35L34_X_STATE | CS35L34_X_LOC); 297 298 /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/ 299 while (slot >= 0) { 300 /* configure VMON_TX_LOC */ 301 if (slot_num == 0) 302 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_1_VMON, 303 CS35L34_X_STATE | CS35L34_X_LOC, slot); 304 305 /* configure IMON_TX_LOC */ 306 if (slot_num == 4) { 307 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_2_IMON, 308 CS35L34_X_STATE | CS35L34_X_LOC, slot); 309 } 310 /* configure VPMON_TX_LOC */ 311 if (slot_num == 3) { 312 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON, 313 CS35L34_X_STATE | CS35L34_X_LOC, slot); 314 } 315 /* configure VBSTMON_TX_LOC */ 316 if (slot_num == 7) { 317 snd_soc_component_update_bits(component, 318 CS35L34_TDM_TX_CTL_4_VBSTMON, 319 CS35L34_X_STATE | CS35L34_X_LOC, slot); 320 } 321 322 /* Enable the relevant tx slot */ 323 reg = CS35L34_TDM_TX_SLOT_EN_4 - (slot/8); 324 bit_pos = slot - ((slot / 8) * (8)); 325 snd_soc_component_update_bits(component, reg, 326 1 << bit_pos, 1 << bit_pos); 327 328 tx_mask &= ~(1 << slot); 329 slot = ffs(tx_mask) - 1; 330 slot_num++; 331 } 332 333 return 0; 334} 335 336static int cs35l34_main_amp_event(struct snd_soc_dapm_widget *w, 337 struct snd_kcontrol *kcontrol, int event) 338{ 339 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 340 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component); 341 342 switch (event) { 343 case SND_SOC_DAPM_POST_PMU: 344 regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL, 345 CS35L34_BST_CVTL_MASK, priv->pdata.boost_vtge); 346 usleep_range(5000, 5100); 347 regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL, 348 CS35L34_MUTE, 0); 349 break; 350 case SND_SOC_DAPM_POST_PMD: 351 regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL, 352 CS35L34_BST_CVTL_MASK, 0); 353 regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL, 354 CS35L34_MUTE, CS35L34_MUTE); 355 usleep_range(5000, 5100); 356 break; 357 default: 358 pr_err("Invalid event = 0x%x\n", event); 359 } 360 return 0; 361} 362 363static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0); 364 365static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 300, 100, 0); 366 367 368static const struct snd_kcontrol_new cs35l34_snd_controls[] = { 369 SOC_SINGLE_SX_TLV("Digital Volume", CS35L34_AMP_DIG_VOL, 370 0, 0x34, 0xE4, dig_vol_tlv), 371 SOC_SINGLE_TLV("Amp Gain Volume", CS35L34_AMP_ANLG_GAIN_CTL, 372 0, 0xF, 0, amp_gain_tlv), 373}; 374 375 376static int cs35l34_mclk_event(struct snd_soc_dapm_widget *w, 377 struct snd_kcontrol *kcontrol, int event) 378{ 379 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 380 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component); 381 int ret, i; 382 unsigned int reg; 383 384 switch (event) { 385 case SND_SOC_DAPM_PRE_PMD: 386 ret = regmap_read(priv->regmap, CS35L34_AMP_DIG_VOL_CTL, 387 ®); 388 if (ret != 0) { 389 pr_err("%s regmap read failure %d\n", __func__, ret); 390 return ret; 391 } 392 if (reg & CS35L34_AMP_DIGSFT) 393 msleep(40); 394 else 395 usleep_range(2000, 2100); 396 397 for (i = 0; i < PDN_DONE_ATTEMPTS; i++) { 398 ret = regmap_read(priv->regmap, CS35L34_INT_STATUS_2, 399 ®); 400 if (ret != 0) { 401 pr_err("%s regmap read failure %d\n", 402 __func__, ret); 403 return ret; 404 } 405 if (reg & CS35L34_PDN_DONE) 406 break; 407 408 usleep_range(5000, 5100); 409 } 410 if (i == PDN_DONE_ATTEMPTS) 411 pr_err("%s Device did not power down properly\n", 412 __func__); 413 break; 414 default: 415 pr_err("Invalid event = 0x%x\n", event); 416 break; 417 } 418 return 0; 419} 420 421static const struct snd_soc_dapm_widget cs35l34_dapm_widgets[] = { 422 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L34_PWRCTL3, 423 1, 1, cs35l34_sdin_event, 424 SND_SOC_DAPM_PRE_PMU | 425 SND_SOC_DAPM_POST_PMD), 426 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L34_PWRCTL3, 2, 1), 427 428 SND_SOC_DAPM_SUPPLY("EXTCLK", CS35L34_PWRCTL3, 7, 1, 429 cs35l34_mclk_event, SND_SOC_DAPM_PRE_PMD), 430 431 SND_SOC_DAPM_OUTPUT("SPK"), 432 433 SND_SOC_DAPM_INPUT("VP"), 434 SND_SOC_DAPM_INPUT("VPST"), 435 SND_SOC_DAPM_INPUT("ISENSE"), 436 SND_SOC_DAPM_INPUT("VSENSE"), 437 438 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L34_PWRCTL2, 7, 1), 439 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L34_PWRCTL2, 6, 1), 440 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L34_PWRCTL3, 3, 1), 441 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L34_PWRCTL3, 4, 1), 442 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L34_PWRCTL2, 5, 1), 443 SND_SOC_DAPM_ADC("BOOST", NULL, CS35L34_PWRCTL2, 2, 1), 444 445 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L34_PWRCTL2, 0, 1, NULL, 0, 446 cs35l34_main_amp_event, SND_SOC_DAPM_POST_PMU | 447 SND_SOC_DAPM_POST_PMD), 448}; 449 450static const struct snd_soc_dapm_route cs35l34_audio_map[] = { 451 {"SDIN", NULL, "AMP Playback"}, 452 {"BOOST", NULL, "SDIN"}, 453 {"CLASS H", NULL, "BOOST"}, 454 {"Main AMP", NULL, "CLASS H"}, 455 {"SPK", NULL, "Main AMP"}, 456 457 {"VPMON ADC", NULL, "CLASS H"}, 458 {"VBSTMON ADC", NULL, "CLASS H"}, 459 {"SPK", NULL, "VPMON ADC"}, 460 {"SPK", NULL, "VBSTMON ADC"}, 461 462 {"IMON ADC", NULL, "ISENSE"}, 463 {"VMON ADC", NULL, "VSENSE"}, 464 {"SDOUT", NULL, "IMON ADC"}, 465 {"SDOUT", NULL, "VMON ADC"}, 466 {"AMP Capture", NULL, "SDOUT"}, 467 468 {"SDIN", NULL, "EXTCLK"}, 469 {"SDOUT", NULL, "EXTCLK"}, 470}; 471 472struct cs35l34_mclk_div { 473 int mclk; 474 int srate; 475 u8 adsp_rate; 476}; 477 478static struct cs35l34_mclk_div cs35l34_mclk_coeffs[] = { 479 480 /* MCLK, Sample Rate, adsp_rate */ 481 482 {5644800, 11025, 0x1}, 483 {5644800, 22050, 0x4}, 484 {5644800, 44100, 0x7}, 485 486 {6000000, 8000, 0x0}, 487 {6000000, 11025, 0x1}, 488 {6000000, 12000, 0x2}, 489 {6000000, 16000, 0x3}, 490 {6000000, 22050, 0x4}, 491 {6000000, 24000, 0x5}, 492 {6000000, 32000, 0x6}, 493 {6000000, 44100, 0x7}, 494 {6000000, 48000, 0x8}, 495 496 {6144000, 8000, 0x0}, 497 {6144000, 11025, 0x1}, 498 {6144000, 12000, 0x2}, 499 {6144000, 16000, 0x3}, 500 {6144000, 22050, 0x4}, 501 {6144000, 24000, 0x5}, 502 {6144000, 32000, 0x6}, 503 {6144000, 44100, 0x7}, 504 {6144000, 48000, 0x8}, 505}; 506 507static int cs35l34_get_mclk_coeff(int mclk, int srate) 508{ 509 int i; 510 511 for (i = 0; i < ARRAY_SIZE(cs35l34_mclk_coeffs); i++) { 512 if (cs35l34_mclk_coeffs[i].mclk == mclk && 513 cs35l34_mclk_coeffs[i].srate == srate) 514 return i; 515 } 516 return -EINVAL; 517} 518 519static int cs35l34_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 520{ 521 struct snd_soc_component *component = codec_dai->component; 522 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component); 523 524 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 525 case SND_SOC_DAIFMT_CBM_CFM: 526 regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL, 527 0x80, 0x80); 528 break; 529 case SND_SOC_DAIFMT_CBS_CFS: 530 regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL, 531 0x80, 0x00); 532 break; 533 default: 534 return -EINVAL; 535 } 536 return 0; 537} 538 539static int cs35l34_pcm_hw_params(struct snd_pcm_substream *substream, 540 struct snd_pcm_hw_params *params, 541 struct snd_soc_dai *dai) 542{ 543 struct snd_soc_component *component = dai->component; 544 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component); 545 int srate = params_rate(params); 546 int ret; 547 548 int coeff = cs35l34_get_mclk_coeff(priv->mclk_int, srate); 549 550 if (coeff < 0) { 551 dev_err(component->dev, "ERROR: Invalid mclk %d and/or srate %d\n", 552 priv->mclk_int, srate); 553 return coeff; 554 } 555 556 ret = regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL, 557 CS35L34_ADSP_RATE, cs35l34_mclk_coeffs[coeff].adsp_rate); 558 if (ret != 0) 559 dev_err(component->dev, "Failed to set clock state %d\n", ret); 560 561 return ret; 562} 563 564static const unsigned int cs35l34_src_rates[] = { 565 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000 566}; 567 568 569static const struct snd_pcm_hw_constraint_list cs35l34_constraints = { 570 .count = ARRAY_SIZE(cs35l34_src_rates), 571 .list = cs35l34_src_rates, 572}; 573 574static int cs35l34_pcm_startup(struct snd_pcm_substream *substream, 575 struct snd_soc_dai *dai) 576{ 577 578 snd_pcm_hw_constraint_list(substream->runtime, 0, 579 SNDRV_PCM_HW_PARAM_RATE, &cs35l34_constraints); 580 return 0; 581} 582 583 584static int cs35l34_set_tristate(struct snd_soc_dai *dai, int tristate) 585{ 586 587 struct snd_soc_component *component = dai->component; 588 589 if (tristate) 590 snd_soc_component_update_bits(component, CS35L34_PWRCTL3, 591 CS35L34_PDN_SDOUT, CS35L34_PDN_SDOUT); 592 else 593 snd_soc_component_update_bits(component, CS35L34_PWRCTL3, 594 CS35L34_PDN_SDOUT, 0); 595 return 0; 596} 597 598static int cs35l34_dai_set_sysclk(struct snd_soc_dai *dai, 599 int clk_id, unsigned int freq, int dir) 600{ 601 struct snd_soc_component *component = dai->component; 602 struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component); 603 unsigned int value; 604 605 switch (freq) { 606 case CS35L34_MCLK_5644: 607 value = CS35L34_MCLK_RATE_5P6448; 608 cs35l34->mclk_int = freq; 609 break; 610 case CS35L34_MCLK_6: 611 value = CS35L34_MCLK_RATE_6P0000; 612 cs35l34->mclk_int = freq; 613 break; 614 case CS35L34_MCLK_6144: 615 value = CS35L34_MCLK_RATE_6P1440; 616 cs35l34->mclk_int = freq; 617 break; 618 case CS35L34_MCLK_11289: 619 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_5P6448; 620 cs35l34->mclk_int = freq / 2; 621 break; 622 case CS35L34_MCLK_12: 623 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P0000; 624 cs35l34->mclk_int = freq / 2; 625 break; 626 case CS35L34_MCLK_12288: 627 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P1440; 628 cs35l34->mclk_int = freq / 2; 629 break; 630 default: 631 dev_err(component->dev, "ERROR: Invalid Frequency %d\n", freq); 632 cs35l34->mclk_int = 0; 633 return -EINVAL; 634 } 635 regmap_update_bits(cs35l34->regmap, CS35L34_MCLK_CTL, 636 CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_MASK, value); 637 return 0; 638} 639 640static const struct snd_soc_dai_ops cs35l34_ops = { 641 .startup = cs35l34_pcm_startup, 642 .set_tristate = cs35l34_set_tristate, 643 .set_fmt = cs35l34_set_dai_fmt, 644 .hw_params = cs35l34_pcm_hw_params, 645 .set_sysclk = cs35l34_dai_set_sysclk, 646 .set_tdm_slot = cs35l34_set_tdm_slot, 647}; 648 649static struct snd_soc_dai_driver cs35l34_dai = { 650 .name = "cs35l34", 651 .id = 0, 652 .playback = { 653 .stream_name = "AMP Playback", 654 .channels_min = 1, 655 .channels_max = 8, 656 .rates = CS35L34_RATES, 657 .formats = CS35L34_FORMATS, 658 }, 659 .capture = { 660 .stream_name = "AMP Capture", 661 .channels_min = 1, 662 .channels_max = 8, 663 .rates = CS35L34_RATES, 664 .formats = CS35L34_FORMATS, 665 }, 666 .ops = &cs35l34_ops, 667 .symmetric_rates = 1, 668}; 669 670static int cs35l34_boost_inductor(struct cs35l34_private *cs35l34, 671 unsigned int inductor) 672{ 673 struct snd_soc_component *component = cs35l34->component; 674 675 switch (inductor) { 676 case 1000: /* 1 uH */ 677 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x24); 678 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x24); 679 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP, 680 0x4E); 681 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 0); 682 break; 683 case 1200: /* 1.2 uH */ 684 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20); 685 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20); 686 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP, 687 0x47); 688 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 1); 689 break; 690 case 1500: /* 1.5uH */ 691 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20); 692 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20); 693 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP, 694 0x3C); 695 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 2); 696 break; 697 case 2200: /* 2.2uH */ 698 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x19); 699 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x25); 700 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP, 701 0x23); 702 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 3); 703 break; 704 default: 705 dev_err(component->dev, "%s Invalid Inductor Value %d uH\n", 706 __func__, inductor); 707 return -EINVAL; 708 } 709 return 0; 710} 711 712static int cs35l34_probe(struct snd_soc_component *component) 713{ 714 int ret = 0; 715 struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component); 716 717 pm_runtime_get_sync(component->dev); 718 719 /* Set over temperature warning attenuation to 6 dB */ 720 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL, 721 CS35L34_OTW_ATTN_MASK, 0x8); 722 723 /* Set Power control registers 2 and 3 to have everything 724 * powered down at initialization 725 */ 726 regmap_write(cs35l34->regmap, CS35L34_PWRCTL2, 0xFD); 727 regmap_write(cs35l34->regmap, CS35L34_PWRCTL3, 0x1F); 728 729 /* Set mute bit at startup */ 730 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL, 731 CS35L34_MUTE, CS35L34_MUTE); 732 733 /* Set Platform Data */ 734 if (cs35l34->pdata.boost_peak) 735 regmap_update_bits(cs35l34->regmap, CS35L34_BST_PEAK_I, 736 CS35L34_BST_PEAK_MASK, 737 cs35l34->pdata.boost_peak); 738 739 if (cs35l34->pdata.gain_zc_disable) 740 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL, 741 CS35L34_GAIN_ZC_MASK, 0); 742 else 743 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL, 744 CS35L34_GAIN_ZC_MASK, CS35L34_GAIN_ZC_MASK); 745 746 if (cs35l34->pdata.aif_half_drv) 747 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_CLK_CTL, 748 CS35L34_ADSP_DRIVE, 0); 749 750 if (cs35l34->pdata.digsft_disable) 751 regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL, 752 CS35L34_AMP_DIGSFT, 0); 753 754 if (cs35l34->pdata.amp_inv) 755 regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL, 756 CS35L34_INV, CS35L34_INV); 757 758 if (cs35l34->pdata.boost_ind) 759 ret = cs35l34_boost_inductor(cs35l34, cs35l34->pdata.boost_ind); 760 761 if (cs35l34->pdata.i2s_sdinloc) 762 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_I2S_CTL, 763 CS35L34_I2S_LOC_MASK, 764 cs35l34->pdata.i2s_sdinloc << CS35L34_I2S_LOC_SHIFT); 765 766 if (cs35l34->pdata.tdm_rising_edge) 767 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_TDM_CTL, 768 1, 1); 769 770 pm_runtime_put_sync(component->dev); 771 772 return ret; 773} 774 775 776static const struct snd_soc_component_driver soc_component_dev_cs35l34 = { 777 .probe = cs35l34_probe, 778 .dapm_widgets = cs35l34_dapm_widgets, 779 .num_dapm_widgets = ARRAY_SIZE(cs35l34_dapm_widgets), 780 .dapm_routes = cs35l34_audio_map, 781 .num_dapm_routes = ARRAY_SIZE(cs35l34_audio_map), 782 .controls = cs35l34_snd_controls, 783 .num_controls = ARRAY_SIZE(cs35l34_snd_controls), 784 .idle_bias_on = 1, 785 .use_pmdown_time = 1, 786 .endianness = 1, 787 .non_legacy_dai_naming = 1, 788}; 789 790static struct regmap_config cs35l34_regmap = { 791 .reg_bits = 8, 792 .val_bits = 8, 793 794 .max_register = CS35L34_MAX_REGISTER, 795 .reg_defaults = cs35l34_reg, 796 .num_reg_defaults = ARRAY_SIZE(cs35l34_reg), 797 .volatile_reg = cs35l34_volatile_register, 798 .readable_reg = cs35l34_readable_register, 799 .precious_reg = cs35l34_precious_register, 800 .cache_type = REGCACHE_RBTREE, 801}; 802 803static int cs35l34_handle_of_data(struct i2c_client *i2c_client, 804 struct cs35l34_platform_data *pdata) 805{ 806 struct device_node *np = i2c_client->dev.of_node; 807 unsigned int val; 808 809 if (of_property_read_u32(np, "cirrus,boost-vtge-millivolt", 810 &val) >= 0) { 811 /* Boost Voltage has a maximum of 8V */ 812 if (val > 8000 || (val < 3300 && val > 0)) { 813 dev_err(&i2c_client->dev, 814 "Invalid Boost Voltage %d mV\n", val); 815 return -EINVAL; 816 } 817 if (val == 0) 818 pdata->boost_vtge = 0; /* Use VP */ 819 else 820 pdata->boost_vtge = ((val - 3300)/100) + 1; 821 } else { 822 dev_warn(&i2c_client->dev, 823 "Boost Voltage not specified. Using VP\n"); 824 } 825 826 if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) { 827 pdata->boost_ind = val; 828 } else { 829 dev_err(&i2c_client->dev, "Inductor not specified.\n"); 830 return -EINVAL; 831 } 832 833 if (of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val) >= 0) { 834 if (val > 3840 || val < 1200) { 835 dev_err(&i2c_client->dev, 836 "Invalid Boost Peak Current %d mA\n", val); 837 return -EINVAL; 838 } 839 pdata->boost_peak = ((val - 1200)/80) + 1; 840 } 841 842 pdata->aif_half_drv = of_property_read_bool(np, 843 "cirrus,aif-half-drv"); 844 pdata->digsft_disable = of_property_read_bool(np, 845 "cirrus,digsft-disable"); 846 847 pdata->gain_zc_disable = of_property_read_bool(np, 848 "cirrus,gain-zc-disable"); 849 pdata->amp_inv = of_property_read_bool(np, "cirrus,amp-inv"); 850 851 if (of_property_read_u32(np, "cirrus,i2s-sdinloc", &val) >= 0) 852 pdata->i2s_sdinloc = val; 853 if (of_property_read_u32(np, "cirrus,tdm-rising-edge", &val) >= 0) 854 pdata->tdm_rising_edge = val; 855 856 return 0; 857} 858 859static irqreturn_t cs35l34_irq_thread(int irq, void *data) 860{ 861 struct cs35l34_private *cs35l34 = data; 862 struct snd_soc_component *component = cs35l34->component; 863 unsigned int sticky1, sticky2, sticky3, sticky4; 864 unsigned int mask1, mask2, mask3, mask4, current1; 865 866 867 /* ack the irq by reading all status registers */ 868 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_4, &sticky4); 869 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_3, &sticky3); 870 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_2, &sticky2); 871 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, &sticky1); 872 873 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_4, &mask4); 874 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_3, &mask3); 875 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_2, &mask2); 876 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_1, &mask1); 877 878 if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3) 879 && !(sticky4 & ~mask4)) 880 return IRQ_NONE; 881 882 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, ¤t1); 883 884 if (sticky1 & CS35L34_CAL_ERR) { 885 dev_err(component->dev, "Cal error\n"); 886 887 /* error is no longer asserted; safe to reset */ 888 if (!(current1 & CS35L34_CAL_ERR)) { 889 dev_dbg(component->dev, "Cal error release\n"); 890 regmap_update_bits(cs35l34->regmap, 891 CS35L34_PROT_RELEASE_CTL, 892 CS35L34_CAL_ERR_RLS, 0); 893 regmap_update_bits(cs35l34->regmap, 894 CS35L34_PROT_RELEASE_CTL, 895 CS35L34_CAL_ERR_RLS, 896 CS35L34_CAL_ERR_RLS); 897 regmap_update_bits(cs35l34->regmap, 898 CS35L34_PROT_RELEASE_CTL, 899 CS35L34_CAL_ERR_RLS, 0); 900 /* note: amp will re-calibrate on next resume */ 901 } 902 } 903 904 if (sticky1 & CS35L34_ALIVE_ERR) 905 dev_err(component->dev, "Alive error\n"); 906 907 if (sticky1 & CS35L34_AMP_SHORT) { 908 dev_crit(component->dev, "Amp short error\n"); 909 910 /* error is no longer asserted; safe to reset */ 911 if (!(current1 & CS35L34_AMP_SHORT)) { 912 dev_dbg(component->dev, 913 "Amp short error release\n"); 914 regmap_update_bits(cs35l34->regmap, 915 CS35L34_PROT_RELEASE_CTL, 916 CS35L34_SHORT_RLS, 0); 917 regmap_update_bits(cs35l34->regmap, 918 CS35L34_PROT_RELEASE_CTL, 919 CS35L34_SHORT_RLS, 920 CS35L34_SHORT_RLS); 921 regmap_update_bits(cs35l34->regmap, 922 CS35L34_PROT_RELEASE_CTL, 923 CS35L34_SHORT_RLS, 0); 924 } 925 } 926 927 if (sticky1 & CS35L34_OTW) { 928 dev_crit(component->dev, "Over temperature warning\n"); 929 930 /* error is no longer asserted; safe to reset */ 931 if (!(current1 & CS35L34_OTW)) { 932 dev_dbg(component->dev, 933 "Over temperature warning release\n"); 934 regmap_update_bits(cs35l34->regmap, 935 CS35L34_PROT_RELEASE_CTL, 936 CS35L34_OTW_RLS, 0); 937 regmap_update_bits(cs35l34->regmap, 938 CS35L34_PROT_RELEASE_CTL, 939 CS35L34_OTW_RLS, 940 CS35L34_OTW_RLS); 941 regmap_update_bits(cs35l34->regmap, 942 CS35L34_PROT_RELEASE_CTL, 943 CS35L34_OTW_RLS, 0); 944 } 945 } 946 947 if (sticky1 & CS35L34_OTE) { 948 dev_crit(component->dev, "Over temperature error\n"); 949 950 /* error is no longer asserted; safe to reset */ 951 if (!(current1 & CS35L34_OTE)) { 952 dev_dbg(component->dev, 953 "Over temperature error release\n"); 954 regmap_update_bits(cs35l34->regmap, 955 CS35L34_PROT_RELEASE_CTL, 956 CS35L34_OTE_RLS, 0); 957 regmap_update_bits(cs35l34->regmap, 958 CS35L34_PROT_RELEASE_CTL, 959 CS35L34_OTE_RLS, 960 CS35L34_OTE_RLS); 961 regmap_update_bits(cs35l34->regmap, 962 CS35L34_PROT_RELEASE_CTL, 963 CS35L34_OTE_RLS, 0); 964 } 965 } 966 967 if (sticky3 & CS35L34_BST_HIGH) { 968 dev_crit(component->dev, "VBST too high error; powering off!\n"); 969 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2, 970 CS35L34_PDN_AMP, CS35L34_PDN_AMP); 971 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1, 972 CS35L34_PDN_ALL, CS35L34_PDN_ALL); 973 } 974 975 if (sticky3 & CS35L34_LBST_SHORT) { 976 dev_crit(component->dev, "LBST short error; powering off!\n"); 977 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2, 978 CS35L34_PDN_AMP, CS35L34_PDN_AMP); 979 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1, 980 CS35L34_PDN_ALL, CS35L34_PDN_ALL); 981 } 982 983 return IRQ_HANDLED; 984} 985 986static const char * const cs35l34_core_supplies[] = { 987 "VA", 988 "VP", 989}; 990 991static int cs35l34_i2c_probe(struct i2c_client *i2c_client, 992 const struct i2c_device_id *id) 993{ 994 struct cs35l34_private *cs35l34; 995 struct cs35l34_platform_data *pdata = 996 dev_get_platdata(&i2c_client->dev); 997 int i; 998 int ret; 999 unsigned int devid = 0; 1000 unsigned int reg; 1001 1002 cs35l34 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l34), GFP_KERNEL); 1003 if (!cs35l34) 1004 return -ENOMEM; 1005 1006 i2c_set_clientdata(i2c_client, cs35l34); 1007 cs35l34->regmap = devm_regmap_init_i2c(i2c_client, &cs35l34_regmap); 1008 if (IS_ERR(cs35l34->regmap)) { 1009 ret = PTR_ERR(cs35l34->regmap); 1010 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1011 return ret; 1012 } 1013 1014 cs35l34->num_core_supplies = ARRAY_SIZE(cs35l34_core_supplies); 1015 for (i = 0; i < ARRAY_SIZE(cs35l34_core_supplies); i++) 1016 cs35l34->core_supplies[i].supply = cs35l34_core_supplies[i]; 1017 1018 ret = devm_regulator_bulk_get(&i2c_client->dev, 1019 cs35l34->num_core_supplies, 1020 cs35l34->core_supplies); 1021 if (ret != 0) { 1022 dev_err(&i2c_client->dev, 1023 "Failed to request core supplies %d\n", ret); 1024 return ret; 1025 } 1026 1027 ret = regulator_bulk_enable(cs35l34->num_core_supplies, 1028 cs35l34->core_supplies); 1029 if (ret != 0) { 1030 dev_err(&i2c_client->dev, 1031 "Failed to enable core supplies: %d\n", ret); 1032 return ret; 1033 } 1034 1035 if (pdata) { 1036 cs35l34->pdata = *pdata; 1037 } else { 1038 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata), 1039 GFP_KERNEL); 1040 if (!pdata) 1041 return -ENOMEM; 1042 1043 if (i2c_client->dev.of_node) { 1044 ret = cs35l34_handle_of_data(i2c_client, pdata); 1045 if (ret != 0) 1046 return ret; 1047 1048 } 1049 cs35l34->pdata = *pdata; 1050 } 1051 1052 ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL, 1053 cs35l34_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1054 "cs35l34", cs35l34); 1055 if (ret != 0) 1056 dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret); 1057 1058 cs35l34->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1059 "reset", GPIOD_OUT_LOW); 1060 if (IS_ERR(cs35l34->reset_gpio)) 1061 return PTR_ERR(cs35l34->reset_gpio); 1062 1063 gpiod_set_value_cansleep(cs35l34->reset_gpio, 1); 1064 1065 msleep(CS35L34_START_DELAY); 1066 1067 ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_AB, ®); 1068 1069 devid = (reg & 0xFF) << 12; 1070 ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_CD, ®); 1071 devid |= (reg & 0xFF) << 4; 1072 ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_E, ®); 1073 devid |= (reg & 0xF0) >> 4; 1074 1075 if (devid != CS35L34_CHIP_ID) { 1076 dev_err(&i2c_client->dev, 1077 "CS35l34 Device ID (%X). Expected ID %X\n", 1078 devid, CS35L34_CHIP_ID); 1079 ret = -ENODEV; 1080 goto err_regulator; 1081 } 1082 1083 ret = regmap_read(cs35l34->regmap, CS35L34_REV_ID, ®); 1084 if (ret < 0) { 1085 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1086 goto err_regulator; 1087 } 1088 1089 dev_info(&i2c_client->dev, 1090 "Cirrus Logic CS35l34 (%x), Revision: %02X\n", devid, 1091 reg & 0xFF); 1092 1093 /* Unmask critical interrupts */ 1094 regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_1, 1095 CS35L34_M_CAL_ERR | CS35L34_M_ALIVE_ERR | 1096 CS35L34_M_AMP_SHORT | CS35L34_M_OTW | 1097 CS35L34_M_OTE, 0); 1098 regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_3, 1099 CS35L34_M_BST_HIGH | CS35L34_M_LBST_SHORT, 0); 1100 1101 pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100); 1102 pm_runtime_use_autosuspend(&i2c_client->dev); 1103 pm_runtime_set_active(&i2c_client->dev); 1104 pm_runtime_enable(&i2c_client->dev); 1105 1106 ret = devm_snd_soc_register_component(&i2c_client->dev, 1107 &soc_component_dev_cs35l34, &cs35l34_dai, 1); 1108 if (ret < 0) { 1109 dev_err(&i2c_client->dev, 1110 "%s: Register component failed\n", __func__); 1111 goto err_regulator; 1112 } 1113 1114 return 0; 1115 1116err_regulator: 1117 regulator_bulk_disable(cs35l34->num_core_supplies, 1118 cs35l34->core_supplies); 1119 1120 return ret; 1121} 1122 1123static int cs35l34_i2c_remove(struct i2c_client *client) 1124{ 1125 struct cs35l34_private *cs35l34 = i2c_get_clientdata(client); 1126 1127 gpiod_set_value_cansleep(cs35l34->reset_gpio, 0); 1128 1129 pm_runtime_disable(&client->dev); 1130 regulator_bulk_disable(cs35l34->num_core_supplies, 1131 cs35l34->core_supplies); 1132 1133 return 0; 1134} 1135 1136static int __maybe_unused cs35l34_runtime_resume(struct device *dev) 1137{ 1138 struct cs35l34_private *cs35l34 = dev_get_drvdata(dev); 1139 int ret; 1140 1141 ret = regulator_bulk_enable(cs35l34->num_core_supplies, 1142 cs35l34->core_supplies); 1143 1144 if (ret != 0) { 1145 dev_err(dev, "Failed to enable core supplies: %d\n", 1146 ret); 1147 return ret; 1148 } 1149 1150 regcache_cache_only(cs35l34->regmap, false); 1151 1152 gpiod_set_value_cansleep(cs35l34->reset_gpio, 1); 1153 msleep(CS35L34_START_DELAY); 1154 1155 ret = regcache_sync(cs35l34->regmap); 1156 if (ret != 0) { 1157 dev_err(dev, "Failed to restore register cache\n"); 1158 goto err; 1159 } 1160 return 0; 1161err: 1162 regcache_cache_only(cs35l34->regmap, true); 1163 regulator_bulk_disable(cs35l34->num_core_supplies, 1164 cs35l34->core_supplies); 1165 1166 return ret; 1167} 1168 1169static int __maybe_unused cs35l34_runtime_suspend(struct device *dev) 1170{ 1171 struct cs35l34_private *cs35l34 = dev_get_drvdata(dev); 1172 1173 regcache_cache_only(cs35l34->regmap, true); 1174 regcache_mark_dirty(cs35l34->regmap); 1175 1176 gpiod_set_value_cansleep(cs35l34->reset_gpio, 0); 1177 1178 regulator_bulk_disable(cs35l34->num_core_supplies, 1179 cs35l34->core_supplies); 1180 1181 return 0; 1182} 1183 1184static const struct dev_pm_ops cs35l34_pm_ops = { 1185 SET_RUNTIME_PM_OPS(cs35l34_runtime_suspend, 1186 cs35l34_runtime_resume, 1187 NULL) 1188}; 1189 1190static const struct of_device_id cs35l34_of_match[] = { 1191 {.compatible = "cirrus,cs35l34"}, 1192 {}, 1193}; 1194MODULE_DEVICE_TABLE(of, cs35l34_of_match); 1195 1196static const struct i2c_device_id cs35l34_id[] = { 1197 {"cs35l34", 0}, 1198 {} 1199}; 1200MODULE_DEVICE_TABLE(i2c, cs35l34_id); 1201 1202static struct i2c_driver cs35l34_i2c_driver = { 1203 .driver = { 1204 .name = "cs35l34", 1205 .pm = &cs35l34_pm_ops, 1206 .of_match_table = cs35l34_of_match, 1207 1208 }, 1209 .id_table = cs35l34_id, 1210 .probe = cs35l34_i2c_probe, 1211 .remove = cs35l34_i2c_remove, 1212 1213}; 1214 1215static int __init cs35l34_modinit(void) 1216{ 1217 int ret; 1218 1219 ret = i2c_add_driver(&cs35l34_i2c_driver); 1220 if (ret != 0) { 1221 pr_err("Failed to register CS35l34 I2C driver: %d\n", ret); 1222 return ret; 1223 } 1224 return 0; 1225} 1226module_init(cs35l34_modinit); 1227 1228static void __exit cs35l34_exit(void) 1229{ 1230 i2c_del_driver(&cs35l34_i2c_driver); 1231} 1232module_exit(cs35l34_exit); 1233 1234MODULE_DESCRIPTION("ASoC CS35l34 driver"); 1235MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>"); 1236MODULE_LICENSE("GPL"); 1237