1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * cs35l33.c -- CS35L33 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: Paul Handrigan <paul.handrigan@cirrus.com> 8 */ 9#include <linux/module.h> 10#include <linux/moduleparam.h> 11#include <linux/kernel.h> 12#include <linux/init.h> 13#include <linux/delay.h> 14#include <linux/i2c.h> 15#include <linux/slab.h> 16#include <linux/workqueue.h> 17#include <linux/platform_device.h> 18#include <sound/core.h> 19#include <sound/pcm.h> 20#include <sound/pcm_params.h> 21#include <sound/soc.h> 22#include <sound/soc-dapm.h> 23#include <sound/initval.h> 24#include <sound/tlv.h> 25#include <linux/gpio/consumer.h> 26#include <sound/cs35l33.h> 27#include <linux/pm_runtime.h> 28#include <linux/regulator/consumer.h> 29#include <linux/regulator/machine.h> 30#include <linux/of.h> 31#include <linux/of_device.h> 32#include <linux/of_irq.h> 33 34#include "cs35l33.h" 35 36#define CS35L33_BOOT_DELAY 50 37 38struct cs35l33_private { 39 struct snd_soc_component *component; 40 struct cs35l33_pdata pdata; 41 struct regmap *regmap; 42 struct gpio_desc *reset_gpio; 43 bool amp_cal; 44 int mclk_int; 45 struct regulator_bulk_data core_supplies[2]; 46 int num_core_supplies; 47 bool is_tdm_mode; 48 bool enable_soft_ramp; 49}; 50 51static const struct reg_default cs35l33_reg[] = { 52 {CS35L33_PWRCTL1, 0x85}, 53 {CS35L33_PWRCTL2, 0xFE}, 54 {CS35L33_CLK_CTL, 0x0C}, 55 {CS35L33_BST_PEAK_CTL, 0x90}, 56 {CS35L33_PROTECT_CTL, 0x55}, 57 {CS35L33_BST_CTL1, 0x00}, 58 {CS35L33_BST_CTL2, 0x01}, 59 {CS35L33_ADSP_CTL, 0x00}, 60 {CS35L33_ADC_CTL, 0xC8}, 61 {CS35L33_DAC_CTL, 0x14}, 62 {CS35L33_DIG_VOL_CTL, 0x00}, 63 {CS35L33_CLASSD_CTL, 0x04}, 64 {CS35L33_AMP_CTL, 0x90}, 65 {CS35L33_INT_MASK_1, 0xFF}, 66 {CS35L33_INT_MASK_2, 0xFF}, 67 {CS35L33_DIAG_LOCK, 0x00}, 68 {CS35L33_DIAG_CTRL_1, 0x40}, 69 {CS35L33_DIAG_CTRL_2, 0x00}, 70 {CS35L33_HG_MEMLDO_CTL, 0x62}, 71 {CS35L33_HG_REL_RATE, 0x03}, 72 {CS35L33_LDO_DEL, 0x12}, 73 {CS35L33_HG_HEAD, 0x0A}, 74 {CS35L33_HG_EN, 0x05}, 75 {CS35L33_TX_VMON, 0x00}, 76 {CS35L33_TX_IMON, 0x03}, 77 {CS35L33_TX_VPMON, 0x02}, 78 {CS35L33_TX_VBSTMON, 0x05}, 79 {CS35L33_TX_FLAG, 0x06}, 80 {CS35L33_TX_EN1, 0x00}, 81 {CS35L33_TX_EN2, 0x00}, 82 {CS35L33_TX_EN3, 0x00}, 83 {CS35L33_TX_EN4, 0x00}, 84 {CS35L33_RX_AUD, 0x40}, 85 {CS35L33_RX_SPLY, 0x03}, 86 {CS35L33_RX_ALIVE, 0x04}, 87 {CS35L33_BST_CTL4, 0x63}, 88}; 89 90static const struct reg_sequence cs35l33_patch[] = { 91 { 0x00, 0x99, 0 }, 92 { 0x59, 0x02, 0 }, 93 { 0x52, 0x30, 0 }, 94 { 0x39, 0x45, 0 }, 95 { 0x57, 0x30, 0 }, 96 { 0x2C, 0x68, 0 }, 97 { 0x00, 0x00, 0 }, 98}; 99 100static bool cs35l33_volatile_register(struct device *dev, unsigned int reg) 101{ 102 switch (reg) { 103 case CS35L33_DEVID_AB: 104 case CS35L33_DEVID_CD: 105 case CS35L33_DEVID_E: 106 case CS35L33_REV_ID: 107 case CS35L33_INT_STATUS_1: 108 case CS35L33_INT_STATUS_2: 109 case CS35L33_HG_STATUS: 110 return true; 111 default: 112 return false; 113 } 114} 115 116static bool cs35l33_writeable_register(struct device *dev, unsigned int reg) 117{ 118 switch (reg) { 119 /* these are read only registers */ 120 case CS35L33_DEVID_AB: 121 case CS35L33_DEVID_CD: 122 case CS35L33_DEVID_E: 123 case CS35L33_REV_ID: 124 case CS35L33_INT_STATUS_1: 125 case CS35L33_INT_STATUS_2: 126 case CS35L33_HG_STATUS: 127 return false; 128 default: 129 return true; 130 } 131} 132 133static bool cs35l33_readable_register(struct device *dev, unsigned int reg) 134{ 135 switch (reg) { 136 case CS35L33_DEVID_AB: 137 case CS35L33_DEVID_CD: 138 case CS35L33_DEVID_E: 139 case CS35L33_REV_ID: 140 case CS35L33_PWRCTL1: 141 case CS35L33_PWRCTL2: 142 case CS35L33_CLK_CTL: 143 case CS35L33_BST_PEAK_CTL: 144 case CS35L33_PROTECT_CTL: 145 case CS35L33_BST_CTL1: 146 case CS35L33_BST_CTL2: 147 case CS35L33_ADSP_CTL: 148 case CS35L33_ADC_CTL: 149 case CS35L33_DAC_CTL: 150 case CS35L33_DIG_VOL_CTL: 151 case CS35L33_CLASSD_CTL: 152 case CS35L33_AMP_CTL: 153 case CS35L33_INT_MASK_1: 154 case CS35L33_INT_MASK_2: 155 case CS35L33_INT_STATUS_1: 156 case CS35L33_INT_STATUS_2: 157 case CS35L33_DIAG_LOCK: 158 case CS35L33_DIAG_CTRL_1: 159 case CS35L33_DIAG_CTRL_2: 160 case CS35L33_HG_MEMLDO_CTL: 161 case CS35L33_HG_REL_RATE: 162 case CS35L33_LDO_DEL: 163 case CS35L33_HG_HEAD: 164 case CS35L33_HG_EN: 165 case CS35L33_TX_VMON: 166 case CS35L33_TX_IMON: 167 case CS35L33_TX_VPMON: 168 case CS35L33_TX_VBSTMON: 169 case CS35L33_TX_FLAG: 170 case CS35L33_TX_EN1: 171 case CS35L33_TX_EN2: 172 case CS35L33_TX_EN3: 173 case CS35L33_TX_EN4: 174 case CS35L33_RX_AUD: 175 case CS35L33_RX_SPLY: 176 case CS35L33_RX_ALIVE: 177 case CS35L33_BST_CTL4: 178 return true; 179 default: 180 return false; 181 } 182} 183 184static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0); 185static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0); 186 187static const struct snd_kcontrol_new cs35l33_snd_controls[] = { 188 189 SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL, 190 4, 0x09, 0, classd_ctl_tlv), 191 SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL, 192 0, 0x34, 0xE4, dac_tlv), 193}; 194 195static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w, 196 struct snd_kcontrol *kcontrol, int event) 197{ 198 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 199 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 200 201 switch (event) { 202 case SND_SOC_DAPM_POST_PMU: 203 if (!priv->amp_cal) { 204 usleep_range(8000, 9000); 205 priv->amp_cal = true; 206 regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL, 207 CS35L33_AMP_CAL, 0); 208 dev_dbg(component->dev, "Amp calibration done\n"); 209 } 210 dev_dbg(component->dev, "Amp turned on\n"); 211 break; 212 case SND_SOC_DAPM_POST_PMD: 213 dev_dbg(component->dev, "Amp turned off\n"); 214 break; 215 default: 216 dev_err(component->dev, "Invalid event = 0x%x\n", event); 217 break; 218 } 219 220 return 0; 221} 222 223static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w, 224 struct snd_kcontrol *kcontrol, int event) 225{ 226 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 227 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 228 unsigned int val; 229 230 switch (event) { 231 case SND_SOC_DAPM_PRE_PMU: 232 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, 233 CS35L33_PDN_BST, 0); 234 val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM; 235 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 236 CS35L33_PDN_TDM, val); 237 dev_dbg(component->dev, "BST turned on\n"); 238 break; 239 case SND_SOC_DAPM_POST_PMU: 240 dev_dbg(component->dev, "SDIN turned on\n"); 241 if (!priv->amp_cal) { 242 regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL, 243 CS35L33_AMP_CAL, CS35L33_AMP_CAL); 244 dev_dbg(component->dev, "Amp calibration started\n"); 245 usleep_range(10000, 11000); 246 } 247 break; 248 case SND_SOC_DAPM_POST_PMD: 249 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 250 CS35L33_PDN_TDM, CS35L33_PDN_TDM); 251 usleep_range(4000, 4100); 252 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, 253 CS35L33_PDN_BST, CS35L33_PDN_BST); 254 dev_dbg(component->dev, "BST and SDIN turned off\n"); 255 break; 256 default: 257 dev_err(component->dev, "Invalid event = 0x%x\n", event); 258 259 } 260 261 return 0; 262} 263 264static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w, 265 struct snd_kcontrol *kcontrol, int event) 266{ 267 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 268 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 269 unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM; 270 unsigned int mask2 = CS35L33_SDOUT_3ST_TDM; 271 unsigned int val, val2; 272 273 switch (event) { 274 case SND_SOC_DAPM_PRE_PMU: 275 if (priv->is_tdm_mode) { 276 /* set sdout_3st_i2s and reset pdn_tdm */ 277 val = CS35L33_SDOUT_3ST_I2S; 278 /* reset sdout_3st_tdm */ 279 val2 = 0; 280 } else { 281 /* reset sdout_3st_i2s and set pdn_tdm */ 282 val = CS35L33_PDN_TDM; 283 /* set sdout_3st_tdm */ 284 val2 = CS35L33_SDOUT_3ST_TDM; 285 } 286 dev_dbg(component->dev, "SDOUT turned on\n"); 287 break; 288 case SND_SOC_DAPM_PRE_PMD: 289 val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM; 290 val2 = CS35L33_SDOUT_3ST_TDM; 291 dev_dbg(component->dev, "SDOUT turned off\n"); 292 break; 293 default: 294 dev_err(component->dev, "Invalid event = 0x%x\n", event); 295 return 0; 296 } 297 298 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 299 mask, val); 300 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 301 mask2, val2); 302 303 return 0; 304} 305 306static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = { 307 308 SND_SOC_DAPM_OUTPUT("SPK"), 309 SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0, 310 cs35l33_spkrdrv_event, 311 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 312 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2, 313 2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU | 314 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 315 316 SND_SOC_DAPM_INPUT("MON"), 317 318 SND_SOC_DAPM_ADC("VMON", NULL, 319 CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1), 320 SND_SOC_DAPM_ADC("IMON", NULL, 321 CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1), 322 SND_SOC_DAPM_ADC("VPMON", NULL, 323 CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1), 324 SND_SOC_DAPM_ADC("VBSTMON", NULL, 325 CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1), 326 327 SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0, 328 cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU | 329 SND_SOC_DAPM_PRE_PMD), 330}; 331 332static const struct snd_soc_dapm_route cs35l33_audio_map[] = { 333 {"SDIN", NULL, "CS35L33 Playback"}, 334 {"SPKDRV", NULL, "SDIN"}, 335 {"SPK", NULL, "SPKDRV"}, 336 337 {"VMON", NULL, "MON"}, 338 {"IMON", NULL, "MON"}, 339 340 {"SDOUT", NULL, "VMON"}, 341 {"SDOUT", NULL, "IMON"}, 342 {"CS35L33 Capture", NULL, "SDOUT"}, 343}; 344 345static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = { 346 {"SPKDRV", NULL, "VPMON"}, 347 {"VPMON", NULL, "CS35L33 Playback"}, 348}; 349 350static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = { 351 {"SDOUT", NULL, "VPMON"}, 352 {"VPMON", NULL, "MON"}, 353 {"SDOUT", NULL, "VBSTMON"}, 354 {"VBSTMON", NULL, "MON"}, 355}; 356 357static int cs35l33_set_bias_level(struct snd_soc_component *component, 358 enum snd_soc_bias_level level) 359{ 360 unsigned int val; 361 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 362 363 switch (level) { 364 case SND_SOC_BIAS_ON: 365 break; 366 case SND_SOC_BIAS_PREPARE: 367 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, 368 CS35L33_PDN_ALL, 0); 369 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 370 CS35L33_MCLKDIS, 0); 371 break; 372 case SND_SOC_BIAS_STANDBY: 373 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, 374 CS35L33_PDN_ALL, CS35L33_PDN_ALL); 375 regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val); 376 usleep_range(1000, 1100); 377 if (val & CS35L33_PDN_DONE) 378 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 379 CS35L33_MCLKDIS, CS35L33_MCLKDIS); 380 break; 381 case SND_SOC_BIAS_OFF: 382 break; 383 default: 384 return -EINVAL; 385 } 386 387 return 0; 388} 389 390struct cs35l33_mclk_div { 391 int mclk; 392 int srate; 393 u8 adsp_rate; 394 u8 int_fs_ratio; 395}; 396 397static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = { 398 /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */ 399 {5644800, 11025, 0x4, CS35L33_INT_FS_RATE}, 400 {5644800, 22050, 0x8, CS35L33_INT_FS_RATE}, 401 {5644800, 44100, 0xC, CS35L33_INT_FS_RATE}, 402 403 {6000000, 8000, 0x1, 0}, 404 {6000000, 11025, 0x2, 0}, 405 {6000000, 11029, 0x3, 0}, 406 {6000000, 12000, 0x4, 0}, 407 {6000000, 16000, 0x5, 0}, 408 {6000000, 22050, 0x6, 0}, 409 {6000000, 22059, 0x7, 0}, 410 {6000000, 24000, 0x8, 0}, 411 {6000000, 32000, 0x9, 0}, 412 {6000000, 44100, 0xA, 0}, 413 {6000000, 44118, 0xB, 0}, 414 {6000000, 48000, 0xC, 0}, 415 416 {6144000, 8000, 0x1, CS35L33_INT_FS_RATE}, 417 {6144000, 12000, 0x4, CS35L33_INT_FS_RATE}, 418 {6144000, 16000, 0x5, CS35L33_INT_FS_RATE}, 419 {6144000, 24000, 0x8, CS35L33_INT_FS_RATE}, 420 {6144000, 32000, 0x9, CS35L33_INT_FS_RATE}, 421 {6144000, 48000, 0xC, CS35L33_INT_FS_RATE}, 422}; 423 424static int cs35l33_get_mclk_coeff(int mclk, int srate) 425{ 426 int i; 427 428 for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) { 429 if (cs35l33_mclk_coeffs[i].mclk == mclk && 430 cs35l33_mclk_coeffs[i].srate == srate) 431 return i; 432 } 433 return -EINVAL; 434} 435 436static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 437{ 438 struct snd_soc_component *component = codec_dai->component; 439 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 440 441 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 442 case SND_SOC_DAIFMT_CBM_CFM: 443 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL, 444 CS35L33_MS_MASK, CS35L33_MS_MASK); 445 dev_dbg(component->dev, "Audio port in master mode\n"); 446 break; 447 case SND_SOC_DAIFMT_CBS_CFS: 448 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL, 449 CS35L33_MS_MASK, 0); 450 dev_dbg(component->dev, "Audio port in slave mode\n"); 451 break; 452 default: 453 return -EINVAL; 454 } 455 456 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 457 case SND_SOC_DAIFMT_DSP_A: 458 /* 459 * tdm mode in cs35l33 resembles dsp-a mode very 460 * closely, it is dsp-a with fsync shifted left by half bclk 461 */ 462 priv->is_tdm_mode = true; 463 dev_dbg(component->dev, "Audio port in TDM mode\n"); 464 break; 465 case SND_SOC_DAIFMT_I2S: 466 priv->is_tdm_mode = false; 467 dev_dbg(component->dev, "Audio port in I2S mode\n"); 468 break; 469 default: 470 return -EINVAL; 471 } 472 473 return 0; 474} 475 476static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream, 477 struct snd_pcm_hw_params *params, 478 struct snd_soc_dai *dai) 479{ 480 struct snd_soc_component *component = dai->component; 481 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 482 int sample_size = params_width(params); 483 int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params)); 484 485 if (coeff < 0) 486 return coeff; 487 488 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 489 CS35L33_ADSP_FS | CS35L33_INT_FS_RATE, 490 cs35l33_mclk_coeffs[coeff].int_fs_ratio 491 | cs35l33_mclk_coeffs[coeff].adsp_rate); 492 493 if (priv->is_tdm_mode) { 494 sample_size = (sample_size / 8) - 1; 495 if (sample_size > 2) 496 sample_size = 2; 497 regmap_update_bits(priv->regmap, CS35L33_RX_AUD, 498 CS35L33_AUDIN_RX_DEPTH, 499 sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT); 500 } 501 502 dev_dbg(component->dev, "sample rate=%d, bits per sample=%d\n", 503 params_rate(params), params_width(params)); 504 505 return 0; 506} 507 508static const unsigned int cs35l33_src_rates[] = { 509 8000, 11025, 11029, 12000, 16000, 22050, 510 22059, 24000, 32000, 44100, 44118, 48000 511}; 512 513static const struct snd_pcm_hw_constraint_list cs35l33_constraints = { 514 .count = ARRAY_SIZE(cs35l33_src_rates), 515 .list = cs35l33_src_rates, 516}; 517 518static int cs35l33_pcm_startup(struct snd_pcm_substream *substream, 519 struct snd_soc_dai *dai) 520{ 521 snd_pcm_hw_constraint_list(substream->runtime, 0, 522 SNDRV_PCM_HW_PARAM_RATE, 523 &cs35l33_constraints); 524 return 0; 525} 526 527static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate) 528{ 529 struct snd_soc_component *component = dai->component; 530 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 531 532 if (tristate) { 533 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 534 CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S); 535 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 536 CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM); 537 } else { 538 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 539 CS35L33_SDOUT_3ST_I2S, 0); 540 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 541 CS35L33_SDOUT_3ST_TDM, 0); 542 } 543 544 return 0; 545} 546 547static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 548 unsigned int rx_mask, int slots, int slot_width) 549{ 550 struct snd_soc_component *component = dai->component; 551 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 552 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 553 unsigned int reg, bit_pos, i; 554 int slot, slot_num; 555 556 if (slot_width != 8) 557 return -EINVAL; 558 559 /* scan rx_mask for aud slot */ 560 slot = ffs(rx_mask) - 1; 561 if (slot >= 0) { 562 regmap_update_bits(priv->regmap, CS35L33_RX_AUD, 563 CS35L33_X_LOC, slot); 564 dev_dbg(component->dev, "Audio starts from slots %d", slot); 565 } 566 567 /* 568 * scan tx_mask: vmon(2 slots); imon (2 slots); 569 * vpmon (1 slot) vbstmon (1 slot) 570 */ 571 slot = ffs(tx_mask) - 1; 572 slot_num = 0; 573 574 for (i = 0; i < 2 ; i++) { 575 /* disable vpmon/vbstmon: enable later if set in tx_mask */ 576 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i, 577 CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE 578 | CS35L33_X_LOC); 579 } 580 581 /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/ 582 snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route, 583 ARRAY_SIZE(cs35l33_vp_vbst_mon_route)); 584 585 while (slot >= 0) { 586 /* configure VMON_TX_LOC */ 587 if (slot_num == 0) { 588 regmap_update_bits(priv->regmap, CS35L33_TX_VMON, 589 CS35L33_X_STATE | CS35L33_X_LOC, slot); 590 dev_dbg(component->dev, "VMON enabled in slots %d-%d", 591 slot, slot + 1); 592 } 593 594 /* configure IMON_TX_LOC */ 595 if (slot_num == 3) { 596 regmap_update_bits(priv->regmap, CS35L33_TX_IMON, 597 CS35L33_X_STATE | CS35L33_X_LOC, slot); 598 dev_dbg(component->dev, "IMON enabled in slots %d-%d", 599 slot, slot + 1); 600 } 601 602 /* configure VPMON_TX_LOC */ 603 if (slot_num == 4) { 604 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON, 605 CS35L33_X_STATE | CS35L33_X_LOC, slot); 606 snd_soc_dapm_add_routes(dapm, 607 &cs35l33_vp_vbst_mon_route[0], 2); 608 dev_dbg(component->dev, "VPMON enabled in slots %d", slot); 609 } 610 611 /* configure VBSTMON_TX_LOC */ 612 if (slot_num == 5) { 613 regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON, 614 CS35L33_X_STATE | CS35L33_X_LOC, slot); 615 snd_soc_dapm_add_routes(dapm, 616 &cs35l33_vp_vbst_mon_route[2], 2); 617 dev_dbg(component->dev, 618 "VBSTMON enabled in slots %d", slot); 619 } 620 621 /* Enable the relevant tx slot */ 622 reg = CS35L33_TX_EN4 - (slot/8); 623 bit_pos = slot - ((slot / 8) * (8)); 624 regmap_update_bits(priv->regmap, reg, 625 1 << bit_pos, 1 << bit_pos); 626 627 tx_mask &= ~(1 << slot); 628 slot = ffs(tx_mask) - 1; 629 slot_num++; 630 } 631 632 return 0; 633} 634 635static int cs35l33_component_set_sysclk(struct snd_soc_component *component, 636 int clk_id, int source, unsigned int freq, int dir) 637{ 638 struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component); 639 640 switch (freq) { 641 case CS35L33_MCLK_5644: 642 case CS35L33_MCLK_6: 643 case CS35L33_MCLK_6144: 644 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, 645 CS35L33_MCLKDIV2, 0); 646 cs35l33->mclk_int = freq; 647 break; 648 case CS35L33_MCLK_11289: 649 case CS35L33_MCLK_12: 650 case CS35L33_MCLK_12288: 651 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, 652 CS35L33_MCLKDIV2, CS35L33_MCLKDIV2); 653 cs35l33->mclk_int = freq/2; 654 break; 655 default: 656 cs35l33->mclk_int = 0; 657 return -EINVAL; 658 } 659 660 dev_dbg(component->dev, "external mclk freq=%d, internal mclk freq=%d\n", 661 freq, cs35l33->mclk_int); 662 663 return 0; 664} 665 666static const struct snd_soc_dai_ops cs35l33_ops = { 667 .startup = cs35l33_pcm_startup, 668 .set_tristate = cs35l33_set_tristate, 669 .set_fmt = cs35l33_set_dai_fmt, 670 .hw_params = cs35l33_pcm_hw_params, 671 .set_tdm_slot = cs35l33_set_tdm_slot, 672}; 673 674static struct snd_soc_dai_driver cs35l33_dai = { 675 .name = "cs35l33-dai", 676 .id = 0, 677 .playback = { 678 .stream_name = "CS35L33 Playback", 679 .channels_min = 1, 680 .channels_max = 1, 681 .rates = CS35L33_RATES, 682 .formats = CS35L33_FORMATS, 683 }, 684 .capture = { 685 .stream_name = "CS35L33 Capture", 686 .channels_min = 2, 687 .channels_max = 2, 688 .rates = CS35L33_RATES, 689 .formats = CS35L33_FORMATS, 690 }, 691 .ops = &cs35l33_ops, 692 .symmetric_rates = 1, 693}; 694 695static int cs35l33_set_hg_data(struct snd_soc_component *component, 696 struct cs35l33_pdata *pdata) 697{ 698 struct cs35l33_hg *hg_config = &pdata->hg_config; 699 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 700 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 701 702 if (hg_config->enable_hg_algo) { 703 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, 704 CS35L33_MEM_DEPTH_MASK, 705 hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT); 706 regmap_write(priv->regmap, CS35L33_HG_REL_RATE, 707 hg_config->release_rate); 708 regmap_update_bits(priv->regmap, CS35L33_HG_HEAD, 709 CS35L33_HD_RM_MASK, 710 hg_config->hd_rm << CS35L33_HD_RM_SHIFT); 711 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, 712 CS35L33_LDO_THLD_MASK, 713 hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT); 714 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, 715 CS35L33_LDO_DISABLE_MASK, 716 hg_config->ldo_path_disable << 717 CS35L33_LDO_DISABLE_SHIFT); 718 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, 719 CS35L33_LDO_ENTRY_DELAY_MASK, 720 hg_config->ldo_entry_delay << 721 CS35L33_LDO_ENTRY_DELAY_SHIFT); 722 if (hg_config->vp_hg_auto) { 723 regmap_update_bits(priv->regmap, CS35L33_HG_EN, 724 CS35L33_VP_HG_AUTO_MASK, 725 CS35L33_VP_HG_AUTO_MASK); 726 snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route, 727 ARRAY_SIZE(cs35l33_vphg_auto_route)); 728 } 729 regmap_update_bits(priv->regmap, CS35L33_HG_EN, 730 CS35L33_VP_HG_MASK, 731 hg_config->vp_hg << CS35L33_VP_HG_SHIFT); 732 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, 733 CS35L33_VP_HG_RATE_MASK, 734 hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT); 735 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, 736 CS35L33_VP_HG_VA_MASK, 737 hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT); 738 regmap_update_bits(priv->regmap, CS35L33_HG_EN, 739 CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK); 740 } 741 return 0; 742} 743 744static int cs35l33_set_bst_ipk(struct snd_soc_component *component, unsigned int bst) 745{ 746 struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component); 747 int ret = 0, steps = 0; 748 749 /* Boost current in uA */ 750 if (bst > 3600000 || bst < 1850000) { 751 dev_err(component->dev, "Invalid boost current %d\n", bst); 752 ret = -EINVAL; 753 goto err; 754 } 755 756 if (bst % 15625) { 757 dev_err(component->dev, "Current not a multiple of 15625uA (%d)\n", 758 bst); 759 ret = -EINVAL; 760 goto err; 761 } 762 763 while (bst > 1850000) { 764 bst -= 15625; 765 steps++; 766 } 767 768 regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL, 769 steps+0x70); 770 771err: 772 return ret; 773} 774 775static int cs35l33_probe(struct snd_soc_component *component) 776{ 777 struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component); 778 779 cs35l33->component = component; 780 pm_runtime_get_sync(component->dev); 781 782 regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL, 783 CS35L33_ALIVE_WD_DIS, 0x8); 784 regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2, 785 CS35L33_ALIVE_WD_DIS2, 786 CS35L33_ALIVE_WD_DIS2); 787 788 /* Set Platform Data */ 789 regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1, 790 CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl); 791 regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL, 792 CS35L33_AMP_DRV_SEL_MASK, 793 cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT); 794 795 if (cs35l33->pdata.boost_ipk) 796 cs35l33_set_bst_ipk(component, cs35l33->pdata.boost_ipk); 797 798 if (cs35l33->enable_soft_ramp) { 799 snd_soc_component_update_bits(component, CS35L33_DAC_CTL, 800 CS35L33_DIGSFT, CS35L33_DIGSFT); 801 snd_soc_component_update_bits(component, CS35L33_DAC_CTL, 802 CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate); 803 } else { 804 snd_soc_component_update_bits(component, CS35L33_DAC_CTL, 805 CS35L33_DIGSFT, 0); 806 } 807 808 /* update IMON scaling rate if different from default of 0x8 */ 809 if (cs35l33->pdata.imon_adc_scale != 0x8) 810 snd_soc_component_update_bits(component, CS35L33_ADC_CTL, 811 CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale); 812 813 cs35l33_set_hg_data(component, &(cs35l33->pdata)); 814 815 /* 816 * unmask important interrupts that causes the chip to enter 817 * speaker safe mode and hence deserves user attention 818 */ 819 regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1, 820 CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT | 821 CS35L33_M_CAL_ERR, 0); 822 823 pm_runtime_put_sync(component->dev); 824 825 return 0; 826} 827 828static const struct snd_soc_component_driver soc_component_dev_cs35l33 = { 829 .probe = cs35l33_probe, 830 .set_bias_level = cs35l33_set_bias_level, 831 .set_sysclk = cs35l33_component_set_sysclk, 832 .controls = cs35l33_snd_controls, 833 .num_controls = ARRAY_SIZE(cs35l33_snd_controls), 834 .dapm_widgets = cs35l33_dapm_widgets, 835 .num_dapm_widgets = ARRAY_SIZE(cs35l33_dapm_widgets), 836 .dapm_routes = cs35l33_audio_map, 837 .num_dapm_routes = ARRAY_SIZE(cs35l33_audio_map), 838 .use_pmdown_time = 1, 839 .endianness = 1, 840 .non_legacy_dai_naming = 1, 841}; 842 843static const struct regmap_config cs35l33_regmap = { 844 .reg_bits = 8, 845 .val_bits = 8, 846 847 .max_register = CS35L33_MAX_REGISTER, 848 .reg_defaults = cs35l33_reg, 849 .num_reg_defaults = ARRAY_SIZE(cs35l33_reg), 850 .volatile_reg = cs35l33_volatile_register, 851 .readable_reg = cs35l33_readable_register, 852 .writeable_reg = cs35l33_writeable_register, 853 .cache_type = REGCACHE_RBTREE, 854 .use_single_read = true, 855 .use_single_write = true, 856}; 857 858static int __maybe_unused cs35l33_runtime_resume(struct device *dev) 859{ 860 struct cs35l33_private *cs35l33 = dev_get_drvdata(dev); 861 int ret; 862 863 dev_dbg(dev, "%s\n", __func__); 864 865 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0); 866 867 ret = regulator_bulk_enable(cs35l33->num_core_supplies, 868 cs35l33->core_supplies); 869 if (ret != 0) { 870 dev_err(dev, "Failed to enable core supplies: %d\n", ret); 871 return ret; 872 } 873 874 regcache_cache_only(cs35l33->regmap, false); 875 876 gpiod_set_value_cansleep(cs35l33->reset_gpio, 1); 877 878 msleep(CS35L33_BOOT_DELAY); 879 880 ret = regcache_sync(cs35l33->regmap); 881 if (ret != 0) { 882 dev_err(dev, "Failed to restore register cache\n"); 883 goto err; 884 } 885 886 return 0; 887 888err: 889 regcache_cache_only(cs35l33->regmap, true); 890 regulator_bulk_disable(cs35l33->num_core_supplies, 891 cs35l33->core_supplies); 892 893 return ret; 894} 895 896static int __maybe_unused cs35l33_runtime_suspend(struct device *dev) 897{ 898 struct cs35l33_private *cs35l33 = dev_get_drvdata(dev); 899 900 dev_dbg(dev, "%s\n", __func__); 901 902 /* redo the calibration in next power up */ 903 cs35l33->amp_cal = false; 904 905 regcache_cache_only(cs35l33->regmap, true); 906 regcache_mark_dirty(cs35l33->regmap); 907 regulator_bulk_disable(cs35l33->num_core_supplies, 908 cs35l33->core_supplies); 909 910 return 0; 911} 912 913static const struct dev_pm_ops cs35l33_pm_ops = { 914 SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend, 915 cs35l33_runtime_resume, 916 NULL) 917}; 918 919static int cs35l33_get_hg_data(const struct device_node *np, 920 struct cs35l33_pdata *pdata) 921{ 922 struct device_node *hg; 923 struct cs35l33_hg *hg_config = &pdata->hg_config; 924 u32 val32; 925 926 hg = of_get_child_by_name(np, "cirrus,hg-algo"); 927 hg_config->enable_hg_algo = hg ? true : false; 928 929 if (hg_config->enable_hg_algo) { 930 if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0) 931 hg_config->mem_depth = val32; 932 if (of_property_read_u32(hg, "cirrus,release-rate", 933 &val32) >= 0) 934 hg_config->release_rate = val32; 935 if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0) 936 hg_config->ldo_thld = val32; 937 if (of_property_read_u32(hg, "cirrus,ldo-path-disable", 938 &val32) >= 0) 939 hg_config->ldo_path_disable = val32; 940 if (of_property_read_u32(hg, "cirrus,ldo-entry-delay", 941 &val32) >= 0) 942 hg_config->ldo_entry_delay = val32; 943 944 hg_config->vp_hg_auto = of_property_read_bool(hg, 945 "cirrus,vp-hg-auto"); 946 947 if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0) 948 hg_config->vp_hg = val32; 949 if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0) 950 hg_config->vp_hg_rate = val32; 951 if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0) 952 hg_config->vp_hg_va = val32; 953 } 954 955 of_node_put(hg); 956 957 return 0; 958} 959 960static irqreturn_t cs35l33_irq_thread(int irq, void *data) 961{ 962 struct cs35l33_private *cs35l33 = data; 963 struct snd_soc_component *component = cs35l33->component; 964 unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2; 965 966 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2, 967 &sticky_val2); 968 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1, 969 &sticky_val1); 970 regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2); 971 regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1); 972 973 /* Check to see if the unmasked bits are active, 974 * if not then exit. 975 */ 976 if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2)) 977 return IRQ_NONE; 978 979 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1, 980 ¤t_val); 981 982 /* handle the interrupts */ 983 984 if (sticky_val1 & CS35L33_AMP_SHORT) { 985 dev_crit(component->dev, "Amp short error\n"); 986 if (!(current_val & CS35L33_AMP_SHORT)) { 987 dev_dbg(component->dev, 988 "Amp short error release\n"); 989 regmap_update_bits(cs35l33->regmap, 990 CS35L33_AMP_CTL, 991 CS35L33_AMP_SHORT_RLS, 0); 992 regmap_update_bits(cs35l33->regmap, 993 CS35L33_AMP_CTL, 994 CS35L33_AMP_SHORT_RLS, 995 CS35L33_AMP_SHORT_RLS); 996 regmap_update_bits(cs35l33->regmap, 997 CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS, 998 0); 999 } 1000 } 1001 1002 if (sticky_val1 & CS35L33_CAL_ERR) { 1003 dev_err(component->dev, "Cal error\n"); 1004 1005 /* redo the calibration in next power up */ 1006 cs35l33->amp_cal = false; 1007 1008 if (!(current_val & CS35L33_CAL_ERR)) { 1009 dev_dbg(component->dev, "Cal error release\n"); 1010 regmap_update_bits(cs35l33->regmap, 1011 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, 1012 0); 1013 regmap_update_bits(cs35l33->regmap, 1014 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, 1015 CS35L33_CAL_ERR_RLS); 1016 regmap_update_bits(cs35l33->regmap, 1017 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, 1018 0); 1019 } 1020 } 1021 1022 if (sticky_val1 & CS35L33_OTE) { 1023 dev_crit(component->dev, "Over temperature error\n"); 1024 if (!(current_val & CS35L33_OTE)) { 1025 dev_dbg(component->dev, 1026 "Over temperature error release\n"); 1027 regmap_update_bits(cs35l33->regmap, 1028 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0); 1029 regmap_update_bits(cs35l33->regmap, 1030 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 1031 CS35L33_OTE_RLS); 1032 regmap_update_bits(cs35l33->regmap, 1033 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0); 1034 } 1035 } 1036 1037 if (sticky_val1 & CS35L33_OTW) { 1038 dev_err(component->dev, "Over temperature warning\n"); 1039 if (!(current_val & CS35L33_OTW)) { 1040 dev_dbg(component->dev, 1041 "Over temperature warning release\n"); 1042 regmap_update_bits(cs35l33->regmap, 1043 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0); 1044 regmap_update_bits(cs35l33->regmap, 1045 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 1046 CS35L33_OTW_RLS); 1047 regmap_update_bits(cs35l33->regmap, 1048 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0); 1049 } 1050 } 1051 if (CS35L33_ALIVE_ERR & sticky_val1) 1052 dev_err(component->dev, "ERROR: ADSPCLK Interrupt\n"); 1053 1054 if (CS35L33_MCLK_ERR & sticky_val1) 1055 dev_err(component->dev, "ERROR: MCLK Interrupt\n"); 1056 1057 if (CS35L33_VMON_OVFL & sticky_val2) 1058 dev_err(component->dev, 1059 "ERROR: VMON Overflow Interrupt\n"); 1060 1061 if (CS35L33_IMON_OVFL & sticky_val2) 1062 dev_err(component->dev, 1063 "ERROR: IMON Overflow Interrupt\n"); 1064 1065 if (CS35L33_VPMON_OVFL & sticky_val2) 1066 dev_err(component->dev, 1067 "ERROR: VPMON Overflow Interrupt\n"); 1068 1069 return IRQ_HANDLED; 1070} 1071 1072static const char * const cs35l33_core_supplies[] = { 1073 "VA", 1074 "VP", 1075}; 1076 1077static int cs35l33_of_get_pdata(struct device *dev, 1078 struct cs35l33_private *cs35l33) 1079{ 1080 struct device_node *np = dev->of_node; 1081 struct cs35l33_pdata *pdata = &cs35l33->pdata; 1082 u32 val32; 1083 1084 if (!np) 1085 return 0; 1086 1087 if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) { 1088 pdata->boost_ctl = val32; 1089 pdata->amp_drv_sel = 1; 1090 } 1091 1092 if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) { 1093 pdata->ramp_rate = val32; 1094 cs35l33->enable_soft_ramp = true; 1095 } 1096 1097 if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0) 1098 pdata->boost_ipk = val32; 1099 1100 if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) { 1101 if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6)) 1102 pdata->imon_adc_scale = val32; 1103 else 1104 /* use default value */ 1105 pdata->imon_adc_scale = 0x8; 1106 } else { 1107 /* use default value */ 1108 pdata->imon_adc_scale = 0x8; 1109 } 1110 1111 cs35l33_get_hg_data(np, pdata); 1112 1113 return 0; 1114} 1115 1116static int cs35l33_i2c_probe(struct i2c_client *i2c_client, 1117 const struct i2c_device_id *id) 1118{ 1119 struct cs35l33_private *cs35l33; 1120 struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev); 1121 int ret, devid, i; 1122 unsigned int reg; 1123 1124 cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private), 1125 GFP_KERNEL); 1126 if (!cs35l33) 1127 return -ENOMEM; 1128 1129 i2c_set_clientdata(i2c_client, cs35l33); 1130 cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap); 1131 if (IS_ERR(cs35l33->regmap)) { 1132 ret = PTR_ERR(cs35l33->regmap); 1133 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1134 return ret; 1135 } 1136 1137 regcache_cache_only(cs35l33->regmap, true); 1138 1139 for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++) 1140 cs35l33->core_supplies[i].supply 1141 = cs35l33_core_supplies[i]; 1142 cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies); 1143 1144 ret = devm_regulator_bulk_get(&i2c_client->dev, 1145 cs35l33->num_core_supplies, 1146 cs35l33->core_supplies); 1147 if (ret != 0) { 1148 dev_err(&i2c_client->dev, 1149 "Failed to request core supplies: %d\n", 1150 ret); 1151 return ret; 1152 } 1153 1154 if (pdata) { 1155 cs35l33->pdata = *pdata; 1156 } else { 1157 cs35l33_of_get_pdata(&i2c_client->dev, cs35l33); 1158 pdata = &cs35l33->pdata; 1159 } 1160 1161 ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL, 1162 cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1163 "cs35l33", cs35l33); 1164 if (ret != 0) 1165 dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret); 1166 1167 /* We could issue !RST or skip it based on AMP topology */ 1168 cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1169 "reset", GPIOD_OUT_HIGH); 1170 if (IS_ERR(cs35l33->reset_gpio)) { 1171 dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n", 1172 __func__); 1173 return PTR_ERR(cs35l33->reset_gpio); 1174 } 1175 1176 ret = regulator_bulk_enable(cs35l33->num_core_supplies, 1177 cs35l33->core_supplies); 1178 if (ret != 0) { 1179 dev_err(&i2c_client->dev, 1180 "Failed to enable core supplies: %d\n", 1181 ret); 1182 return ret; 1183 } 1184 1185 gpiod_set_value_cansleep(cs35l33->reset_gpio, 1); 1186 1187 msleep(CS35L33_BOOT_DELAY); 1188 regcache_cache_only(cs35l33->regmap, false); 1189 1190 /* initialize codec */ 1191 ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_AB, ®); 1192 devid = (reg & 0xFF) << 12; 1193 ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_CD, ®); 1194 devid |= (reg & 0xFF) << 4; 1195 ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_E, ®); 1196 devid |= (reg & 0xF0) >> 4; 1197 1198 if (devid != CS35L33_CHIP_ID) { 1199 dev_err(&i2c_client->dev, 1200 "CS35L33 Device ID (%X). Expected ID %X\n", 1201 devid, CS35L33_CHIP_ID); 1202 ret = -EINVAL; 1203 goto err_enable; 1204 } 1205 1206 ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, ®); 1207 if (ret < 0) { 1208 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1209 goto err_enable; 1210 } 1211 1212 dev_info(&i2c_client->dev, 1213 "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF); 1214 1215 ret = regmap_register_patch(cs35l33->regmap, 1216 cs35l33_patch, ARRAY_SIZE(cs35l33_patch)); 1217 if (ret < 0) { 1218 dev_err(&i2c_client->dev, 1219 "Error in applying regmap patch: %d\n", ret); 1220 goto err_enable; 1221 } 1222 1223 /* disable mclk and tdm */ 1224 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, 1225 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM, 1226 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM); 1227 1228 pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100); 1229 pm_runtime_use_autosuspend(&i2c_client->dev); 1230 pm_runtime_set_active(&i2c_client->dev); 1231 pm_runtime_enable(&i2c_client->dev); 1232 1233 ret = devm_snd_soc_register_component(&i2c_client->dev, 1234 &soc_component_dev_cs35l33, &cs35l33_dai, 1); 1235 if (ret < 0) { 1236 dev_err(&i2c_client->dev, "%s: Register component failed\n", 1237 __func__); 1238 goto err_enable; 1239 } 1240 1241 return 0; 1242 1243err_enable: 1244 regulator_bulk_disable(cs35l33->num_core_supplies, 1245 cs35l33->core_supplies); 1246 1247 return ret; 1248} 1249 1250static int cs35l33_i2c_remove(struct i2c_client *client) 1251{ 1252 struct cs35l33_private *cs35l33 = i2c_get_clientdata(client); 1253 1254 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0); 1255 1256 pm_runtime_disable(&client->dev); 1257 regulator_bulk_disable(cs35l33->num_core_supplies, 1258 cs35l33->core_supplies); 1259 1260 return 0; 1261} 1262 1263static const struct of_device_id cs35l33_of_match[] = { 1264 { .compatible = "cirrus,cs35l33", }, 1265 {}, 1266}; 1267MODULE_DEVICE_TABLE(of, cs35l33_of_match); 1268 1269static const struct i2c_device_id cs35l33_id[] = { 1270 {"cs35l33", 0}, 1271 {} 1272}; 1273 1274MODULE_DEVICE_TABLE(i2c, cs35l33_id); 1275 1276static struct i2c_driver cs35l33_i2c_driver = { 1277 .driver = { 1278 .name = "cs35l33", 1279 .pm = &cs35l33_pm_ops, 1280 .of_match_table = cs35l33_of_match, 1281 1282 }, 1283 .id_table = cs35l33_id, 1284 .probe = cs35l33_i2c_probe, 1285 .remove = cs35l33_i2c_remove, 1286 1287}; 1288module_i2c_driver(cs35l33_i2c_driver); 1289 1290MODULE_DESCRIPTION("ASoC CS35L33 driver"); 1291MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>"); 1292MODULE_LICENSE("GPL"); 1293