1// SPDX-License-Identifier: GPL-2.0 2// 3// Driver for Microchip S/PDIF RX Controller 4// 5// Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6// 7// Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9#include <linux/clk.h> 10#include <linux/io.h> 11#include <linux/module.h> 12#include <linux/regmap.h> 13#include <linux/spinlock.h> 14 15#include <sound/dmaengine_pcm.h> 16#include <sound/pcm_params.h> 17#include <sound/soc.h> 18 19/* 20 * ---- S/PDIF Receiver Controller Register map ---- 21 */ 22#define SPDIFRX_CR 0x00 /* Control Register */ 23#define SPDIFRX_MR 0x04 /* Mode Register */ 24 25#define SPDIFRX_IER 0x10 /* Interrupt Enable Register */ 26#define SPDIFRX_IDR 0x14 /* Interrupt Disable Register */ 27#define SPDIFRX_IMR 0x18 /* Interrupt Mask Register */ 28#define SPDIFRX_ISR 0x1c /* Interrupt Status Register */ 29#define SPDIFRX_RSR 0x20 /* Status Register */ 30#define SPDIFRX_RHR 0x24 /* Holding Register */ 31 32#define SPDIFRX_CHSR(channel, reg) \ 33 (0x30 + (channel) * 0x30 + (reg) * 4) /* Channel x Status Registers */ 34 35#define SPDIFRX_CHUD(channel, reg) \ 36 (0x48 + (channel) * 0x30 + (reg) * 4) /* Channel x User Data Registers */ 37 38#define SPDIFRX_WPMR 0xE4 /* Write Protection Mode Register */ 39#define SPDIFRX_WPSR 0xE8 /* Write Protection Status Register */ 40 41#define SPDIFRX_VERSION 0xFC /* Version Register */ 42 43/* 44 * ---- Control Register (Write-only) ---- 45 */ 46#define SPDIFRX_CR_SWRST BIT(0) /* Software Reset */ 47 48/* 49 * ---- Mode Register (Read/Write) ---- 50 */ 51/* Receive Enable */ 52#define SPDIFRX_MR_RXEN_MASK GENMASK(0, 0) 53#define SPDIFRX_MR_RXEN_DISABLE (0 << 0) /* SPDIF Receiver Disabled */ 54#define SPDIFRX_MR_RXEN_ENABLE (1 << 0) /* SPDIF Receiver Enabled */ 55 56/* Validity Bit Mode */ 57#define SPDIFRX_MR_VBMODE_MASK GENAMSK(1, 1) 58#define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \ 59 (0 << 1) /* Load sample regardless of validity bit value */ 60#define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \ 61 (1 << 1) /* Load sample only if validity bit is 0 */ 62 63/* Data Word Endian Mode */ 64#define SPDIFRX_MR_ENDIAN_MASK GENMASK(2, 2) 65#define SPDIFRX_MR_ENDIAN_LITTLE (0 << 2) /* Little Endian Mode */ 66#define SPDIFRX_MR_ENDIAN_BIG (1 << 2) /* Big Endian Mode */ 67 68/* Parity Bit Mode */ 69#define SPDIFRX_MR_PBMODE_MASK GENMASK(3, 3) 70#define SPDIFRX_MR_PBMODE_PARCHECK (0 << 3) /* Parity Check Enabled */ 71#define SPDIFRX_MR_PBMODE_NOPARCHECK (1 << 3) /* Parity Check Disabled */ 72 73/* Sample Data Width */ 74#define SPDIFRX_MR_DATAWIDTH_MASK GENMASK(5, 4) 75#define SPDIFRX_MR_DATAWIDTH(width) \ 76 (((6 - (width) / 4) << 4) & SPDIFRX_MR_DATAWIDTH_MASK) 77 78/* Packed Data Mode in Receive Holding Register */ 79#define SPDIFRX_MR_PACK_MASK GENMASK(7, 7) 80#define SPDIFRX_MR_PACK_DISABLED (0 << 7) 81#define SPDIFRX_MR_PACK_ENABLED (1 << 7) 82 83/* Start of Block Bit Mode */ 84#define SPDIFRX_MR_SBMODE_MASK GENMASK(8, 8) 85#define SPDIFRX_MR_SBMODE_ALWAYS_LOAD (0 << 8) 86#define SPDIFRX_MR_SBMODE_DISCARD (1 << 8) 87 88/* Consecutive Preamble Error Threshold Automatic Restart */ 89#define SPDIFRX_MR_AUTORST_MASK GENMASK(24, 24) 90#define SPDIFRX_MR_AUTORST_NOACTION (0 << 24) 91#define SPDIFRX_MR_AUTORST_UNLOCK_ON_PRE_ERR (1 << 24) 92 93/* 94 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 95 */ 96#define SPDIFRX_IR_RXRDY BIT(0) 97#define SPDIFRX_IR_LOCKED BIT(1) 98#define SPDIFRX_IR_LOSS BIT(2) 99#define SPDIFRX_IR_BLOCKEND BIT(3) 100#define SPDIFRX_IR_SFE BIT(4) 101#define SPDIFRX_IR_PAR_ERR BIT(5) 102#define SPDIFRX_IR_OVERRUN BIT(6) 103#define SPDIFRX_IR_RXFULL BIT(7) 104#define SPDIFRX_IR_CSC(ch) BIT((ch) + 8) 105#define SPDIFRX_IR_SECE BIT(10) 106#define SPDIFRX_IR_BLOCKST BIT(11) 107#define SPDIFRX_IR_NRZ_ERR BIT(12) 108#define SPDIFRX_IR_PRE_ERR BIT(13) 109#define SPDIFRX_IR_CP_ERR BIT(14) 110 111/* 112 * ---- Receiver Status Register (Read/Write) ---- 113 */ 114/* Enable Status */ 115#define SPDIFRX_RSR_ULOCK BIT(0) 116#define SPDIFRX_RSR_BADF BIT(1) 117#define SPDIFRX_RSR_LOWF BIT(2) 118#define SPDIFRX_RSR_NOSIGNAL BIT(3) 119#define SPDIFRX_RSR_IFS_MASK GENMASK(27, 16) 120#define SPDIFRX_RSR_IFS(reg) \ 121 (((reg) & SPDIFRX_RSR_IFS_MASK) >> 16) 122 123/* 124 * ---- Version Register (Read-only) ---- 125 */ 126#define SPDIFRX_VERSION_MASK GENMASK(11, 0) 127#define SPDIFRX_VERSION_MFN_MASK GENMASK(18, 16) 128#define SPDIFRX_VERSION_MFN(reg) (((reg) & SPDIFRX_VERSION_MFN_MASK) >> 16) 129 130static bool mchp_spdifrx_readable_reg(struct device *dev, unsigned int reg) 131{ 132 switch (reg) { 133 case SPDIFRX_MR: 134 case SPDIFRX_IMR: 135 case SPDIFRX_ISR: 136 case SPDIFRX_RSR: 137 case SPDIFRX_CHSR(0, 0): 138 case SPDIFRX_CHSR(0, 1): 139 case SPDIFRX_CHSR(0, 2): 140 case SPDIFRX_CHSR(0, 3): 141 case SPDIFRX_CHSR(0, 4): 142 case SPDIFRX_CHSR(0, 5): 143 case SPDIFRX_CHUD(0, 0): 144 case SPDIFRX_CHUD(0, 1): 145 case SPDIFRX_CHUD(0, 2): 146 case SPDIFRX_CHUD(0, 3): 147 case SPDIFRX_CHUD(0, 4): 148 case SPDIFRX_CHUD(0, 5): 149 case SPDIFRX_CHSR(1, 0): 150 case SPDIFRX_CHSR(1, 1): 151 case SPDIFRX_CHSR(1, 2): 152 case SPDIFRX_CHSR(1, 3): 153 case SPDIFRX_CHSR(1, 4): 154 case SPDIFRX_CHSR(1, 5): 155 case SPDIFRX_CHUD(1, 0): 156 case SPDIFRX_CHUD(1, 1): 157 case SPDIFRX_CHUD(1, 2): 158 case SPDIFRX_CHUD(1, 3): 159 case SPDIFRX_CHUD(1, 4): 160 case SPDIFRX_CHUD(1, 5): 161 case SPDIFRX_WPMR: 162 case SPDIFRX_WPSR: 163 case SPDIFRX_VERSION: 164 return true; 165 default: 166 return false; 167 } 168} 169 170static bool mchp_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 171{ 172 switch (reg) { 173 case SPDIFRX_CR: 174 case SPDIFRX_MR: 175 case SPDIFRX_IER: 176 case SPDIFRX_IDR: 177 case SPDIFRX_WPMR: 178 return true; 179 default: 180 return false; 181 } 182} 183 184static bool mchp_spdifrx_precious_reg(struct device *dev, unsigned int reg) 185{ 186 switch (reg) { 187 case SPDIFRX_ISR: 188 case SPDIFRX_RHR: 189 return true; 190 default: 191 return false; 192 } 193} 194 195static const struct regmap_config mchp_spdifrx_regmap_config = { 196 .reg_bits = 32, 197 .reg_stride = 4, 198 .val_bits = 32, 199 .max_register = SPDIFRX_VERSION, 200 .readable_reg = mchp_spdifrx_readable_reg, 201 .writeable_reg = mchp_spdifrx_writeable_reg, 202 .precious_reg = mchp_spdifrx_precious_reg, 203}; 204 205#define SPDIFRX_GCLK_RATIO_MIN (12 * 64) 206 207#define SPDIFRX_CS_BITS 192 208#define SPDIFRX_UD_BITS 192 209 210#define SPDIFRX_CHANNELS 2 211 212struct mchp_spdifrx_ch_stat { 213 unsigned char data[SPDIFRX_CS_BITS / 8]; 214 struct completion done; 215}; 216 217struct mchp_spdifrx_user_data { 218 unsigned char data[SPDIFRX_UD_BITS / 8]; 219 struct completion done; 220}; 221 222struct mchp_spdifrx_mixer_control { 223 struct mchp_spdifrx_ch_stat ch_stat[SPDIFRX_CHANNELS]; 224 struct mchp_spdifrx_user_data user_data[SPDIFRX_CHANNELS]; 225 bool ulock; 226 bool badf; 227 bool signal; 228}; 229 230struct mchp_spdifrx_dev { 231 struct snd_dmaengine_dai_dma_data capture; 232 struct mchp_spdifrx_mixer_control control; 233 struct mutex mlock; 234 struct device *dev; 235 struct regmap *regmap; 236 struct clk *pclk; 237 struct clk *gclk; 238 unsigned int fmt; 239 unsigned int trigger_enabled; 240 unsigned int gclk_enabled:1; 241}; 242 243static void mchp_spdifrx_channel_status_read(struct mchp_spdifrx_dev *dev, 244 int channel) 245{ 246 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 247 u8 *ch_stat = &ctrl->ch_stat[channel].data[0]; 248 u32 val; 249 int i; 250 251 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat[channel].data) / 4; i++) { 252 regmap_read(dev->regmap, SPDIFRX_CHSR(channel, i), &val); 253 *ch_stat++ = val & 0xFF; 254 *ch_stat++ = (val >> 8) & 0xFF; 255 *ch_stat++ = (val >> 16) & 0xFF; 256 *ch_stat++ = (val >> 24) & 0xFF; 257 } 258} 259 260static void mchp_spdifrx_channel_user_data_read(struct mchp_spdifrx_dev *dev, 261 int channel) 262{ 263 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 264 u8 *user_data = &ctrl->user_data[channel].data[0]; 265 u32 val; 266 int i; 267 268 for (i = 0; i < ARRAY_SIZE(ctrl->user_data[channel].data) / 4; i++) { 269 regmap_read(dev->regmap, SPDIFRX_CHUD(channel, i), &val); 270 *user_data++ = val & 0xFF; 271 *user_data++ = (val >> 8) & 0xFF; 272 *user_data++ = (val >> 16) & 0xFF; 273 *user_data++ = (val >> 24) & 0xFF; 274 } 275} 276 277static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id) 278{ 279 struct mchp_spdifrx_dev *dev = dev_id; 280 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 281 u32 sr, imr, pending; 282 irqreturn_t ret = IRQ_NONE; 283 int ch; 284 285 regmap_read(dev->regmap, SPDIFRX_ISR, &sr); 286 regmap_read(dev->regmap, SPDIFRX_IMR, &imr); 287 pending = sr & imr; 288 dev_dbg(dev->dev, "ISR: %#x, IMR: %#x, pending: %#x\n", sr, imr, 289 pending); 290 291 if (!pending) 292 return IRQ_NONE; 293 294 if (pending & SPDIFRX_IR_BLOCKEND) { 295 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 296 mchp_spdifrx_channel_user_data_read(dev, ch); 297 complete(&ctrl->user_data[ch].done); 298 } 299 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); 300 ret = IRQ_HANDLED; 301 } 302 303 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 304 if (pending & SPDIFRX_IR_CSC(ch)) { 305 mchp_spdifrx_channel_status_read(dev, ch); 306 complete(&ctrl->ch_stat[ch].done); 307 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_CSC(ch)); 308 ret = IRQ_HANDLED; 309 } 310 } 311 312 if (pending & SPDIFRX_IR_OVERRUN) { 313 dev_warn(dev->dev, "Overrun detected\n"); 314 ret = IRQ_HANDLED; 315 } 316 317 return ret; 318} 319 320static int mchp_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 321 struct snd_soc_dai *dai) 322{ 323 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 324 int ret = 0; 325 326 switch (cmd) { 327 case SNDRV_PCM_TRIGGER_START: 328 case SNDRV_PCM_TRIGGER_RESUME: 329 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 330 mutex_lock(&dev->mlock); 331 /* Enable overrun interrupts */ 332 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_OVERRUN); 333 334 /* Enable receiver. */ 335 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 336 SPDIFRX_MR_RXEN_ENABLE); 337 dev->trigger_enabled = true; 338 mutex_unlock(&dev->mlock); 339 break; 340 case SNDRV_PCM_TRIGGER_STOP: 341 case SNDRV_PCM_TRIGGER_SUSPEND: 342 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 343 mutex_lock(&dev->mlock); 344 /* Disable overrun interrupts */ 345 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_OVERRUN); 346 347 /* Disable receiver. */ 348 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 349 SPDIFRX_MR_RXEN_DISABLE); 350 dev->trigger_enabled = false; 351 mutex_unlock(&dev->mlock); 352 break; 353 default: 354 ret = -EINVAL; 355 } 356 357 return ret; 358} 359 360static int mchp_spdifrx_hw_params(struct snd_pcm_substream *substream, 361 struct snd_pcm_hw_params *params, 362 struct snd_soc_dai *dai) 363{ 364 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 365 u32 mr = 0; 366 int ret; 367 368 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 369 __func__, params_rate(params), params_format(params), 370 params_width(params), params_channels(params)); 371 372 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 373 dev_err(dev->dev, "Playback is not supported\n"); 374 return -EINVAL; 375 } 376 377 if (params_channels(params) != SPDIFRX_CHANNELS) { 378 dev_err(dev->dev, "unsupported number of channels: %d\n", 379 params_channels(params)); 380 return -EINVAL; 381 } 382 383 switch (params_format(params)) { 384 case SNDRV_PCM_FORMAT_S16_BE: 385 case SNDRV_PCM_FORMAT_S20_3BE: 386 case SNDRV_PCM_FORMAT_S24_3BE: 387 case SNDRV_PCM_FORMAT_S24_BE: 388 mr |= SPDIFRX_MR_ENDIAN_BIG; 389 fallthrough; 390 case SNDRV_PCM_FORMAT_S16_LE: 391 case SNDRV_PCM_FORMAT_S20_3LE: 392 case SNDRV_PCM_FORMAT_S24_3LE: 393 case SNDRV_PCM_FORMAT_S24_LE: 394 mr |= SPDIFRX_MR_DATAWIDTH(params_width(params)); 395 break; 396 default: 397 dev_err(dev->dev, "unsupported PCM format: %d\n", 398 params_format(params)); 399 return -EINVAL; 400 } 401 402 mutex_lock(&dev->mlock); 403 if (dev->trigger_enabled) { 404 dev_err(dev->dev, "PCM already running\n"); 405 ret = -EBUSY; 406 goto unlock; 407 } 408 409 if (dev->gclk_enabled) { 410 clk_disable_unprepare(dev->gclk); 411 dev->gclk_enabled = 0; 412 } 413 ret = clk_set_min_rate(dev->gclk, params_rate(params) * 414 SPDIFRX_GCLK_RATIO_MIN + 1); 415 if (ret) { 416 dev_err(dev->dev, 417 "unable to set gclk min rate: rate %u * ratio %u + 1\n", 418 params_rate(params), SPDIFRX_GCLK_RATIO_MIN); 419 goto unlock; 420 } 421 ret = clk_prepare_enable(dev->gclk); 422 if (ret) { 423 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 424 goto unlock; 425 } 426 dev->gclk_enabled = 1; 427 428 dev_dbg(dev->dev, "GCLK range min set to %d\n", 429 params_rate(params) * SPDIFRX_GCLK_RATIO_MIN + 1); 430 431 ret = regmap_write(dev->regmap, SPDIFRX_MR, mr); 432 433unlock: 434 mutex_unlock(&dev->mlock); 435 436 return ret; 437} 438 439static int mchp_spdifrx_hw_free(struct snd_pcm_substream *substream, 440 struct snd_soc_dai *dai) 441{ 442 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 443 444 mutex_lock(&dev->mlock); 445 if (dev->gclk_enabled) { 446 clk_disable_unprepare(dev->gclk); 447 dev->gclk_enabled = 0; 448 } 449 mutex_unlock(&dev->mlock); 450 return 0; 451} 452 453static const struct snd_soc_dai_ops mchp_spdifrx_dai_ops = { 454 .trigger = mchp_spdifrx_trigger, 455 .hw_params = mchp_spdifrx_hw_params, 456 .hw_free = mchp_spdifrx_hw_free, 457}; 458 459#define MCHP_SPDIF_RATES SNDRV_PCM_RATE_8000_192000 460 461#define MCHP_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 462 SNDRV_PCM_FMTBIT_U16_BE | \ 463 SNDRV_PCM_FMTBIT_S20_3LE | \ 464 SNDRV_PCM_FMTBIT_S20_3BE | \ 465 SNDRV_PCM_FMTBIT_S24_3LE | \ 466 SNDRV_PCM_FMTBIT_S24_3BE | \ 467 SNDRV_PCM_FMTBIT_S24_LE | \ 468 SNDRV_PCM_FMTBIT_S24_BE \ 469 ) 470 471static int mchp_spdifrx_info(struct snd_kcontrol *kcontrol, 472 struct snd_ctl_elem_info *uinfo) 473{ 474 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 475 uinfo->count = 1; 476 477 return 0; 478} 479 480static int mchp_spdifrx_cs_get(struct mchp_spdifrx_dev *dev, 481 int channel, 482 struct snd_ctl_elem_value *uvalue) 483{ 484 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 485 struct mchp_spdifrx_ch_stat *ch_stat = &ctrl->ch_stat[channel]; 486 int ret = 0; 487 488 mutex_lock(&dev->mlock); 489 490 /* 491 * We may reach this point with both clocks enabled but the receiver 492 * still disabled. To void waiting for completion and return with 493 * timeout check the dev->trigger_enabled. 494 * 495 * To retrieve data: 496 * - if the receiver is enabled CSC IRQ will update the data in software 497 * caches (ch_stat->data) 498 * - otherwise we just update it here the software caches with latest 499 * available information and return it; in this case we don't need 500 * spin locking as the IRQ is disabled and will not be raised from 501 * anywhere else. 502 */ 503 504 if (dev->trigger_enabled) { 505 reinit_completion(&ch_stat->done); 506 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_CSC(channel)); 507 /* Check for new data available */ 508 ret = wait_for_completion_interruptible_timeout(&ch_stat->done, 509 msecs_to_jiffies(100)); 510 /* Valid stream might not be present */ 511 if (ret <= 0) { 512 dev_dbg(dev->dev, "channel status for channel %d timeout\n", 513 channel); 514 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_CSC(channel)); 515 ret = ret ? : -ETIMEDOUT; 516 goto unlock; 517 } else { 518 ret = 0; 519 } 520 } else { 521 /* Update software cache with latest channel status. */ 522 mchp_spdifrx_channel_status_read(dev, channel); 523 } 524 525 memcpy(uvalue->value.iec958.status, ch_stat->data, 526 sizeof(ch_stat->data)); 527 528unlock: 529 mutex_unlock(&dev->mlock); 530 return ret; 531} 532 533static int mchp_spdifrx_cs1_get(struct snd_kcontrol *kcontrol, 534 struct snd_ctl_elem_value *uvalue) 535{ 536 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 537 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 538 539 return mchp_spdifrx_cs_get(dev, 0, uvalue); 540} 541 542static int mchp_spdifrx_cs2_get(struct snd_kcontrol *kcontrol, 543 struct snd_ctl_elem_value *uvalue) 544{ 545 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 546 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 547 548 return mchp_spdifrx_cs_get(dev, 1, uvalue); 549} 550 551static int mchp_spdifrx_cs_mask(struct snd_kcontrol *kcontrol, 552 struct snd_ctl_elem_value *uvalue) 553{ 554 memset(uvalue->value.iec958.status, 0xff, 555 sizeof(uvalue->value.iec958.status)); 556 557 return 0; 558} 559 560static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev, 561 int channel, 562 struct snd_ctl_elem_value *uvalue) 563{ 564 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 565 struct mchp_spdifrx_user_data *user_data = &ctrl->user_data[channel]; 566 int ret = 0; 567 568 mutex_lock(&dev->mlock); 569 570 /* 571 * We may reach this point with both clocks enabled but the receiver 572 * still disabled. To void waiting for completion to just timeout we 573 * check here the dev->trigger_enabled flag. 574 * 575 * To retrieve data: 576 * - if the receiver is enabled we need to wait for blockend IRQ to read 577 * data to and update it for us in software caches 578 * - otherwise reading the SPDIFRX_CHUD() registers is enough. 579 */ 580 581 if (dev->trigger_enabled) { 582 reinit_completion(&user_data->done); 583 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_BLOCKEND); 584 ret = wait_for_completion_interruptible_timeout(&user_data->done, 585 msecs_to_jiffies(100)); 586 /* Valid stream might not be present. */ 587 if (ret <= 0) { 588 dev_dbg(dev->dev, "user data for channel %d timeout\n", 589 channel); 590 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); 591 ret = ret ? : -ETIMEDOUT; 592 goto unlock; 593 } else { 594 ret = 0; 595 } 596 } else { 597 /* Update software cache with last available data. */ 598 mchp_spdifrx_channel_user_data_read(dev, channel); 599 } 600 601 memcpy(uvalue->value.iec958.subcode, user_data->data, 602 sizeof(user_data->data)); 603 604unlock: 605 mutex_unlock(&dev->mlock); 606 return ret; 607} 608 609static int mchp_spdifrx_subcode_ch1_get(struct snd_kcontrol *kcontrol, 610 struct snd_ctl_elem_value *uvalue) 611{ 612 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 613 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 614 615 return mchp_spdifrx_subcode_ch_get(dev, 0, uvalue); 616} 617 618static int mchp_spdifrx_subcode_ch2_get(struct snd_kcontrol *kcontrol, 619 struct snd_ctl_elem_value *uvalue) 620{ 621 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 622 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 623 624 return mchp_spdifrx_subcode_ch_get(dev, 1, uvalue); 625} 626 627static int mchp_spdifrx_boolean_info(struct snd_kcontrol *kcontrol, 628 struct snd_ctl_elem_info *uinfo) 629{ 630 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 631 uinfo->count = 1; 632 uinfo->value.integer.min = 0; 633 uinfo->value.integer.max = 1; 634 635 return 0; 636} 637 638static int mchp_spdifrx_ulock_get(struct snd_kcontrol *kcontrol, 639 struct snd_ctl_elem_value *uvalue) 640{ 641 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 642 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 643 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 644 u32 val; 645 bool ulock_old = ctrl->ulock; 646 647 mutex_lock(&dev->mlock); 648 649 /* 650 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 651 * and the receiver is disabled. Thus we take into account the 652 * dev->trigger_enabled here to return a real status. 653 */ 654 if (dev->trigger_enabled) { 655 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 656 ctrl->ulock = !(val & SPDIFRX_RSR_ULOCK); 657 } else { 658 ctrl->ulock = 0; 659 } 660 661 uvalue->value.integer.value[0] = ctrl->ulock; 662 663 mutex_unlock(&dev->mlock); 664 665 return ulock_old != ctrl->ulock; 666} 667 668static int mchp_spdifrx_badf_get(struct snd_kcontrol *kcontrol, 669 struct snd_ctl_elem_value *uvalue) 670{ 671 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 672 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 673 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 674 u32 val; 675 bool badf_old = ctrl->badf; 676 677 mutex_lock(&dev->mlock); 678 679 /* 680 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 681 * and the receiver is disabled. Thus we take into account the 682 * dev->trigger_enabled here to return a real status. 683 */ 684 if (dev->trigger_enabled) { 685 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 686 ctrl->badf = !!(val & SPDIFRX_RSR_BADF); 687 } else { 688 ctrl->badf = 0; 689 } 690 691 mutex_unlock(&dev->mlock); 692 693 uvalue->value.integer.value[0] = ctrl->badf; 694 695 return badf_old != ctrl->badf; 696} 697 698static int mchp_spdifrx_signal_get(struct snd_kcontrol *kcontrol, 699 struct snd_ctl_elem_value *uvalue) 700{ 701 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 702 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 703 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 704 u32 val = ~0U, loops = 10; 705 int ret; 706 bool signal_old = ctrl->signal; 707 708 mutex_lock(&dev->mlock); 709 710 /* 711 * To get the signal we need to have receiver enabled. This 712 * could be enabled also from trigger() function thus we need to 713 * take care of not disabling the receiver when it runs. 714 */ 715 if (!dev->trigger_enabled) { 716 ret = clk_prepare_enable(dev->gclk); 717 if (ret) 718 goto unlock; 719 720 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 721 SPDIFRX_MR_RXEN_ENABLE); 722 723 /* Wait for RSR.ULOCK bit. */ 724 while (--loops) { 725 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 726 if (!(val & SPDIFRX_RSR_ULOCK)) 727 break; 728 usleep_range(100, 150); 729 } 730 731 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 732 SPDIFRX_MR_RXEN_DISABLE); 733 734 clk_disable_unprepare(dev->gclk); 735 } else { 736 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 737 } 738 739unlock: 740 mutex_unlock(&dev->mlock); 741 742 if (!(val & SPDIFRX_RSR_ULOCK)) 743 ctrl->signal = !(val & SPDIFRX_RSR_NOSIGNAL); 744 else 745 ctrl->signal = 0; 746 uvalue->value.integer.value[0] = ctrl->signal; 747 748 return signal_old != ctrl->signal; 749} 750 751static int mchp_spdifrx_rate_info(struct snd_kcontrol *kcontrol, 752 struct snd_ctl_elem_info *uinfo) 753{ 754 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 755 uinfo->count = 1; 756 uinfo->value.integer.min = 0; 757 uinfo->value.integer.max = 192000; 758 759 return 0; 760} 761 762static int mchp_spdifrx_rate_get(struct snd_kcontrol *kcontrol, 763 struct snd_ctl_elem_value *ucontrol) 764{ 765 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 766 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 767 u32 val; 768 int rate; 769 770 mutex_lock(&dev->mlock); 771 772 /* 773 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 774 * and the receiver is disabled. Thus we take into account the 775 * dev->trigger_enabled here to return a real status. 776 */ 777 if (dev->trigger_enabled) { 778 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 779 /* If the receiver is not locked, ISF data is invalid. */ 780 if (val & SPDIFRX_RSR_ULOCK || !(val & SPDIFRX_RSR_IFS_MASK)) { 781 ucontrol->value.integer.value[0] = 0; 782 goto unlock; 783 } 784 } else { 785 /* Reveicer is not locked, IFS data is invalid. */ 786 ucontrol->value.integer.value[0] = 0; 787 goto unlock; 788 } 789 790 rate = clk_get_rate(dev->gclk); 791 792 ucontrol->value.integer.value[0] = rate / (32 * SPDIFRX_RSR_IFS(val)); 793 794unlock: 795 mutex_unlock(&dev->mlock); 796 return 0; 797} 798 799static struct snd_kcontrol_new mchp_spdifrx_ctrls[] = { 800 /* Channel status controller */ 801 { 802 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 803 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT) 804 " Channel 1", 805 .access = SNDRV_CTL_ELEM_ACCESS_READ | 806 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 807 .info = mchp_spdifrx_info, 808 .get = mchp_spdifrx_cs1_get, 809 }, 810 { 811 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 812 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT) 813 " Channel 2", 814 .access = SNDRV_CTL_ELEM_ACCESS_READ | 815 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 816 .info = mchp_spdifrx_info, 817 .get = mchp_spdifrx_cs2_get, 818 }, 819 { 820 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 821 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), 822 .access = SNDRV_CTL_ELEM_ACCESS_READ, 823 .info = mchp_spdifrx_info, 824 .get = mchp_spdifrx_cs_mask, 825 }, 826 /* User bits controller */ 827 { 828 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 829 .name = "IEC958 Subcode Capture Default Channel 1", 830 .access = SNDRV_CTL_ELEM_ACCESS_READ | 831 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 832 .info = mchp_spdifrx_info, 833 .get = mchp_spdifrx_subcode_ch1_get, 834 }, 835 { 836 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 837 .name = "IEC958 Subcode Capture Default Channel 2", 838 .access = SNDRV_CTL_ELEM_ACCESS_READ | 839 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 840 .info = mchp_spdifrx_info, 841 .get = mchp_spdifrx_subcode_ch2_get, 842 }, 843 /* Lock status */ 844 { 845 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 846 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Unlocked", 847 .access = SNDRV_CTL_ELEM_ACCESS_READ | 848 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 849 .info = mchp_spdifrx_boolean_info, 850 .get = mchp_spdifrx_ulock_get, 851 }, 852 /* Bad format */ 853 { 854 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 855 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE)"Bad Format", 856 .access = SNDRV_CTL_ELEM_ACCESS_READ | 857 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 858 .info = mchp_spdifrx_boolean_info, 859 .get = mchp_spdifrx_badf_get, 860 }, 861 /* Signal */ 862 { 863 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 864 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Signal", 865 .access = SNDRV_CTL_ELEM_ACCESS_READ | 866 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 867 .info = mchp_spdifrx_boolean_info, 868 .get = mchp_spdifrx_signal_get, 869 }, 870 /* Sampling rate */ 871 { 872 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 873 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Rate", 874 .access = SNDRV_CTL_ELEM_ACCESS_READ | 875 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 876 .info = mchp_spdifrx_rate_info, 877 .get = mchp_spdifrx_rate_get, 878 }, 879}; 880 881static int mchp_spdifrx_dai_probe(struct snd_soc_dai *dai) 882{ 883 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 884 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 885 int ch; 886 int err; 887 888 err = clk_prepare_enable(dev->pclk); 889 if (err) { 890 dev_err(dev->dev, 891 "failed to enable the peripheral clock: %d\n", err); 892 return err; 893 } 894 895 snd_soc_dai_init_dma_data(dai, NULL, &dev->capture); 896 897 /* Software reset the IP */ 898 regmap_write(dev->regmap, SPDIFRX_CR, SPDIFRX_CR_SWRST); 899 900 /* Default configuration */ 901 regmap_write(dev->regmap, SPDIFRX_MR, 902 SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 | 903 SPDIFRX_MR_SBMODE_DISCARD | 904 SPDIFRX_MR_AUTORST_NOACTION | 905 SPDIFRX_MR_PACK_DISABLED); 906 907 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 908 init_completion(&ctrl->ch_stat[ch].done); 909 init_completion(&ctrl->user_data[ch].done); 910 } 911 912 /* Add controls */ 913 snd_soc_add_dai_controls(dai, mchp_spdifrx_ctrls, 914 ARRAY_SIZE(mchp_spdifrx_ctrls)); 915 916 return 0; 917} 918 919static int mchp_spdifrx_dai_remove(struct snd_soc_dai *dai) 920{ 921 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 922 923 /* Disable interrupts */ 924 regmap_write(dev->regmap, SPDIFRX_IDR, GENMASK(14, 0)); 925 926 clk_disable_unprepare(dev->pclk); 927 928 return 0; 929} 930 931static struct snd_soc_dai_driver mchp_spdifrx_dai = { 932 .name = "mchp-spdifrx", 933 .probe = mchp_spdifrx_dai_probe, 934 .remove = mchp_spdifrx_dai_remove, 935 .capture = { 936 .stream_name = "S/PDIF Capture", 937 .channels_min = SPDIFRX_CHANNELS, 938 .channels_max = SPDIFRX_CHANNELS, 939 .rates = MCHP_SPDIF_RATES, 940 .formats = MCHP_SPDIF_FORMATS, 941 }, 942 .ops = &mchp_spdifrx_dai_ops, 943}; 944 945static const struct snd_soc_component_driver mchp_spdifrx_component = { 946 .name = "mchp-spdifrx", 947}; 948 949static const struct of_device_id mchp_spdifrx_dt_ids[] = { 950 { 951 .compatible = "microchip,sama7g5-spdifrx", 952 }, 953 { /* sentinel */ } 954}; 955MODULE_DEVICE_TABLE(of, mchp_spdifrx_dt_ids); 956 957static int mchp_spdifrx_probe(struct platform_device *pdev) 958{ 959 struct mchp_spdifrx_dev *dev; 960 struct resource *mem; 961 struct regmap *regmap; 962 void __iomem *base; 963 int irq; 964 int err; 965 u32 vers; 966 967 /* Get memory for driver data. */ 968 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 969 if (!dev) 970 return -ENOMEM; 971 972 /* Map I/O registers. */ 973 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 974 if (IS_ERR(base)) 975 return PTR_ERR(base); 976 977 regmap = devm_regmap_init_mmio(&pdev->dev, base, 978 &mchp_spdifrx_regmap_config); 979 if (IS_ERR(regmap)) 980 return PTR_ERR(regmap); 981 982 /* Request IRQ. */ 983 irq = platform_get_irq(pdev, 0); 984 if (irq < 0) 985 return irq; 986 987 err = devm_request_irq(&pdev->dev, irq, mchp_spdif_interrupt, 0, 988 dev_name(&pdev->dev), dev); 989 if (err) 990 return err; 991 992 /* Get the peripheral clock */ 993 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 994 if (IS_ERR(dev->pclk)) { 995 err = PTR_ERR(dev->pclk); 996 dev_err(&pdev->dev, "failed to get the peripheral clock: %d\n", 997 err); 998 return err; 999 } 1000 1001 /* Get the generated clock */ 1002 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 1003 if (IS_ERR(dev->gclk)) { 1004 err = PTR_ERR(dev->gclk); 1005 dev_err(&pdev->dev, 1006 "failed to get the PMC generated clock: %d\n", err); 1007 return err; 1008 } 1009 1010 /* 1011 * Signal control need a valid rate on gclk. hw_params() configures 1012 * it propertly but requesting signal before any hw_params() has been 1013 * called lead to invalid value returned for signal. Thus, configure 1014 * gclk at a valid rate, here, in initialization, to simplify the 1015 * control path. 1016 */ 1017 clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1); 1018 1019 mutex_init(&dev->mlock); 1020 1021 dev->dev = &pdev->dev; 1022 dev->regmap = regmap; 1023 platform_set_drvdata(pdev, dev); 1024 1025 dev->capture.addr = (dma_addr_t)mem->start + SPDIFRX_RHR; 1026 dev->capture.maxburst = 1; 1027 1028 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1029 if (err) { 1030 dev_err(&pdev->dev, "failed to register PMC: %d\n", err); 1031 return err; 1032 } 1033 1034 err = devm_snd_soc_register_component(&pdev->dev, 1035 &mchp_spdifrx_component, 1036 &mchp_spdifrx_dai, 1); 1037 if (err) { 1038 dev_err(&pdev->dev, "fail to register dai\n"); 1039 return err; 1040 } 1041 1042 regmap_read(regmap, SPDIFRX_VERSION, &vers); 1043 dev_info(&pdev->dev, "hw version: %#lx\n", vers & SPDIFRX_VERSION_MASK); 1044 1045 return 0; 1046} 1047 1048static struct platform_driver mchp_spdifrx_driver = { 1049 .probe = mchp_spdifrx_probe, 1050 .driver = { 1051 .name = "mchp_spdifrx", 1052 .of_match_table = of_match_ptr(mchp_spdifrx_dt_ids), 1053 }, 1054}; 1055 1056module_platform_driver(mchp_spdifrx_driver); 1057 1058MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 1059MODULE_DESCRIPTION("Microchip S/PDIF RX Controller Driver"); 1060MODULE_LICENSE("GPL v2"); 1061