1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * AMD ALSA SoC PCM Driver for ACP 2.x 4 * 5 * Copyright 2014-2015 Advanced Micro Devices, Inc. 6 */ 7 8#include <linux/module.h> 9#include <linux/delay.h> 10#include <linux/io.h> 11#include <linux/iopoll.h> 12#include <linux/sizes.h> 13#include <linux/pm_runtime.h> 14 15#include <sound/soc.h> 16#include <drm/amd_asic_type.h> 17#include "acp.h" 18 19#define DRV_NAME "acp_audio_dma" 20 21#define PLAYBACK_MIN_NUM_PERIODS 2 22#define PLAYBACK_MAX_NUM_PERIODS 2 23#define PLAYBACK_MAX_PERIOD_SIZE 16384 24#define PLAYBACK_MIN_PERIOD_SIZE 1024 25#define CAPTURE_MIN_NUM_PERIODS 2 26#define CAPTURE_MAX_NUM_PERIODS 2 27#define CAPTURE_MAX_PERIOD_SIZE 16384 28#define CAPTURE_MIN_PERIOD_SIZE 1024 29 30#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 31#define MIN_BUFFER MAX_BUFFER 32 33#define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 34#define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 35#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 36#define ST_MIN_BUFFER ST_MAX_BUFFER 37 38#define DRV_NAME "acp_audio_dma" 39bool bt_uart_enable = true; 40EXPORT_SYMBOL(bt_uart_enable); 41 42static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 43 .info = SNDRV_PCM_INFO_INTERLEAVED | 44 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 45 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 46 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 47 .formats = SNDRV_PCM_FMTBIT_S16_LE | 48 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 49 .channels_min = 1, 50 .channels_max = 8, 51 .rates = SNDRV_PCM_RATE_8000_96000, 52 .rate_min = 8000, 53 .rate_max = 96000, 54 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 55 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 56 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 57 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 58 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 59}; 60 61static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 62 .info = SNDRV_PCM_INFO_INTERLEAVED | 63 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 64 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 65 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 66 .formats = SNDRV_PCM_FMTBIT_S16_LE | 67 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 68 .channels_min = 1, 69 .channels_max = 2, 70 .rates = SNDRV_PCM_RATE_8000_48000, 71 .rate_min = 8000, 72 .rate_max = 48000, 73 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 74 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 75 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 76 .periods_min = CAPTURE_MIN_NUM_PERIODS, 77 .periods_max = CAPTURE_MAX_NUM_PERIODS, 78}; 79 80static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 81 .info = SNDRV_PCM_INFO_INTERLEAVED | 82 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 83 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 84 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 85 .formats = SNDRV_PCM_FMTBIT_S16_LE | 86 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 87 .channels_min = 1, 88 .channels_max = 8, 89 .rates = SNDRV_PCM_RATE_8000_96000, 90 .rate_min = 8000, 91 .rate_max = 96000, 92 .buffer_bytes_max = ST_MAX_BUFFER, 93 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 94 .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 95 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 96 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 97}; 98 99static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 100 .info = SNDRV_PCM_INFO_INTERLEAVED | 101 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 102 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 103 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 104 .formats = SNDRV_PCM_FMTBIT_S16_LE | 105 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 106 .channels_min = 1, 107 .channels_max = 2, 108 .rates = SNDRV_PCM_RATE_8000_48000, 109 .rate_min = 8000, 110 .rate_max = 48000, 111 .buffer_bytes_max = ST_MAX_BUFFER, 112 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 113 .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 114 .periods_min = CAPTURE_MIN_NUM_PERIODS, 115 .periods_max = CAPTURE_MAX_NUM_PERIODS, 116}; 117 118static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 119{ 120 return readl(acp_mmio + (reg * 4)); 121} 122 123static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 124{ 125 writel(val, acp_mmio + (reg * 4)); 126} 127 128/* 129 * Configure a given dma channel parameters - enable/disable, 130 * number of descriptors, priority 131 */ 132static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 133 u16 dscr_strt_idx, u16 num_dscrs, 134 enum acp_dma_priority_level priority_level) 135{ 136 u32 dma_ctrl; 137 138 /* disable the channel run field */ 139 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 140 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 141 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 142 143 /* program a DMA channel with first descriptor to be processed. */ 144 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 145 & dscr_strt_idx), 146 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 147 148 /* 149 * program a DMA channel with the number of descriptors to be 150 * processed in the transfer 151 */ 152 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 153 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 154 155 /* set DMA channel priority */ 156 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 157} 158 159/* Initialize a dma descriptor in SRAM based on descritor information passed */ 160static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 161 u16 descr_idx, 162 acp_dma_dscr_transfer_t *descr_info) 163{ 164 u32 sram_offset; 165 166 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 167 168 /* program the source base address. */ 169 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 170 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 171 /* program the destination base address. */ 172 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 173 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 174 175 /* program the number of bytes to be transferred for this descriptor. */ 176 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 177 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 178} 179 180static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num) 181{ 182 u32 dma_ctrl; 183 int ret; 184 185 /* clear the reset bit */ 186 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 187 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 188 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 189 /* check the reset bit before programming configuration registers */ 190 ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4), 191 dma_ctrl, 192 !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK), 193 100, ACP_DMA_RESET_TIME); 194 if (ret < 0) 195 pr_err("Failed to clear reset of channel : %d\n", ch_num); 196} 197 198/* 199 * Initialize the DMA descriptor information for transfer between 200 * system memory <-> ACP SRAM 201 */ 202static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 203 u32 size, int direction, 204 u32 pte_offset, u16 ch, 205 u32 sram_bank, u16 dma_dscr_idx, 206 u32 asic_type) 207{ 208 u16 i; 209 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 210 211 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 212 dmadscr[i].xfer_val = 0; 213 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 214 dma_dscr_idx = dma_dscr_idx + i; 215 dmadscr[i].dest = sram_bank + (i * (size / 2)); 216 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 217 + (pte_offset * SZ_4K) + (i * (size / 2)); 218 switch (asic_type) { 219 case CHIP_STONEY: 220 dmadscr[i].xfer_val |= 221 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | 222 (size / 2); 223 break; 224 default: 225 dmadscr[i].xfer_val |= 226 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | 227 (size / 2); 228 } 229 } else { 230 dma_dscr_idx = dma_dscr_idx + i; 231 dmadscr[i].src = sram_bank + (i * (size / 2)); 232 dmadscr[i].dest = 233 ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 234 (pte_offset * SZ_4K) + (i * (size / 2)); 235 switch (asic_type) { 236 case CHIP_STONEY: 237 dmadscr[i].xfer_val |= 238 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | 239 (size / 2); 240 break; 241 default: 242 dmadscr[i].xfer_val |= 243 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | 244 (size / 2); 245 } 246 } 247 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 248 &dmadscr[i]); 249 } 250 pre_config_reset(acp_mmio, ch); 251 config_acp_dma_channel(acp_mmio, ch, 252 dma_dscr_idx - 1, 253 NUM_DSCRS_PER_CHANNEL, 254 ACP_DMA_PRIORITY_LEVEL_NORMAL); 255} 256 257/* 258 * Initialize the DMA descriptor information for transfer between 259 * ACP SRAM <-> I2S 260 */ 261static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 262 int direction, u32 sram_bank, 263 u16 destination, u16 ch, 264 u16 dma_dscr_idx, u32 asic_type) 265{ 266 u16 i; 267 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 268 269 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 270 dmadscr[i].xfer_val = 0; 271 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 272 dma_dscr_idx = dma_dscr_idx + i; 273 dmadscr[i].src = sram_bank + (i * (size / 2)); 274 /* dmadscr[i].dest is unused by hardware. */ 275 dmadscr[i].dest = 0; 276 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 277 (size / 2); 278 } else { 279 dma_dscr_idx = dma_dscr_idx + i; 280 /* dmadscr[i].src is unused by hardware. */ 281 dmadscr[i].src = 0; 282 dmadscr[i].dest = 283 sram_bank + (i * (size / 2)); 284 dmadscr[i].xfer_val |= BIT(22) | 285 (destination << 16) | (size / 2); 286 } 287 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 288 &dmadscr[i]); 289 } 290 pre_config_reset(acp_mmio, ch); 291 /* Configure the DMA channel with the above descriptore */ 292 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 293 NUM_DSCRS_PER_CHANNEL, 294 ACP_DMA_PRIORITY_LEVEL_NORMAL); 295} 296 297/* Create page table entries in ACP SRAM for the allocated memory */ 298static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr, 299 u16 num_of_pages, u32 pte_offset) 300{ 301 u16 page_idx; 302 u32 low; 303 u32 high; 304 u32 offset; 305 306 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 307 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 308 /* Load the low address of page int ACP SRAM through SRBM */ 309 acp_reg_write((offset + (page_idx * 8)), 310 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 311 312 low = lower_32_bits(addr); 313 high = upper_32_bits(addr); 314 315 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 316 317 /* Load the High address of page int ACP SRAM through SRBM */ 318 acp_reg_write((offset + (page_idx * 8) + 4), 319 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 320 321 /* page enable in ACP */ 322 high |= BIT(31); 323 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 324 325 /* Move to next physically contiguos page */ 326 addr += PAGE_SIZE; 327 } 328} 329 330static void config_acp_dma(void __iomem *acp_mmio, 331 struct audio_substream_data *rtd, 332 u32 asic_type) 333{ 334 u16 ch_acp_sysmem, ch_acp_i2s; 335 336 acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages, 337 rtd->pte_offset); 338 339 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 340 ch_acp_sysmem = rtd->ch1; 341 ch_acp_i2s = rtd->ch2; 342 } else { 343 ch_acp_i2s = rtd->ch1; 344 ch_acp_sysmem = rtd->ch2; 345 } 346 /* Configure System memory <-> ACP SRAM DMA descriptors */ 347 set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, 348 rtd->direction, rtd->pte_offset, 349 ch_acp_sysmem, rtd->sram_bank, 350 rtd->dma_dscr_idx_1, asic_type); 351 /* Configure ACP SRAM <-> I2S DMA descriptors */ 352 set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, 353 rtd->direction, rtd->sram_bank, 354 rtd->destination, ch_acp_i2s, 355 rtd->dma_dscr_idx_2, asic_type); 356} 357 358static void acp_dma_cap_channel_enable(void __iomem *acp_mmio, 359 u16 cap_channel) 360{ 361 u32 val, ch_reg, imr_reg, res_reg; 362 363 switch (cap_channel) { 364 case CAP_CHANNEL1: 365 ch_reg = mmACP_I2SMICSP_RER1; 366 res_reg = mmACP_I2SMICSP_RCR1; 367 imr_reg = mmACP_I2SMICSP_IMR1; 368 break; 369 case CAP_CHANNEL0: 370 default: 371 ch_reg = mmACP_I2SMICSP_RER0; 372 res_reg = mmACP_I2SMICSP_RCR0; 373 imr_reg = mmACP_I2SMICSP_IMR0; 374 break; 375 } 376 val = acp_reg_read(acp_mmio, 377 mmACP_I2S_16BIT_RESOLUTION_EN); 378 if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { 379 acp_reg_write(0x0, acp_mmio, ch_reg); 380 /* Set 16bit resolution on capture */ 381 acp_reg_write(0x2, acp_mmio, res_reg); 382 } 383 val = acp_reg_read(acp_mmio, imr_reg); 384 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 385 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 386 acp_reg_write(val, acp_mmio, imr_reg); 387 acp_reg_write(0x1, acp_mmio, ch_reg); 388} 389 390static void acp_dma_cap_channel_disable(void __iomem *acp_mmio, 391 u16 cap_channel) 392{ 393 u32 val, ch_reg, imr_reg; 394 395 switch (cap_channel) { 396 case CAP_CHANNEL1: 397 imr_reg = mmACP_I2SMICSP_IMR1; 398 ch_reg = mmACP_I2SMICSP_RER1; 399 break; 400 case CAP_CHANNEL0: 401 default: 402 imr_reg = mmACP_I2SMICSP_IMR0; 403 ch_reg = mmACP_I2SMICSP_RER0; 404 break; 405 } 406 val = acp_reg_read(acp_mmio, imr_reg); 407 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 408 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 409 acp_reg_write(val, acp_mmio, imr_reg); 410 acp_reg_write(0x0, acp_mmio, ch_reg); 411} 412 413/* Start a given DMA channel transfer */ 414static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular) 415{ 416 u32 dma_ctrl; 417 418 /* read the dma control register and disable the channel run field */ 419 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 420 421 /* Invalidating the DAGB cache */ 422 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 423 424 /* 425 * configure the DMA channel and start the DMA transfer 426 * set dmachrun bit to start the transfer and enable the 427 * interrupt on completion of the dma transfer 428 */ 429 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 430 431 switch (ch_num) { 432 case ACP_TO_I2S_DMA_CH_NUM: 433 case I2S_TO_ACP_DMA_CH_NUM: 434 case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: 435 case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: 436 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 437 break; 438 default: 439 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 440 break; 441 } 442 443 /* enable for ACP to SRAM DMA channel */ 444 if (is_circular == true) 445 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 446 else 447 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 448 449 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 450} 451 452/* Stop a given DMA channel transfer */ 453static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 454{ 455 u32 dma_ctrl; 456 u32 dma_ch_sts; 457 u32 count = ACP_DMA_RESET_TIME; 458 459 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 460 461 /* 462 * clear the dma control register fields before writing zero 463 * in reset bit 464 */ 465 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 466 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 467 468 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 469 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 470 471 if (dma_ch_sts & BIT(ch_num)) { 472 /* 473 * set the reset bit for this channel to stop the dma 474 * transfer 475 */ 476 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 477 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 478 } 479 480 /* check the channel status bit for some time and return the status */ 481 while (true) { 482 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 483 if (!(dma_ch_sts & BIT(ch_num))) { 484 /* 485 * clear the reset flag after successfully stopping 486 * the dma transfer and break from the loop 487 */ 488 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 489 490 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 491 + ch_num); 492 break; 493 } 494 if (--count == 0) { 495 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 496 return -ETIMEDOUT; 497 } 498 udelay(100); 499 } 500 return 0; 501} 502 503static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 504 bool power_on) 505{ 506 u32 val, req_reg, sts_reg, sts_reg_mask; 507 u32 loops = 1000; 508 509 if (bank < 32) { 510 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 511 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 512 sts_reg_mask = 0xFFFFFFFF; 513 514 } else { 515 bank -= 32; 516 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 517 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 518 sts_reg_mask = 0x0000FFFF; 519 } 520 521 val = acp_reg_read(acp_mmio, req_reg); 522 if (val & (1 << bank)) { 523 /* bank is in off state */ 524 if (power_on == true) 525 /* request to on */ 526 val &= ~(1 << bank); 527 else 528 /* request to off */ 529 return; 530 } else { 531 /* bank is in on state */ 532 if (power_on == false) 533 /* request to off */ 534 val |= 1 << bank; 535 else 536 /* request to on */ 537 return; 538 } 539 acp_reg_write(val, acp_mmio, req_reg); 540 541 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 542 if (!loops--) { 543 pr_err("ACP SRAM bank %d state change failed\n", bank); 544 break; 545 } 546 cpu_relax(); 547 } 548} 549 550/* Initialize and bring ACP hardware to default state. */ 551static int acp_init(void __iomem *acp_mmio, u32 asic_type) 552{ 553 u16 bank; 554 u32 val, count, sram_pte_offset; 555 556 /* Assert Soft reset of ACP */ 557 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 558 559 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 560 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 561 562 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 563 while (true) { 564 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 565 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 566 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 567 break; 568 if (--count == 0) { 569 pr_err("Failed to reset ACP\n"); 570 return -ETIMEDOUT; 571 } 572 udelay(100); 573 } 574 575 /* Enable clock to ACP and wait until the clock is enabled */ 576 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 577 val = val | ACP_CONTROL__ClkEn_MASK; 578 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 579 580 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 581 582 while (true) { 583 val = acp_reg_read(acp_mmio, mmACP_STATUS); 584 if (val & (u32)0x1) 585 break; 586 if (--count == 0) { 587 pr_err("Failed to reset ACP\n"); 588 return -ETIMEDOUT; 589 } 590 udelay(100); 591 } 592 593 /* Deassert the SOFT RESET flags */ 594 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 595 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 596 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 597 598 /* For BT instance change pins from UART to BT */ 599 if (!bt_uart_enable) { 600 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); 601 val |= ACP_BT_UART_PAD_SELECT_MASK; 602 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); 603 } 604 605 /* initiailize Onion control DAGB register */ 606 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 607 mmACP_AXI2DAGB_ONION_CNTL); 608 609 /* initiailize Garlic control DAGB registers */ 610 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 611 mmACP_AXI2DAGB_GARLIC_CNTL); 612 613 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 614 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 615 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 616 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 617 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 618 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 619 mmACP_DAGB_PAGE_SIZE_GRP_1); 620 621 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 622 mmACP_DMA_DESC_BASE_ADDR); 623 624 /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 625 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 626 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 627 acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 628 629 /* 630 * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 631 * Now, turn off all of them. This can't be done in 'poweron' of 632 * ACP pm domain, as this requires ACP to be initialized. 633 * For Stoney, Memory gating is disabled,i.e SRAM Banks 634 * won't be turned off. The default state for SRAM banks is ON. 635 * Setting SRAM bank state code skipped for STONEY platform. 636 */ 637 if (asic_type != CHIP_STONEY) { 638 for (bank = 1; bank < 48; bank++) 639 acp_set_sram_bank_state(acp_mmio, bank, false); 640 } 641 return 0; 642} 643 644/* Deinitialize ACP */ 645static int acp_deinit(void __iomem *acp_mmio) 646{ 647 u32 val; 648 u32 count; 649 650 /* Assert Soft reset of ACP */ 651 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 652 653 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 654 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 655 656 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 657 while (true) { 658 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 659 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 660 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 661 break; 662 if (--count == 0) { 663 pr_err("Failed to reset ACP\n"); 664 return -ETIMEDOUT; 665 } 666 udelay(100); 667 } 668 /* Disable ACP clock */ 669 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 670 val &= ~ACP_CONTROL__ClkEn_MASK; 671 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 672 673 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 674 675 while (true) { 676 val = acp_reg_read(acp_mmio, mmACP_STATUS); 677 if (!(val & (u32)0x1)) 678 break; 679 if (--count == 0) { 680 pr_err("Failed to reset ACP\n"); 681 return -ETIMEDOUT; 682 } 683 udelay(100); 684 } 685 return 0; 686} 687 688/* ACP DMA irq handler routine for playback, capture usecases */ 689static irqreturn_t dma_irq_handler(int irq, void *arg) 690{ 691 u16 dscr_idx; 692 u32 intr_flag, ext_intr_status; 693 struct audio_drv_data *irq_data; 694 void __iomem *acp_mmio; 695 struct device *dev = arg; 696 bool valid_irq = false; 697 698 irq_data = dev_get_drvdata(dev); 699 acp_mmio = irq_data->acp_mmio; 700 701 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 702 intr_flag = (((ext_intr_status & 703 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 704 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 705 706 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 707 valid_irq = true; 708 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 709 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 710 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 711 } 712 713 if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { 714 valid_irq = true; 715 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); 716 acp_reg_write((intr_flag & 717 BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, 718 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 719 } 720 721 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 722 valid_irq = true; 723 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) == 724 CAPTURE_START_DMA_DESCR_CH15) 725 dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 726 else 727 dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 728 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 729 1, 0); 730 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 731 732 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 733 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 734 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 735 } 736 737 if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { 738 valid_irq = true; 739 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) == 740 CAPTURE_START_DMA_DESCR_CH11) 741 dscr_idx = CAPTURE_END_DMA_DESCR_CH10; 742 else 743 dscr_idx = CAPTURE_START_DMA_DESCR_CH10; 744 config_acp_dma_channel(acp_mmio, 745 ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 746 dscr_idx, 1, 0); 747 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 748 false); 749 750 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); 751 acp_reg_write((intr_flag & 752 BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, 753 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 754 } 755 756 if (valid_irq) 757 return IRQ_HANDLED; 758 else 759 return IRQ_NONE; 760} 761 762static int acp_dma_open(struct snd_soc_component *component, 763 struct snd_pcm_substream *substream) 764{ 765 u16 bank; 766 int ret = 0; 767 struct snd_pcm_runtime *runtime = substream->runtime; 768 struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 769 struct audio_substream_data *adata = 770 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 771 if (!adata) 772 return -ENOMEM; 773 774 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 775 switch (intr_data->asic_type) { 776 case CHIP_STONEY: 777 runtime->hw = acp_st_pcm_hardware_playback; 778 break; 779 default: 780 runtime->hw = acp_pcm_hardware_playback; 781 } 782 } else { 783 switch (intr_data->asic_type) { 784 case CHIP_STONEY: 785 runtime->hw = acp_st_pcm_hardware_capture; 786 break; 787 default: 788 runtime->hw = acp_pcm_hardware_capture; 789 } 790 } 791 792 ret = snd_pcm_hw_constraint_integer(runtime, 793 SNDRV_PCM_HW_PARAM_PERIODS); 794 if (ret < 0) { 795 dev_err(component->dev, "set integer constraint failed\n"); 796 kfree(adata); 797 return ret; 798 } 799 800 adata->acp_mmio = intr_data->acp_mmio; 801 runtime->private_data = adata; 802 803 /* 804 * Enable ACP irq, when neither playback or capture streams are 805 * active by the time when a new stream is being opened. 806 * This enablement is not required for another stream, if current 807 * stream is not closed 808 */ 809 if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && 810 !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream) 811 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 812 813 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 814 /* 815 * For Stoney, Memory gating is disabled,i.e SRAM Banks 816 * won't be turned off. The default state for SRAM banks is ON. 817 * Setting SRAM bank state code skipped for STONEY platform. 818 */ 819 if (intr_data->asic_type != CHIP_STONEY) { 820 for (bank = 1; bank <= 4; bank++) 821 acp_set_sram_bank_state(intr_data->acp_mmio, 822 bank, true); 823 } 824 } else { 825 if (intr_data->asic_type != CHIP_STONEY) { 826 for (bank = 5; bank <= 8; bank++) 827 acp_set_sram_bank_state(intr_data->acp_mmio, 828 bank, true); 829 } 830 } 831 832 return 0; 833} 834 835static int acp_dma_hw_params(struct snd_soc_component *component, 836 struct snd_pcm_substream *substream, 837 struct snd_pcm_hw_params *params) 838{ 839 uint64_t size; 840 u32 val = 0; 841 struct snd_pcm_runtime *runtime; 842 struct audio_substream_data *rtd; 843 struct snd_soc_pcm_runtime *prtd = asoc_substream_to_rtd(substream); 844 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 845 struct snd_soc_card *card = prtd->card; 846 struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card); 847 848 runtime = substream->runtime; 849 rtd = runtime->private_data; 850 851 if (WARN_ON(!rtd)) 852 return -EINVAL; 853 854 if (pinfo) { 855 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 856 rtd->i2s_instance = pinfo->play_i2s_instance; 857 } else { 858 rtd->i2s_instance = pinfo->cap_i2s_instance; 859 rtd->capture_channel = pinfo->capture_channel; 860 } 861 } 862 if (adata->asic_type == CHIP_STONEY) { 863 val = acp_reg_read(adata->acp_mmio, 864 mmACP_I2S_16BIT_RESOLUTION_EN); 865 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 866 switch (rtd->i2s_instance) { 867 case I2S_BT_INSTANCE: 868 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 869 break; 870 case I2S_SP_INSTANCE: 871 default: 872 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 873 } 874 } else { 875 switch (rtd->i2s_instance) { 876 case I2S_BT_INSTANCE: 877 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 878 break; 879 case I2S_SP_INSTANCE: 880 default: 881 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 882 } 883 } 884 acp_reg_write(val, adata->acp_mmio, 885 mmACP_I2S_16BIT_RESOLUTION_EN); 886 } 887 888 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 889 switch (rtd->i2s_instance) { 890 case I2S_BT_INSTANCE: 891 rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; 892 rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; 893 rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; 894 rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS; 895 rtd->destination = TO_BLUETOOTH; 896 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; 897 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; 898 rtd->byte_cnt_high_reg_offset = 899 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; 900 rtd->byte_cnt_low_reg_offset = 901 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; 902 adata->play_i2sbt_stream = substream; 903 break; 904 case I2S_SP_INSTANCE: 905 default: 906 switch (adata->asic_type) { 907 case CHIP_STONEY: 908 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 909 break; 910 default: 911 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 912 } 913 rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; 914 rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; 915 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 916 rtd->destination = TO_ACP_I2S_1; 917 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; 918 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; 919 rtd->byte_cnt_high_reg_offset = 920 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; 921 rtd->byte_cnt_low_reg_offset = 922 mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; 923 adata->play_i2ssp_stream = substream; 924 } 925 } else { 926 switch (rtd->i2s_instance) { 927 case I2S_BT_INSTANCE: 928 rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; 929 rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; 930 rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; 931 rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS; 932 rtd->destination = FROM_BLUETOOTH; 933 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; 934 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; 935 rtd->byte_cnt_high_reg_offset = 936 mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; 937 rtd->byte_cnt_low_reg_offset = 938 mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; 939 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11; 940 adata->capture_i2sbt_stream = substream; 941 break; 942 case I2S_SP_INSTANCE: 943 default: 944 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 945 rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM; 946 rtd->ch2 = ACP_TO_SYSRAM_CH_NUM; 947 switch (adata->asic_type) { 948 case CHIP_STONEY: 949 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; 950 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; 951 break; 952 default: 953 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 954 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; 955 } 956 rtd->destination = FROM_ACP_I2S_1; 957 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; 958 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; 959 rtd->byte_cnt_high_reg_offset = 960 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; 961 rtd->byte_cnt_low_reg_offset = 962 mmACP_I2S_RECEIVED_BYTE_CNT_LOW; 963 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15; 964 adata->capture_i2ssp_stream = substream; 965 } 966 } 967 968 size = params_buffer_bytes(params); 969 970 acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 971 /* Save for runtime private data */ 972 rtd->dma_addr = runtime->dma_addr; 973 rtd->order = get_order(size); 974 975 /* Fill the page table entries in ACP SRAM */ 976 rtd->size = size; 977 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 978 rtd->direction = substream->stream; 979 980 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 981 return 0; 982} 983 984static u64 acp_get_byte_count(struct audio_substream_data *rtd) 985{ 986 union acp_dma_count byte_count; 987 988 byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, 989 rtd->byte_cnt_high_reg_offset); 990 byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, 991 rtd->byte_cnt_low_reg_offset); 992 return byte_count.bytescount; 993} 994 995static snd_pcm_uframes_t acp_dma_pointer(struct snd_soc_component *component, 996 struct snd_pcm_substream *substream) 997{ 998 u32 buffersize; 999 u32 pos = 0; 1000 u64 bytescount = 0; 1001 u16 dscr; 1002 u32 period_bytes, delay; 1003 1004 struct snd_pcm_runtime *runtime = substream->runtime; 1005 struct audio_substream_data *rtd = runtime->private_data; 1006 1007 if (!rtd) 1008 return -EINVAL; 1009 1010 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1011 period_bytes = frames_to_bytes(runtime, runtime->period_size); 1012 bytescount = acp_get_byte_count(rtd); 1013 if (bytescount >= rtd->bytescount) 1014 bytescount -= rtd->bytescount; 1015 if (bytescount < period_bytes) { 1016 pos = 0; 1017 } else { 1018 dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr); 1019 if (dscr == rtd->dma_dscr_idx_1) 1020 pos = period_bytes; 1021 else 1022 pos = 0; 1023 } 1024 if (bytescount > 0) { 1025 delay = do_div(bytescount, period_bytes); 1026 runtime->delay = bytes_to_frames(runtime, delay); 1027 } 1028 } else { 1029 buffersize = frames_to_bytes(runtime, runtime->buffer_size); 1030 bytescount = acp_get_byte_count(rtd); 1031 if (bytescount > rtd->bytescount) 1032 bytescount -= rtd->bytescount; 1033 pos = do_div(bytescount, buffersize); 1034 } 1035 return bytes_to_frames(runtime, pos); 1036} 1037 1038static int acp_dma_mmap(struct snd_soc_component *component, 1039 struct snd_pcm_substream *substream, 1040 struct vm_area_struct *vma) 1041{ 1042 return snd_pcm_lib_default_mmap(substream, vma); 1043} 1044 1045static int acp_dma_prepare(struct snd_soc_component *component, 1046 struct snd_pcm_substream *substream) 1047{ 1048 struct snd_pcm_runtime *runtime = substream->runtime; 1049 struct audio_substream_data *rtd = runtime->private_data; 1050 u16 ch_acp_sysmem, ch_acp_i2s; 1051 1052 if (!rtd) 1053 return -EINVAL; 1054 1055 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 1056 ch_acp_sysmem = rtd->ch1; 1057 ch_acp_i2s = rtd->ch2; 1058 } else { 1059 ch_acp_i2s = rtd->ch1; 1060 ch_acp_sysmem = rtd->ch2; 1061 } 1062 config_acp_dma_channel(rtd->acp_mmio, 1063 ch_acp_sysmem, 1064 rtd->dma_dscr_idx_1, 1065 NUM_DSCRS_PER_CHANNEL, 0); 1066 config_acp_dma_channel(rtd->acp_mmio, 1067 ch_acp_i2s, 1068 rtd->dma_dscr_idx_2, 1069 NUM_DSCRS_PER_CHANNEL, 0); 1070 return 0; 1071} 1072 1073static int acp_dma_trigger(struct snd_soc_component *component, 1074 struct snd_pcm_substream *substream, int cmd) 1075{ 1076 int ret; 1077 1078 struct snd_pcm_runtime *runtime = substream->runtime; 1079 struct audio_substream_data *rtd = runtime->private_data; 1080 1081 if (!rtd) 1082 return -EINVAL; 1083 switch (cmd) { 1084 case SNDRV_PCM_TRIGGER_START: 1085 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1086 case SNDRV_PCM_TRIGGER_RESUME: 1087 rtd->bytescount = acp_get_byte_count(rtd); 1088 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1089 if (rtd->capture_channel == CAP_CHANNEL0) { 1090 acp_dma_cap_channel_disable(rtd->acp_mmio, 1091 CAP_CHANNEL1); 1092 acp_dma_cap_channel_enable(rtd->acp_mmio, 1093 CAP_CHANNEL0); 1094 } 1095 if (rtd->capture_channel == CAP_CHANNEL1) { 1096 acp_dma_cap_channel_disable(rtd->acp_mmio, 1097 CAP_CHANNEL0); 1098 acp_dma_cap_channel_enable(rtd->acp_mmio, 1099 CAP_CHANNEL1); 1100 } 1101 acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1102 } else { 1103 acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1104 acp_dma_start(rtd->acp_mmio, rtd->ch2, true); 1105 } 1106 ret = 0; 1107 break; 1108 case SNDRV_PCM_TRIGGER_STOP: 1109 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1110 case SNDRV_PCM_TRIGGER_SUSPEND: 1111 acp_dma_stop(rtd->acp_mmio, rtd->ch2); 1112 ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); 1113 break; 1114 default: 1115 ret = -EINVAL; 1116 } 1117 return ret; 1118} 1119 1120static int acp_dma_new(struct snd_soc_component *component, 1121 struct snd_soc_pcm_runtime *rtd) 1122{ 1123 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1124 struct device *parent = component->dev->parent; 1125 1126 switch (adata->asic_type) { 1127 case CHIP_STONEY: 1128 snd_pcm_set_managed_buffer_all(rtd->pcm, 1129 SNDRV_DMA_TYPE_DEV, 1130 parent, 1131 ST_MIN_BUFFER, 1132 ST_MAX_BUFFER); 1133 break; 1134 default: 1135 snd_pcm_set_managed_buffer_all(rtd->pcm, 1136 SNDRV_DMA_TYPE_DEV, 1137 parent, 1138 MIN_BUFFER, 1139 MAX_BUFFER); 1140 break; 1141 } 1142 return 0; 1143} 1144 1145static int acp_dma_close(struct snd_soc_component *component, 1146 struct snd_pcm_substream *substream) 1147{ 1148 u16 bank; 1149 struct snd_pcm_runtime *runtime = substream->runtime; 1150 struct audio_substream_data *rtd = runtime->private_data; 1151 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1152 1153 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1154 switch (rtd->i2s_instance) { 1155 case I2S_BT_INSTANCE: 1156 adata->play_i2sbt_stream = NULL; 1157 break; 1158 case I2S_SP_INSTANCE: 1159 default: 1160 adata->play_i2ssp_stream = NULL; 1161 /* 1162 * For Stoney, Memory gating is disabled,i.e SRAM Banks 1163 * won't be turned off. The default state for SRAM banks 1164 * is ON.Setting SRAM bank state code skipped for STONEY 1165 * platform. Added condition checks for Carrizo platform 1166 * only. 1167 */ 1168 if (adata->asic_type != CHIP_STONEY) { 1169 for (bank = 1; bank <= 4; bank++) 1170 acp_set_sram_bank_state(adata->acp_mmio, 1171 bank, false); 1172 } 1173 } 1174 } else { 1175 switch (rtd->i2s_instance) { 1176 case I2S_BT_INSTANCE: 1177 adata->capture_i2sbt_stream = NULL; 1178 break; 1179 case I2S_SP_INSTANCE: 1180 default: 1181 adata->capture_i2ssp_stream = NULL; 1182 if (adata->asic_type != CHIP_STONEY) { 1183 for (bank = 5; bank <= 8; bank++) 1184 acp_set_sram_bank_state(adata->acp_mmio, 1185 bank, false); 1186 } 1187 } 1188 } 1189 1190 /* 1191 * Disable ACP irq, when the current stream is being closed and 1192 * another stream is also not active. 1193 */ 1194 if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && 1195 !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) 1196 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1197 kfree(rtd); 1198 return 0; 1199} 1200 1201static const struct snd_soc_component_driver acp_asoc_platform = { 1202 .name = DRV_NAME, 1203 .open = acp_dma_open, 1204 .close = acp_dma_close, 1205 .hw_params = acp_dma_hw_params, 1206 .trigger = acp_dma_trigger, 1207 .pointer = acp_dma_pointer, 1208 .mmap = acp_dma_mmap, 1209 .prepare = acp_dma_prepare, 1210 .pcm_construct = acp_dma_new, 1211}; 1212 1213static int acp_audio_probe(struct platform_device *pdev) 1214{ 1215 int status; 1216 struct audio_drv_data *audio_drv_data; 1217 struct resource *res; 1218 const u32 *pdata = pdev->dev.platform_data; 1219 1220 if (!pdata) { 1221 dev_err(&pdev->dev, "Missing platform data\n"); 1222 return -ENODEV; 1223 } 1224 1225 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 1226 GFP_KERNEL); 1227 if (!audio_drv_data) 1228 return -ENOMEM; 1229 1230 audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0); 1231 if (IS_ERR(audio_drv_data->acp_mmio)) 1232 return PTR_ERR(audio_drv_data->acp_mmio); 1233 1234 /* 1235 * The following members gets populated in device 'open' 1236 * function. Till then interrupts are disabled in 'acp_init' 1237 * and device doesn't generate any interrupts. 1238 */ 1239 1240 audio_drv_data->play_i2ssp_stream = NULL; 1241 audio_drv_data->capture_i2ssp_stream = NULL; 1242 audio_drv_data->play_i2sbt_stream = NULL; 1243 audio_drv_data->capture_i2sbt_stream = NULL; 1244 1245 audio_drv_data->asic_type = *pdata; 1246 1247 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1248 if (!res) { 1249 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 1250 return -ENODEV; 1251 } 1252 1253 status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 1254 0, "ACP_IRQ", &pdev->dev); 1255 if (status) { 1256 dev_err(&pdev->dev, "ACP IRQ request failed\n"); 1257 return status; 1258 } 1259 1260 dev_set_drvdata(&pdev->dev, audio_drv_data); 1261 1262 /* Initialize the ACP */ 1263 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 1264 if (status) { 1265 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 1266 return status; 1267 } 1268 1269 status = devm_snd_soc_register_component(&pdev->dev, 1270 &acp_asoc_platform, NULL, 0); 1271 if (status != 0) { 1272 dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 1273 return status; 1274 } 1275 1276 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 1277 pm_runtime_use_autosuspend(&pdev->dev); 1278 pm_runtime_enable(&pdev->dev); 1279 1280 return status; 1281} 1282 1283static int acp_audio_remove(struct platform_device *pdev) 1284{ 1285 int status; 1286 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 1287 1288 status = acp_deinit(adata->acp_mmio); 1289 if (status) 1290 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 1291 pm_runtime_disable(&pdev->dev); 1292 1293 return 0; 1294} 1295 1296static int acp_pcm_resume(struct device *dev) 1297{ 1298 u16 bank; 1299 int status; 1300 struct audio_substream_data *rtd; 1301 struct audio_drv_data *adata = dev_get_drvdata(dev); 1302 1303 status = acp_init(adata->acp_mmio, adata->asic_type); 1304 if (status) { 1305 dev_err(dev, "ACP Init failed status:%d\n", status); 1306 return status; 1307 } 1308 1309 if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 1310 /* 1311 * For Stoney, Memory gating is disabled,i.e SRAM Banks 1312 * won't be turned off. The default state for SRAM banks is ON. 1313 * Setting SRAM bank state code skipped for STONEY platform. 1314 */ 1315 if (adata->asic_type != CHIP_STONEY) { 1316 for (bank = 1; bank <= 4; bank++) 1317 acp_set_sram_bank_state(adata->acp_mmio, bank, 1318 true); 1319 } 1320 rtd = adata->play_i2ssp_stream->runtime->private_data; 1321 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1322 } 1323 if (adata->capture_i2ssp_stream && 1324 adata->capture_i2ssp_stream->runtime) { 1325 if (adata->asic_type != CHIP_STONEY) { 1326 for (bank = 5; bank <= 8; bank++) 1327 acp_set_sram_bank_state(adata->acp_mmio, bank, 1328 true); 1329 } 1330 rtd = adata->capture_i2ssp_stream->runtime->private_data; 1331 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1332 } 1333 if (adata->asic_type != CHIP_CARRIZO) { 1334 if (adata->play_i2sbt_stream && 1335 adata->play_i2sbt_stream->runtime) { 1336 rtd = adata->play_i2sbt_stream->runtime->private_data; 1337 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1338 } 1339 if (adata->capture_i2sbt_stream && 1340 adata->capture_i2sbt_stream->runtime) { 1341 rtd = adata->capture_i2sbt_stream->runtime->private_data; 1342 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1343 } 1344 } 1345 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1346 return 0; 1347} 1348 1349static int acp_pcm_runtime_suspend(struct device *dev) 1350{ 1351 int status; 1352 struct audio_drv_data *adata = dev_get_drvdata(dev); 1353 1354 status = acp_deinit(adata->acp_mmio); 1355 if (status) 1356 dev_err(dev, "ACP Deinit failed status:%d\n", status); 1357 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1358 return 0; 1359} 1360 1361static int acp_pcm_runtime_resume(struct device *dev) 1362{ 1363 int status; 1364 struct audio_drv_data *adata = dev_get_drvdata(dev); 1365 1366 status = acp_init(adata->acp_mmio, adata->asic_type); 1367 if (status) { 1368 dev_err(dev, "ACP Init failed status:%d\n", status); 1369 return status; 1370 } 1371 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1372 return 0; 1373} 1374 1375static const struct dev_pm_ops acp_pm_ops = { 1376 .resume = acp_pcm_resume, 1377 .runtime_suspend = acp_pcm_runtime_suspend, 1378 .runtime_resume = acp_pcm_runtime_resume, 1379}; 1380 1381static struct platform_driver acp_dma_driver = { 1382 .probe = acp_audio_probe, 1383 .remove = acp_audio_remove, 1384 .driver = { 1385 .name = DRV_NAME, 1386 .pm = &acp_pm_ops, 1387 }, 1388}; 1389 1390module_platform_driver(acp_dma_driver); 1391 1392MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1393MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 1394MODULE_DESCRIPTION("AMD ACP PCM Driver"); 1395MODULE_LICENSE("GPL v2"); 1396MODULE_ALIAS("platform:"DRV_NAME); 1397