1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11#include <linux/init.h> 12#include <linux/delay.h> 13#include <linux/slab.h> 14#include <linux/mutex.h> 15#include <linux/module.h> 16#include <linux/firmware.h> 17#include <linux/kernel.h> 18#include <linux/types.h> 19#include <linux/io.h> 20#include <linux/pci.h> 21#include <asm/io.h> 22#include <sound/core.h> 23#include <sound/hda_codec.h> 24#include "hda_local.h" 25#include "hda_auto_parser.h" 26#include "hda_jack.h" 27 28#include "ca0132_regs.h" 29 30/* Enable this to see controls for tuning purpose. */ 31/*#define ENABLE_TUNING_CONTROLS*/ 32 33#ifdef ENABLE_TUNING_CONTROLS 34#include <sound/tlv.h> 35#endif 36 37#define FLOAT_ZERO 0x00000000 38#define FLOAT_ONE 0x3f800000 39#define FLOAT_TWO 0x40000000 40#define FLOAT_THREE 0x40400000 41#define FLOAT_FIVE 0x40a00000 42#define FLOAT_SIX 0x40c00000 43#define FLOAT_EIGHT 0x41000000 44#define FLOAT_MINUS_5 0xc0a00000 45 46#define UNSOL_TAG_DSP 0x16 47 48#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 49#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 50 51#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 52#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 53#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 54 55#define MASTERCONTROL 0x80 56#define MASTERCONTROL_ALLOC_DMA_CHAN 10 57#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 58 59#define WIDGET_CHIP_CTRL 0x15 60#define WIDGET_DSP_CTRL 0x16 61 62#define MEM_CONNID_MICIN1 3 63#define MEM_CONNID_MICIN2 5 64#define MEM_CONNID_MICOUT1 12 65#define MEM_CONNID_MICOUT2 14 66#define MEM_CONNID_WUH 10 67#define MEM_CONNID_DSP 16 68#define MEM_CONNID_DMIC 100 69 70#define SCP_SET 0 71#define SCP_GET 1 72 73#define EFX_FILE "ctefx.bin" 74#define DESKTOP_EFX_FILE "ctefx-desktop.bin" 75#define R3DI_EFX_FILE "ctefx-r3di.bin" 76 77#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78MODULE_FIRMWARE(EFX_FILE); 79MODULE_FIRMWARE(DESKTOP_EFX_FILE); 80MODULE_FIRMWARE(R3DI_EFX_FILE); 81#endif 82 83static const char *const dirstr[2] = { "Playback", "Capture" }; 84 85#define NUM_OF_OUTPUTS 2 86static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 87enum { 88 SPEAKER_OUT, 89 HEADPHONE_OUT, 90}; 91 92enum { 93 DIGITAL_MIC, 94 LINE_MIC_IN 95}; 96 97/* Strings for Input Source Enum Control */ 98static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 99#define IN_SRC_NUM_OF_INPUTS 3 100enum { 101 REAR_MIC, 102 REAR_LINE_IN, 103 FRONT_MIC, 104}; 105 106enum { 107#define VNODE_START_NID 0x80 108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 109 VNID_MIC, 110 VNID_HP_SEL, 111 VNID_AMIC1_SEL, 112 VNID_HP_ASEL, 113 VNID_AMIC1_ASEL, 114 VNODE_END_NID, 115#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 116 117#define EFFECT_START_NID 0x90 118#define OUT_EFFECT_START_NID EFFECT_START_NID 119 SURROUND = OUT_EFFECT_START_NID, 120 CRYSTALIZER, 121 DIALOG_PLUS, 122 SMART_VOLUME, 123 X_BASS, 124 EQUALIZER, 125 OUT_EFFECT_END_NID, 126#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 127 128#define IN_EFFECT_START_NID OUT_EFFECT_END_NID 129 ECHO_CANCELLATION = IN_EFFECT_START_NID, 130 VOICE_FOCUS, 131 MIC_SVM, 132 NOISE_REDUCTION, 133 IN_EFFECT_END_NID, 134#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 135 136 VOICEFX = IN_EFFECT_END_NID, 137 PLAY_ENHANCEMENT, 138 CRYSTAL_VOICE, 139 EFFECT_END_NID, 140 OUTPUT_SOURCE_ENUM, 141 INPUT_SOURCE_ENUM, 142 XBASS_XOVER, 143 EQ_PRESET_ENUM, 144 SMART_VOLUME_ENUM, 145 MIC_BOOST_ENUM, 146 AE5_HEADPHONE_GAIN_ENUM, 147 AE5_SOUND_FILTER_ENUM, 148 ZXR_HEADPHONE_GAIN, 149 SPEAKER_CHANNEL_CFG_ENUM, 150 SPEAKER_FULL_RANGE_FRONT, 151 SPEAKER_FULL_RANGE_REAR, 152 BASS_REDIRECTION, 153 BASS_REDIRECTION_XOVER, 154#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 155}; 156 157/* Effects values size*/ 158#define EFFECT_VALS_MAX_COUNT 12 159 160/* 161 * Default values for the effect slider controls, they are in order of their 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 163 * X-bass. 164 */ 165static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 166/* Amount of effect level sliders for ca0132_alt controls. */ 167#define EFFECT_LEVEL_SLIDERS 5 168 169/* Latency introduced by DSP blocks in milliseconds. */ 170#define DSP_CAPTURE_INIT_LATENCY 0 171#define DSP_CRYSTAL_VOICE_LATENCY 124 172#define DSP_PLAYBACK_INIT_LATENCY 13 173#define DSP_PLAY_ENHANCEMENT_LATENCY 30 174#define DSP_SPEAKER_OUT_LATENCY 7 175 176struct ct_effect { 177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 178 hda_nid_t nid; 179 int mid; /*effect module ID*/ 180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 181 int direct; /* 0:output; 1:input*/ 182 int params; /* number of default non-on/off params */ 183 /*effect default values, 1st is on/off. */ 184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 185}; 186 187#define EFX_DIR_OUT 0 188#define EFX_DIR_IN 1 189 190static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 191 { .name = "Surround", 192 .nid = SURROUND, 193 .mid = 0x96, 194 .reqs = {0, 1}, 195 .direct = EFX_DIR_OUT, 196 .params = 1, 197 .def_vals = {0x3F800000, 0x3F2B851F} 198 }, 199 { .name = "Crystalizer", 200 .nid = CRYSTALIZER, 201 .mid = 0x96, 202 .reqs = {7, 8}, 203 .direct = EFX_DIR_OUT, 204 .params = 1, 205 .def_vals = {0x3F800000, 0x3F266666} 206 }, 207 { .name = "Dialog Plus", 208 .nid = DIALOG_PLUS, 209 .mid = 0x96, 210 .reqs = {2, 3}, 211 .direct = EFX_DIR_OUT, 212 .params = 1, 213 .def_vals = {0x00000000, 0x3F000000} 214 }, 215 { .name = "Smart Volume", 216 .nid = SMART_VOLUME, 217 .mid = 0x96, 218 .reqs = {4, 5, 6}, 219 .direct = EFX_DIR_OUT, 220 .params = 2, 221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 222 }, 223 { .name = "X-Bass", 224 .nid = X_BASS, 225 .mid = 0x96, 226 .reqs = {24, 23, 25}, 227 .direct = EFX_DIR_OUT, 228 .params = 2, 229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 230 }, 231 { .name = "Equalizer", 232 .nid = EQUALIZER, 233 .mid = 0x96, 234 .reqs = {9, 10, 11, 12, 13, 14, 235 15, 16, 17, 18, 19, 20}, 236 .direct = EFX_DIR_OUT, 237 .params = 11, 238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000} 241 }, 242 { .name = "Echo Cancellation", 243 .nid = ECHO_CANCELLATION, 244 .mid = 0x95, 245 .reqs = {0, 1, 2, 3}, 246 .direct = EFX_DIR_IN, 247 .params = 3, 248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 249 }, 250 { .name = "Voice Focus", 251 .nid = VOICE_FOCUS, 252 .mid = 0x95, 253 .reqs = {6, 7, 8, 9}, 254 .direct = EFX_DIR_IN, 255 .params = 3, 256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 257 }, 258 { .name = "Mic SVM", 259 .nid = MIC_SVM, 260 .mid = 0x95, 261 .reqs = {44, 45}, 262 .direct = EFX_DIR_IN, 263 .params = 1, 264 .def_vals = {0x00000000, 0x3F3D70A4} 265 }, 266 { .name = "Noise Reduction", 267 .nid = NOISE_REDUCTION, 268 .mid = 0x95, 269 .reqs = {4, 5}, 270 .direct = EFX_DIR_IN, 271 .params = 1, 272 .def_vals = {0x3F800000, 0x3F000000} 273 }, 274 { .name = "VoiceFX", 275 .nid = VOICEFX, 276 .mid = 0x95, 277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 278 .direct = EFX_DIR_IN, 279 .params = 8, 280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 282 0x00000000} 283 } 284}; 285 286/* Tuning controls */ 287#ifdef ENABLE_TUNING_CONTROLS 288 289enum { 290#define TUNING_CTL_START_NID 0xC0 291 WEDGE_ANGLE = TUNING_CTL_START_NID, 292 SVM_LEVEL, 293 EQUALIZER_BAND_0, 294 EQUALIZER_BAND_1, 295 EQUALIZER_BAND_2, 296 EQUALIZER_BAND_3, 297 EQUALIZER_BAND_4, 298 EQUALIZER_BAND_5, 299 EQUALIZER_BAND_6, 300 EQUALIZER_BAND_7, 301 EQUALIZER_BAND_8, 302 EQUALIZER_BAND_9, 303 TUNING_CTL_END_NID 304#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 305}; 306 307struct ct_tuning_ctl { 308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 309 hda_nid_t parent_nid; 310 hda_nid_t nid; 311 int mid; /*effect module ID*/ 312 int req; /*effect module request*/ 313 int direct; /* 0:output; 1:input*/ 314 unsigned int def_val;/*effect default values*/ 315}; 316 317static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 318 { .name = "Wedge Angle", 319 .parent_nid = VOICE_FOCUS, 320 .nid = WEDGE_ANGLE, 321 .mid = 0x95, 322 .req = 8, 323 .direct = EFX_DIR_IN, 324 .def_val = 0x41F00000 325 }, 326 { .name = "SVM Level", 327 .parent_nid = MIC_SVM, 328 .nid = SVM_LEVEL, 329 .mid = 0x95, 330 .req = 45, 331 .direct = EFX_DIR_IN, 332 .def_val = 0x3F3D70A4 333 }, 334 { .name = "EQ Band0", 335 .parent_nid = EQUALIZER, 336 .nid = EQUALIZER_BAND_0, 337 .mid = 0x96, 338 .req = 11, 339 .direct = EFX_DIR_OUT, 340 .def_val = 0x00000000 341 }, 342 { .name = "EQ Band1", 343 .parent_nid = EQUALIZER, 344 .nid = EQUALIZER_BAND_1, 345 .mid = 0x96, 346 .req = 12, 347 .direct = EFX_DIR_OUT, 348 .def_val = 0x00000000 349 }, 350 { .name = "EQ Band2", 351 .parent_nid = EQUALIZER, 352 .nid = EQUALIZER_BAND_2, 353 .mid = 0x96, 354 .req = 13, 355 .direct = EFX_DIR_OUT, 356 .def_val = 0x00000000 357 }, 358 { .name = "EQ Band3", 359 .parent_nid = EQUALIZER, 360 .nid = EQUALIZER_BAND_3, 361 .mid = 0x96, 362 .req = 14, 363 .direct = EFX_DIR_OUT, 364 .def_val = 0x00000000 365 }, 366 { .name = "EQ Band4", 367 .parent_nid = EQUALIZER, 368 .nid = EQUALIZER_BAND_4, 369 .mid = 0x96, 370 .req = 15, 371 .direct = EFX_DIR_OUT, 372 .def_val = 0x00000000 373 }, 374 { .name = "EQ Band5", 375 .parent_nid = EQUALIZER, 376 .nid = EQUALIZER_BAND_5, 377 .mid = 0x96, 378 .req = 16, 379 .direct = EFX_DIR_OUT, 380 .def_val = 0x00000000 381 }, 382 { .name = "EQ Band6", 383 .parent_nid = EQUALIZER, 384 .nid = EQUALIZER_BAND_6, 385 .mid = 0x96, 386 .req = 17, 387 .direct = EFX_DIR_OUT, 388 .def_val = 0x00000000 389 }, 390 { .name = "EQ Band7", 391 .parent_nid = EQUALIZER, 392 .nid = EQUALIZER_BAND_7, 393 .mid = 0x96, 394 .req = 18, 395 .direct = EFX_DIR_OUT, 396 .def_val = 0x00000000 397 }, 398 { .name = "EQ Band8", 399 .parent_nid = EQUALIZER, 400 .nid = EQUALIZER_BAND_8, 401 .mid = 0x96, 402 .req = 19, 403 .direct = EFX_DIR_OUT, 404 .def_val = 0x00000000 405 }, 406 { .name = "EQ Band9", 407 .parent_nid = EQUALIZER, 408 .nid = EQUALIZER_BAND_9, 409 .mid = 0x96, 410 .req = 20, 411 .direct = EFX_DIR_OUT, 412 .def_val = 0x00000000 413 } 414}; 415#endif 416 417/* Voice FX Presets */ 418#define VOICEFX_MAX_PARAM_COUNT 9 419 420struct ct_voicefx { 421 char *name; 422 hda_nid_t nid; 423 int mid; 424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 425}; 426 427struct ct_voicefx_preset { 428 char *name; /*preset name*/ 429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 430}; 431 432static const struct ct_voicefx ca0132_voicefx = { 433 .name = "VoiceFX Capture Switch", 434 .nid = VOICEFX, 435 .mid = 0x95, 436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 437}; 438 439static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 440 { .name = "Neutral", 441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 442 0x44FA0000, 0x3F800000, 0x3F800000, 443 0x3F800000, 0x00000000, 0x00000000 } 444 }, 445 { .name = "Female2Male", 446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 447 0x44FA0000, 0x3F19999A, 0x3F866666, 448 0x3F800000, 0x00000000, 0x00000000 } 449 }, 450 { .name = "Male2Female", 451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 452 0x450AC000, 0x4017AE14, 0x3F6B851F, 453 0x3F800000, 0x00000000, 0x00000000 } 454 }, 455 { .name = "ScrappyKid", 456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 457 0x44FA0000, 0x40400000, 0x3F28F5C3, 458 0x3F800000, 0x00000000, 0x00000000 } 459 }, 460 { .name = "Elderly", 461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 462 0x44E10000, 0x3FB33333, 0x3FB9999A, 463 0x3F800000, 0x3E3A2E43, 0x00000000 } 464 }, 465 { .name = "Orc", 466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 467 0x45098000, 0x3F266666, 0x3FC00000, 468 0x3F800000, 0x00000000, 0x00000000 } 469 }, 470 { .name = "Elf", 471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 472 0x45193000, 0x3F8E147B, 0x3F75C28F, 473 0x3F800000, 0x00000000, 0x00000000 } 474 }, 475 { .name = "Dwarf", 476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 477 0x45007000, 0x3F451EB8, 0x3F7851EC, 478 0x3F800000, 0x00000000, 0x00000000 } 479 }, 480 { .name = "AlienBrute", 481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 482 0x451F6000, 0x3F266666, 0x3FA7D945, 483 0x3F800000, 0x3CF5C28F, 0x00000000 } 484 }, 485 { .name = "Robot", 486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 487 0x44FA0000, 0x3FB2718B, 0x3F800000, 488 0xBC07010E, 0x00000000, 0x00000000 } 489 }, 490 { .name = "Marine", 491 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 493 0x3F0A3D71, 0x00000000, 0x00000000 } 494 }, 495 { .name = "Emo", 496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 497 0x44FA0000, 0x3F800000, 0x3F800000, 498 0x3E4CCCCD, 0x00000000, 0x00000000 } 499 }, 500 { .name = "DeepVoice", 501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 503 0x3F800000, 0x00000000, 0x00000000 } 504 }, 505 { .name = "Munchkin", 506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 507 0x44FA0000, 0x3F800000, 0x3F1A043C, 508 0x3F800000, 0x00000000, 0x00000000 } 509 } 510}; 511 512/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 513 514#define EQ_PRESET_MAX_PARAM_COUNT 11 515 516struct ct_eq { 517 char *name; 518 hda_nid_t nid; 519 int mid; 520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 521}; 522 523struct ct_eq_preset { 524 char *name; /*preset name*/ 525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 526}; 527 528static const struct ct_eq ca0132_alt_eq_enum = { 529 .name = "FX: Equalizer Preset Switch", 530 .nid = EQ_PRESET_ENUM, 531 .mid = 0x96, 532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 533}; 534 535 536static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 537 { .name = "Flat", 538 .vals = { 0x00000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000 } 542 }, 543 { .name = "Acoustic", 544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 545 0x40000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x40000000, 547 0x40000000, 0x40000000 } 548 }, 549 { .name = "Classical", 550 .vals = { 0x00000000, 0x00000000, 0x40C00000, 551 0x40C00000, 0x40466666, 0x00000000, 552 0x00000000, 0x00000000, 0x00000000, 553 0x40466666, 0x40466666 } 554 }, 555 { .name = "Country", 556 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 558 0x00000000, 0x00000000, 0x40000000, 559 0x40466666, 0x40800000 } 560 }, 561 { .name = "Dance", 562 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 563 0x40466666, 0x40866666, 0xBF99999A, 564 0xBF99999A, 0x00000000, 0x00000000, 565 0x40800000, 0x40800000 } 566 }, 567 { .name = "Jazz", 568 .vals = { 0x00000000, 0x00000000, 0x00000000, 569 0x3F8CCCCD, 0x40800000, 0x40800000, 570 0x40800000, 0x00000000, 0x3F8CCCCD, 571 0x40466666, 0x40466666 } 572 }, 573 { .name = "New Age", 574 .vals = { 0x00000000, 0x00000000, 0x40000000, 575 0x40000000, 0x00000000, 0x00000000, 576 0x00000000, 0x3F8CCCCD, 0x40000000, 577 0x40000000, 0x40000000 } 578 }, 579 { .name = "Pop", 580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 581 0x40000000, 0x40000000, 0x00000000, 582 0xBF99999A, 0xBF99999A, 0x00000000, 583 0x40466666, 0x40C00000 } 584 }, 585 { .name = "Rock", 586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 587 0x3F8CCCCD, 0x40000000, 0xBF99999A, 588 0xBF99999A, 0x00000000, 0x00000000, 589 0x40800000, 0x40800000 } 590 }, 591 { .name = "Vocal", 592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 593 0xBF99999A, 0x00000000, 0x40466666, 594 0x40800000, 0x40466666, 0x00000000, 595 0x00000000, 0x3F8CCCCD } 596 } 597}; 598 599/* 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 601 * set as not being full range, and bass redirection is enabled, all 602 * frequencies below the crossover frequency are redirected to the LFE 603 * channel. If the surround configuration has no LFE channel, this can't be 604 * enabled. X-Bass must be disabled when using these. 605 */ 606enum speaker_range_reqs { 607 SPEAKER_BASS_REDIRECT = 0x15, 608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 609 /* Between 0x16-0x1a are the X-Bass reqs. */ 610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 615}; 616 617/* 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to 619 * module ID 0x96, the output effects module. 620 */ 621enum speaker_tuning_reqs { 622 /* 623 * Currently, this value is always set to 0.0f. However, on Windows, 624 * when selecting certain headphone profiles on the new Sound Blaster 625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 626 * sent. This gets the speaker EQ address area, which is then used to 627 * send over (presumably) an equalizer profile for the specific 628 * headphone setup. It is sent using the same method the DSP 629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 630 * file exists in linux firmware tree but goes unused. It would also 631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 633 * set to 1.0f. 634 */ 635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 645 /* 646 * Inversion is used when setting headphone virtualization to line 647 * out. Not sure why this is, but it's the only place it's ever used. 648 */ 649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 651 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 652 SPEAKER_TUNING_LFE_INVERT = 0x2c, 653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 657 /* Delay is used when setting surround speaker distance in Windows. */ 658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 660 SPEAKER_TUNING_CENTER_DELAY = 0x33, 661 SPEAKER_TUNING_LFE_DELAY = 0x34, 662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 666 /* Of these two, only mute seems to ever be used. */ 667 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 668 SPEAKER_TUNING_MUTE = 0x3a, 669}; 670 671/* Surround output channel count configuration structures. */ 672#define SPEAKER_CHANNEL_CFG_COUNT 5 673enum { 674 SPEAKER_CHANNELS_2_0, 675 SPEAKER_CHANNELS_2_1, 676 SPEAKER_CHANNELS_4_0, 677 SPEAKER_CHANNELS_4_1, 678 SPEAKER_CHANNELS_5_1, 679}; 680 681struct ca0132_alt_speaker_channel_cfg { 682 char *name; 683 unsigned int val; 684}; 685 686static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 687 { .name = "2.0", 688 .val = FLOAT_ONE 689 }, 690 { .name = "2.1", 691 .val = FLOAT_TWO 692 }, 693 { .name = "4.0", 694 .val = FLOAT_FIVE 695 }, 696 { .name = "4.1", 697 .val = FLOAT_SIX 698 }, 699 { .name = "5.1", 700 .val = FLOAT_EIGHT 701 } 702}; 703 704/* 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 706 * and I don't know what the third req is, but it's always zero. I assume it's 707 * some sort of update or set command to tell the DSP there's new volume info. 708 */ 709#define DSP_VOL_OUT 0 710#define DSP_VOL_IN 1 711 712struct ct_dsp_volume_ctl { 713 hda_nid_t vnid; 714 int mid; /* module ID*/ 715 unsigned int reqs[3]; /* scp req ID */ 716}; 717 718static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 719 { .vnid = VNID_SPK, 720 .mid = 0x32, 721 .reqs = {3, 4, 2} 722 }, 723 { .vnid = VNID_MIC, 724 .mid = 0x37, 725 .reqs = {2, 3, 1} 726 } 727}; 728 729/* Values for ca0113_mmio_command_set for selecting output. */ 730#define AE_CA0113_OUT_SET_COMMANDS 6 731struct ae_ca0113_output_set { 732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 735}; 736 737static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 740 /* Speakers. */ 741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 742 /* Headphones. */ 743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 744}; 745 746static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 749 /* Speakers. */ 750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 751 /* Headphones. */ 752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 753}; 754 755/* ae5 ca0113 command sequences to set headphone gain levels. */ 756#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 757struct ae5_headphone_gain_set { 758 char *name; 759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 760}; 761 762static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 763 { .name = "Low (16-31", 764 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 765 }, 766 { .name = "Medium (32-149", 767 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 768 }, 769 { .name = "High (150-600", 770 .vals = { 0xff, 0xff, 0xff, 0x7f } 771 } 772}; 773 774struct ae5_filter_set { 775 char *name; 776 unsigned int val; 777}; 778 779static const struct ae5_filter_set ae5_filter_presets[] = { 780 { .name = "Slow Roll Off", 781 .val = 0xa0 782 }, 783 { .name = "Minimum Phase", 784 .val = 0xc0 785 }, 786 { .name = "Fast Roll Off", 787 .val = 0x80 788 } 789}; 790 791enum hda_cmd_vendor_io { 792 /* for DspIO node */ 793 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 794 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 795 796 VENDOR_DSPIO_STATUS = 0xF01, 797 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 798 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 799 VENDOR_DSPIO_DSP_INIT = 0x703, 800 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 801 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 802 803 /* for ChipIO node */ 804 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 805 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 806 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 807 VENDOR_CHIPIO_DATA_LOW = 0x300, 808 VENDOR_CHIPIO_DATA_HIGH = 0x400, 809 810 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 811 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 812 813 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 814 VENDOR_CHIPIO_STATUS = 0xF01, 815 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 816 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 817 818 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 819 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 820 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 821 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 822 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 823 824 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 825 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 826 827 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 828 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 829 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 830 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 831 VENDOR_CHIPIO_FLAG_SET = 0x70F, 832 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 833 VENDOR_CHIPIO_PARAM_SET = 0x710, 834 VENDOR_CHIPIO_PARAM_GET = 0xF10, 835 836 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 837 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 838 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 839 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 840 841 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 842 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 843 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 844 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 845 846 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 847 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 848 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 849 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 850 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 851 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 852 853 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 854}; 855 856/* 857 * Control flag IDs 858 */ 859enum control_flag_id { 860 /* Connection manager stream setup is bypassed/enabled */ 861 CONTROL_FLAG_C_MGR = 0, 862 /* DSP DMA is bypassed/enabled */ 863 CONTROL_FLAG_DMA = 1, 864 /* 8051 'idle' mode is disabled/enabled */ 865 CONTROL_FLAG_IDLE_ENABLE = 2, 866 /* Tracker for the SPDIF-in path is bypassed/enabled */ 867 CONTROL_FLAG_TRACKER = 3, 868 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 869 CONTROL_FLAG_SPDIF2OUT = 4, 870 /* Digital Microphone is disabled/enabled */ 871 CONTROL_FLAG_DMIC = 5, 872 /* ADC_B rate is 48 kHz/96 kHz */ 873 CONTROL_FLAG_ADC_B_96KHZ = 6, 874 /* ADC_C rate is 48 kHz/96 kHz */ 875 CONTROL_FLAG_ADC_C_96KHZ = 7, 876 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 877 CONTROL_FLAG_DAC_96KHZ = 8, 878 /* DSP rate is 48 kHz/96 kHz */ 879 CONTROL_FLAG_DSP_96KHZ = 9, 880 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 881 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 882 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 883 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 884 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 885 CONTROL_FLAG_DECODE_LOOP = 12, 886 /* De-emphasis filter on DAC-1 disabled/enabled */ 887 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 888 /* De-emphasis filter on DAC-2 disabled/enabled */ 889 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 890 /* De-emphasis filter on DAC-3 disabled/enabled */ 891 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 892 /* High-pass filter on ADC_B disabled/enabled */ 893 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 894 /* High-pass filter on ADC_C disabled/enabled */ 895 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 896 /* Common mode on Port_A disabled/enabled */ 897 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 898 /* Common mode on Port_D disabled/enabled */ 899 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 900 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 901 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 902 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 903 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 904 /* ASI rate is 48kHz/96kHz */ 905 CONTROL_FLAG_ASI_96KHZ = 22, 906 /* DAC power settings able to control attached ports no/yes */ 907 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 908 /* Clock Stop OK reporting is disabled/enabled */ 909 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 910 /* Number of control flags */ 911 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 912}; 913 914/* 915 * Control parameter IDs 916 */ 917enum control_param_id { 918 /* 0: None, 1: Mic1In*/ 919 CONTROL_PARAM_VIP_SOURCE = 1, 920 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 921 CONTROL_PARAM_SPDIF1_SOURCE = 2, 922 /* Port A output stage gain setting to use when 16 Ohm output 923 * impedance is selected*/ 924 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 925 /* Port D output stage gain setting to use when 16 Ohm output 926 * impedance is selected*/ 927 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 928 929 /* 930 * This control param name was found in the 8051 memory, and makes 931 * sense given the fact the AE-5 uses it and has the ASI flag set. 932 */ 933 CONTROL_PARAM_ASI = 23, 934 935 /* Stream Control */ 936 937 /* Select stream with the given ID */ 938 CONTROL_PARAM_STREAM_ID = 24, 939 /* Source connection point for the selected stream */ 940 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 941 /* Destination connection point for the selected stream */ 942 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 943 /* Number of audio channels in the selected stream */ 944 CONTROL_PARAM_STREAMS_CHANNELS = 27, 945 /*Enable control for the selected stream */ 946 CONTROL_PARAM_STREAM_CONTROL = 28, 947 948 /* Connection Point Control */ 949 950 /* Select connection point with the given ID */ 951 CONTROL_PARAM_CONN_POINT_ID = 29, 952 /* Connection point sample rate */ 953 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 954 955 /* Node Control */ 956 957 /* Select HDA node with the given ID */ 958 CONTROL_PARAM_NODE_ID = 31 959}; 960 961/* 962 * Dsp Io Status codes 963 */ 964enum hda_vendor_status_dspio { 965 /* Success */ 966 VENDOR_STATUS_DSPIO_OK = 0x00, 967 /* Busy, unable to accept new command, the host must retry */ 968 VENDOR_STATUS_DSPIO_BUSY = 0x01, 969 /* SCP command queue is full */ 970 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 971 /* SCP response queue is empty */ 972 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 973}; 974 975/* 976 * Chip Io Status codes 977 */ 978enum hda_vendor_status_chipio { 979 /* Success */ 980 VENDOR_STATUS_CHIPIO_OK = 0x00, 981 /* Busy, unable to accept new command, the host must retry */ 982 VENDOR_STATUS_CHIPIO_BUSY = 0x01 983}; 984 985/* 986 * CA0132 sample rate 987 */ 988enum ca0132_sample_rate { 989 SR_6_000 = 0x00, 990 SR_8_000 = 0x01, 991 SR_9_600 = 0x02, 992 SR_11_025 = 0x03, 993 SR_16_000 = 0x04, 994 SR_22_050 = 0x05, 995 SR_24_000 = 0x06, 996 SR_32_000 = 0x07, 997 SR_44_100 = 0x08, 998 SR_48_000 = 0x09, 999 SR_88_200 = 0x0A, 1000 SR_96_000 = 0x0B, 1001 SR_144_000 = 0x0C, 1002 SR_176_400 = 0x0D, 1003 SR_192_000 = 0x0E, 1004 SR_384_000 = 0x0F, 1005 1006 SR_COUNT = 0x10, 1007 1008 SR_RATE_UNKNOWN = 0x1F 1009}; 1010 1011enum dsp_download_state { 1012 DSP_DOWNLOAD_FAILED = -1, 1013 DSP_DOWNLOAD_INIT = 0, 1014 DSP_DOWNLOADING = 1, 1015 DSP_DOWNLOADED = 2 1016}; 1017 1018/* retrieve parameters from hda format */ 1019#define get_hdafmt_chs(fmt) (fmt & 0xf) 1020#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1021#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1022#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1023 1024/* 1025 * CA0132 specific 1026 */ 1027 1028struct ca0132_spec { 1029 const struct snd_kcontrol_new *mixers[5]; 1030 unsigned int num_mixers; 1031 const struct hda_verb *base_init_verbs; 1032 const struct hda_verb *base_exit_verbs; 1033 const struct hda_verb *chip_init_verbs; 1034 const struct hda_verb *desktop_init_verbs; 1035 struct hda_verb *spec_init_verbs; 1036 struct auto_pin_cfg autocfg; 1037 1038 /* Nodes configurations */ 1039 struct hda_multi_out multiout; 1040 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1041 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1042 unsigned int num_outputs; 1043 hda_nid_t input_pins[AUTO_PIN_LAST]; 1044 hda_nid_t adcs[AUTO_PIN_LAST]; 1045 hda_nid_t dig_out; 1046 hda_nid_t dig_in; 1047 unsigned int num_inputs; 1048 hda_nid_t shared_mic_nid; 1049 hda_nid_t shared_out_nid; 1050 hda_nid_t unsol_tag_hp; 1051 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1052 hda_nid_t unsol_tag_amic1; 1053 1054 /* chip access */ 1055 struct mutex chipio_mutex; /* chip access mutex */ 1056 u32 curr_chip_addx; 1057 1058 /* DSP download related */ 1059 enum dsp_download_state dsp_state; 1060 unsigned int dsp_stream_id; 1061 unsigned int wait_scp; 1062 unsigned int wait_scp_header; 1063 unsigned int wait_num_data; 1064 unsigned int scp_resp_header; 1065 unsigned int scp_resp_data[4]; 1066 unsigned int scp_resp_count; 1067 bool startup_check_entered; 1068 bool dsp_reload; 1069 1070 /* mixer and effects related */ 1071 unsigned char dmic_ctl; 1072 int cur_out_type; 1073 int cur_mic_type; 1074 long vnode_lvol[VNODES_COUNT]; 1075 long vnode_rvol[VNODES_COUNT]; 1076 long vnode_lswitch[VNODES_COUNT]; 1077 long vnode_rswitch[VNODES_COUNT]; 1078 long effects_switch[EFFECTS_COUNT]; 1079 long voicefx_val; 1080 long cur_mic_boost; 1081 /* ca0132_alt control related values */ 1082 unsigned char in_enum_val; 1083 unsigned char out_enum_val; 1084 unsigned char channel_cfg_val; 1085 unsigned char speaker_range_val[2]; 1086 unsigned char mic_boost_enum_val; 1087 unsigned char smart_volume_setting; 1088 unsigned char bass_redirection_val; 1089 long bass_redirect_xover_freq; 1090 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1091 long xbass_xover_freq; 1092 long eq_preset_val; 1093 unsigned int tlv[4]; 1094 struct hda_vmaster_mute_hook vmaster_mute; 1095 /* AE-5 Control values */ 1096 unsigned char ae5_headphone_gain_val; 1097 unsigned char ae5_filter_val; 1098 /* ZxR Control Values */ 1099 unsigned char zxr_gain_set; 1100 1101 struct hda_codec *codec; 1102 struct delayed_work unsol_hp_work; 1103 int quirk; 1104 1105#ifdef ENABLE_TUNING_CONTROLS 1106 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1107#endif 1108 /* 1109 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1110 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1111 * things. 1112 */ 1113 bool use_pci_mmio; 1114 void __iomem *mem_base; 1115 1116 /* 1117 * Whether or not to use the alt functions like alt_select_out, 1118 * alt_select_in, etc. Only used on desktop codecs for now, because of 1119 * surround sound support. 1120 */ 1121 bool use_alt_functions; 1122 1123 /* 1124 * Whether or not to use alt controls: volume effect sliders, EQ 1125 * presets, smart volume presets, and new control names with FX prefix. 1126 * Renames PlayEnhancement and CrystalVoice too. 1127 */ 1128 bool use_alt_controls; 1129}; 1130 1131/* 1132 * CA0132 quirks table 1133 */ 1134enum { 1135 QUIRK_NONE, 1136 QUIRK_ALIENWARE, 1137 QUIRK_ALIENWARE_M17XR4, 1138 QUIRK_SBZ, 1139 QUIRK_ZXR, 1140 QUIRK_ZXR_DBPRO, 1141 QUIRK_R3DI, 1142 QUIRK_R3D, 1143 QUIRK_AE5, 1144 QUIRK_AE7, 1145}; 1146 1147#ifdef CONFIG_PCI 1148#define ca0132_quirk(spec) ((spec)->quirk) 1149#define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1150#define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1151#define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1152#else 1153#define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1154#define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1155#define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1156#define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1157#endif 1158 1159static const struct hda_pintbl alienware_pincfgs[] = { 1160 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1161 { 0x0c, 0x411111f0 }, /* N/A */ 1162 { 0x0d, 0x411111f0 }, /* N/A */ 1163 { 0x0e, 0x411111f0 }, /* N/A */ 1164 { 0x0f, 0x0321101f }, /* HP */ 1165 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1166 { 0x11, 0x03a11021 }, /* Mic */ 1167 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1168 { 0x13, 0x411111f0 }, /* N/A */ 1169 { 0x18, 0x411111f0 }, /* N/A */ 1170 {} 1171}; 1172 1173/* Sound Blaster Z pin configs taken from Windows Driver */ 1174static const struct hda_pintbl sbz_pincfgs[] = { 1175 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1176 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1177 { 0x0d, 0x014510f0 }, /* Digital Out */ 1178 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1179 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1180 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1181 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1182 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1183 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1184 { 0x18, 0x50d000f0 }, /* N/A */ 1185 {} 1186}; 1187 1188/* Sound Blaster ZxR pin configs taken from Windows Driver */ 1189static const struct hda_pintbl zxr_pincfgs[] = { 1190 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1191 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1192 { 0x0d, 0x014510f0 }, /* Digital Out */ 1193 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1194 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1195 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1196 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1197 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1198 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1199 { 0x18, 0x50d000f0 }, /* N/A */ 1200 {} 1201}; 1202 1203/* Recon3D pin configs taken from Windows Driver */ 1204static const struct hda_pintbl r3d_pincfgs[] = { 1205 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1206 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1207 { 0x0d, 0x014510f0 }, /* Digital Out */ 1208 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1209 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1210 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1211 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1212 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1213 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1214 { 0x18, 0x50d000f0 }, /* N/A */ 1215 {} 1216}; 1217 1218/* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1219static const struct hda_pintbl ae5_pincfgs[] = { 1220 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1221 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1222 { 0x0d, 0x014510f0 }, /* Digital Out */ 1223 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1224 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1225 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1226 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1227 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1228 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1229 { 0x18, 0x50d000f0 }, /* N/A */ 1230 {} 1231}; 1232 1233/* Recon3D integrated pin configs taken from Windows Driver */ 1234static const struct hda_pintbl r3di_pincfgs[] = { 1235 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1236 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1237 { 0x0d, 0x014510f0 }, /* Digital Out */ 1238 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1239 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1240 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1241 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1242 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1243 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1244 { 0x18, 0x500000f0 }, /* N/A */ 1245 {} 1246}; 1247 1248static const struct hda_pintbl ae7_pincfgs[] = { 1249 { 0x0b, 0x01017010 }, 1250 { 0x0c, 0x014510f0 }, 1251 { 0x0d, 0x414510f0 }, 1252 { 0x0e, 0x01c520f0 }, 1253 { 0x0f, 0x01017114 }, 1254 { 0x10, 0x01017011 }, 1255 { 0x11, 0x018170ff }, 1256 { 0x12, 0x01a170f0 }, 1257 { 0x13, 0x908700f0 }, 1258 { 0x18, 0x500000f0 }, 1259 {} 1260}; 1261 1262static const struct snd_pci_quirk ca0132_quirks[] = { 1263 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1264 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1265 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1266 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1267 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1268 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1269 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1270 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1271 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1272 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1273 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1274 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1275 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), 1276 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), 1277 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1278 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1279 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1280 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), 1281 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1282 {} 1283}; 1284 1285/* Output selection quirk info structures. */ 1286#define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1287#define MAX_QUIRK_SCP_SET_VALS 2 1288struct ca0132_alt_out_set_info { 1289 unsigned int dac2port; /* ParamID 0x0d value. */ 1290 1291 bool has_hda_gpio; 1292 char hda_gpio_pin; 1293 char hda_gpio_set; 1294 1295 unsigned int mmio_gpio_count; 1296 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1297 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1298 1299 unsigned int scp_cmds_count; 1300 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1301 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1302 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1303 1304 bool has_chipio_write; 1305 unsigned int chipio_write_addr; 1306 unsigned int chipio_write_data; 1307}; 1308 1309struct ca0132_alt_out_set_quirk_data { 1310 int quirk_id; 1311 1312 bool has_headphone_gain; 1313 bool is_ae_series; 1314 1315 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1316}; 1317 1318static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1319 { .quirk_id = QUIRK_R3DI, 1320 .has_headphone_gain = false, 1321 .is_ae_series = false, 1322 .out_set_info = { 1323 /* Speakers. */ 1324 { .dac2port = 0x24, 1325 .has_hda_gpio = true, 1326 .hda_gpio_pin = 2, 1327 .hda_gpio_set = 1, 1328 .mmio_gpio_count = 0, 1329 .scp_cmds_count = 0, 1330 .has_chipio_write = false, 1331 }, 1332 /* Headphones. */ 1333 { .dac2port = 0x21, 1334 .has_hda_gpio = true, 1335 .hda_gpio_pin = 2, 1336 .hda_gpio_set = 0, 1337 .mmio_gpio_count = 0, 1338 .scp_cmds_count = 0, 1339 .has_chipio_write = false, 1340 } }, 1341 }, 1342 { .quirk_id = QUIRK_R3D, 1343 .has_headphone_gain = false, 1344 .is_ae_series = false, 1345 .out_set_info = { 1346 /* Speakers. */ 1347 { .dac2port = 0x24, 1348 .has_hda_gpio = false, 1349 .mmio_gpio_count = 1, 1350 .mmio_gpio_pin = { 1 }, 1351 .mmio_gpio_set = { 1 }, 1352 .scp_cmds_count = 0, 1353 .has_chipio_write = false, 1354 }, 1355 /* Headphones. */ 1356 { .dac2port = 0x21, 1357 .has_hda_gpio = false, 1358 .mmio_gpio_count = 1, 1359 .mmio_gpio_pin = { 1 }, 1360 .mmio_gpio_set = { 0 }, 1361 .scp_cmds_count = 0, 1362 .has_chipio_write = false, 1363 } }, 1364 }, 1365 { .quirk_id = QUIRK_SBZ, 1366 .has_headphone_gain = false, 1367 .is_ae_series = false, 1368 .out_set_info = { 1369 /* Speakers. */ 1370 { .dac2port = 0x18, 1371 .has_hda_gpio = false, 1372 .mmio_gpio_count = 3, 1373 .mmio_gpio_pin = { 7, 4, 1 }, 1374 .mmio_gpio_set = { 0, 1, 1 }, 1375 .scp_cmds_count = 0, 1376 .has_chipio_write = false, }, 1377 /* Headphones. */ 1378 { .dac2port = 0x12, 1379 .has_hda_gpio = false, 1380 .mmio_gpio_count = 3, 1381 .mmio_gpio_pin = { 7, 4, 1 }, 1382 .mmio_gpio_set = { 1, 1, 0 }, 1383 .scp_cmds_count = 0, 1384 .has_chipio_write = false, 1385 } }, 1386 }, 1387 { .quirk_id = QUIRK_ZXR, 1388 .has_headphone_gain = true, 1389 .is_ae_series = false, 1390 .out_set_info = { 1391 /* Speakers. */ 1392 { .dac2port = 0x24, 1393 .has_hda_gpio = false, 1394 .mmio_gpio_count = 3, 1395 .mmio_gpio_pin = { 2, 3, 5 }, 1396 .mmio_gpio_set = { 1, 1, 0 }, 1397 .scp_cmds_count = 0, 1398 .has_chipio_write = false, 1399 }, 1400 /* Headphones. */ 1401 { .dac2port = 0x21, 1402 .has_hda_gpio = false, 1403 .mmio_gpio_count = 3, 1404 .mmio_gpio_pin = { 2, 3, 5 }, 1405 .mmio_gpio_set = { 0, 1, 1 }, 1406 .scp_cmds_count = 0, 1407 .has_chipio_write = false, 1408 } }, 1409 }, 1410 { .quirk_id = QUIRK_AE5, 1411 .has_headphone_gain = true, 1412 .is_ae_series = true, 1413 .out_set_info = { 1414 /* Speakers. */ 1415 { .dac2port = 0xa4, 1416 .has_hda_gpio = false, 1417 .mmio_gpio_count = 0, 1418 .scp_cmds_count = 2, 1419 .scp_cmd_mid = { 0x96, 0x96 }, 1420 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1421 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1422 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1423 .has_chipio_write = true, 1424 .chipio_write_addr = 0x0018b03c, 1425 .chipio_write_data = 0x00000012 1426 }, 1427 /* Headphones. */ 1428 { .dac2port = 0xa1, 1429 .has_hda_gpio = false, 1430 .mmio_gpio_count = 0, 1431 .scp_cmds_count = 2, 1432 .scp_cmd_mid = { 0x96, 0x96 }, 1433 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1434 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1435 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1436 .has_chipio_write = true, 1437 .chipio_write_addr = 0x0018b03c, 1438 .chipio_write_data = 0x00000012 1439 } }, 1440 }, 1441 { .quirk_id = QUIRK_AE7, 1442 .has_headphone_gain = true, 1443 .is_ae_series = true, 1444 .out_set_info = { 1445 /* Speakers. */ 1446 { .dac2port = 0x58, 1447 .has_hda_gpio = false, 1448 .mmio_gpio_count = 1, 1449 .mmio_gpio_pin = { 0 }, 1450 .mmio_gpio_set = { 1 }, 1451 .scp_cmds_count = 2, 1452 .scp_cmd_mid = { 0x96, 0x96 }, 1453 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1454 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1455 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1456 .has_chipio_write = true, 1457 .chipio_write_addr = 0x0018b03c, 1458 .chipio_write_data = 0x00000000 1459 }, 1460 /* Headphones. */ 1461 { .dac2port = 0x58, 1462 .has_hda_gpio = false, 1463 .mmio_gpio_count = 1, 1464 .mmio_gpio_pin = { 0 }, 1465 .mmio_gpio_set = { 1 }, 1466 .scp_cmds_count = 2, 1467 .scp_cmd_mid = { 0x96, 0x96 }, 1468 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1469 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1470 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1471 .has_chipio_write = true, 1472 .chipio_write_addr = 0x0018b03c, 1473 .chipio_write_data = 0x00000010 1474 } }, 1475 } 1476}; 1477 1478/* 1479 * CA0132 codec access 1480 */ 1481static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1482 unsigned int verb, unsigned int parm, unsigned int *res) 1483{ 1484 unsigned int response; 1485 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1486 *res = response; 1487 1488 return ((response == -1) ? -1 : 0); 1489} 1490 1491static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1492 unsigned short converter_format, unsigned int *res) 1493{ 1494 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1495 converter_format & 0xffff, res); 1496} 1497 1498static int codec_set_converter_stream_channel(struct hda_codec *codec, 1499 hda_nid_t nid, unsigned char stream, 1500 unsigned char channel, unsigned int *res) 1501{ 1502 unsigned char converter_stream_channel = 0; 1503 1504 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1505 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1506 converter_stream_channel, res); 1507} 1508 1509/* Chip access helper function */ 1510static int chipio_send(struct hda_codec *codec, 1511 unsigned int reg, 1512 unsigned int data) 1513{ 1514 unsigned int res; 1515 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1516 1517 /* send bits of data specified by reg */ 1518 do { 1519 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1520 reg, data); 1521 if (res == VENDOR_STATUS_CHIPIO_OK) 1522 return 0; 1523 msleep(20); 1524 } while (time_before(jiffies, timeout)); 1525 1526 return -EIO; 1527} 1528 1529/* 1530 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1531 */ 1532static int chipio_write_address(struct hda_codec *codec, 1533 unsigned int chip_addx) 1534{ 1535 struct ca0132_spec *spec = codec->spec; 1536 int res; 1537 1538 if (spec->curr_chip_addx == chip_addx) 1539 return 0; 1540 1541 /* send low 16 bits of the address */ 1542 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1543 chip_addx & 0xffff); 1544 1545 if (res != -EIO) { 1546 /* send high 16 bits of the address */ 1547 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1548 chip_addx >> 16); 1549 } 1550 1551 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1552 1553 return res; 1554} 1555 1556/* 1557 * Write data through the vendor widget -- NOT protected by the Mutex! 1558 */ 1559static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1560{ 1561 struct ca0132_spec *spec = codec->spec; 1562 int res; 1563 1564 /* send low 16 bits of the data */ 1565 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1566 1567 if (res != -EIO) { 1568 /* send high 16 bits of the data */ 1569 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1570 data >> 16); 1571 } 1572 1573 /*If no error encountered, automatically increment the address 1574 as per chip behaviour*/ 1575 spec->curr_chip_addx = (res != -EIO) ? 1576 (spec->curr_chip_addx + 4) : ~0U; 1577 return res; 1578} 1579 1580/* 1581 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1582 */ 1583static int chipio_write_data_multiple(struct hda_codec *codec, 1584 const u32 *data, 1585 unsigned int count) 1586{ 1587 int status = 0; 1588 1589 if (data == NULL) { 1590 codec_dbg(codec, "chipio_write_data null ptr\n"); 1591 return -EINVAL; 1592 } 1593 1594 while ((count-- != 0) && (status == 0)) 1595 status = chipio_write_data(codec, *data++); 1596 1597 return status; 1598} 1599 1600 1601/* 1602 * Read data through the vendor widget -- NOT protected by the Mutex! 1603 */ 1604static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1605{ 1606 struct ca0132_spec *spec = codec->spec; 1607 int res; 1608 1609 /* post read */ 1610 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1611 1612 if (res != -EIO) { 1613 /* read status */ 1614 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1615 } 1616 1617 if (res != -EIO) { 1618 /* read data */ 1619 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1620 VENDOR_CHIPIO_HIC_READ_DATA, 1621 0); 1622 } 1623 1624 /*If no error encountered, automatically increment the address 1625 as per chip behaviour*/ 1626 spec->curr_chip_addx = (res != -EIO) ? 1627 (spec->curr_chip_addx + 4) : ~0U; 1628 return res; 1629} 1630 1631/* 1632 * Write given value to the given address through the chip I/O widget. 1633 * protected by the Mutex 1634 */ 1635static int chipio_write(struct hda_codec *codec, 1636 unsigned int chip_addx, const unsigned int data) 1637{ 1638 struct ca0132_spec *spec = codec->spec; 1639 int err; 1640 1641 mutex_lock(&spec->chipio_mutex); 1642 1643 /* write the address, and if successful proceed to write data */ 1644 err = chipio_write_address(codec, chip_addx); 1645 if (err < 0) 1646 goto exit; 1647 1648 err = chipio_write_data(codec, data); 1649 if (err < 0) 1650 goto exit; 1651 1652exit: 1653 mutex_unlock(&spec->chipio_mutex); 1654 return err; 1655} 1656 1657/* 1658 * Write given value to the given address through the chip I/O widget. 1659 * not protected by the Mutex 1660 */ 1661static int chipio_write_no_mutex(struct hda_codec *codec, 1662 unsigned int chip_addx, const unsigned int data) 1663{ 1664 int err; 1665 1666 1667 /* write the address, and if successful proceed to write data */ 1668 err = chipio_write_address(codec, chip_addx); 1669 if (err < 0) 1670 goto exit; 1671 1672 err = chipio_write_data(codec, data); 1673 if (err < 0) 1674 goto exit; 1675 1676exit: 1677 return err; 1678} 1679 1680/* 1681 * Write multiple values to the given address through the chip I/O widget. 1682 * protected by the Mutex 1683 */ 1684static int chipio_write_multiple(struct hda_codec *codec, 1685 u32 chip_addx, 1686 const u32 *data, 1687 unsigned int count) 1688{ 1689 struct ca0132_spec *spec = codec->spec; 1690 int status; 1691 1692 mutex_lock(&spec->chipio_mutex); 1693 status = chipio_write_address(codec, chip_addx); 1694 if (status < 0) 1695 goto error; 1696 1697 status = chipio_write_data_multiple(codec, data, count); 1698error: 1699 mutex_unlock(&spec->chipio_mutex); 1700 1701 return status; 1702} 1703 1704/* 1705 * Read the given address through the chip I/O widget 1706 * protected by the Mutex 1707 */ 1708static int chipio_read(struct hda_codec *codec, 1709 unsigned int chip_addx, unsigned int *data) 1710{ 1711 struct ca0132_spec *spec = codec->spec; 1712 int err; 1713 1714 mutex_lock(&spec->chipio_mutex); 1715 1716 /* write the address, and if successful proceed to write data */ 1717 err = chipio_write_address(codec, chip_addx); 1718 if (err < 0) 1719 goto exit; 1720 1721 err = chipio_read_data(codec, data); 1722 if (err < 0) 1723 goto exit; 1724 1725exit: 1726 mutex_unlock(&spec->chipio_mutex); 1727 return err; 1728} 1729 1730/* 1731 * Set chip control flags through the chip I/O widget. 1732 */ 1733static void chipio_set_control_flag(struct hda_codec *codec, 1734 enum control_flag_id flag_id, 1735 bool flag_state) 1736{ 1737 unsigned int val; 1738 unsigned int flag_bit; 1739 1740 flag_bit = (flag_state ? 1 : 0); 1741 val = (flag_bit << 7) | (flag_id); 1742 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1743 VENDOR_CHIPIO_FLAG_SET, val); 1744} 1745 1746/* 1747 * Set chip parameters through the chip I/O widget. 1748 */ 1749static void chipio_set_control_param(struct hda_codec *codec, 1750 enum control_param_id param_id, int param_val) 1751{ 1752 struct ca0132_spec *spec = codec->spec; 1753 int val; 1754 1755 if ((param_id < 32) && (param_val < 8)) { 1756 val = (param_val << 5) | (param_id); 1757 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1758 VENDOR_CHIPIO_PARAM_SET, val); 1759 } else { 1760 mutex_lock(&spec->chipio_mutex); 1761 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1762 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1763 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1764 param_id); 1765 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1766 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1767 param_val); 1768 } 1769 mutex_unlock(&spec->chipio_mutex); 1770 } 1771} 1772 1773/* 1774 * Set chip parameters through the chip I/O widget. NO MUTEX. 1775 */ 1776static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1777 enum control_param_id param_id, int param_val) 1778{ 1779 int val; 1780 1781 if ((param_id < 32) && (param_val < 8)) { 1782 val = (param_val << 5) | (param_id); 1783 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1784 VENDOR_CHIPIO_PARAM_SET, val); 1785 } else { 1786 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1787 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1788 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1789 param_id); 1790 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1791 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1792 param_val); 1793 } 1794 } 1795} 1796/* 1797 * Connect stream to a source point, and then connect 1798 * that source point to a destination point. 1799 */ 1800static void chipio_set_stream_source_dest(struct hda_codec *codec, 1801 int streamid, int source_point, int dest_point) 1802{ 1803 chipio_set_control_param_no_mutex(codec, 1804 CONTROL_PARAM_STREAM_ID, streamid); 1805 chipio_set_control_param_no_mutex(codec, 1806 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1807 chipio_set_control_param_no_mutex(codec, 1808 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1809} 1810 1811/* 1812 * Set number of channels in the selected stream. 1813 */ 1814static void chipio_set_stream_channels(struct hda_codec *codec, 1815 int streamid, unsigned int channels) 1816{ 1817 chipio_set_control_param_no_mutex(codec, 1818 CONTROL_PARAM_STREAM_ID, streamid); 1819 chipio_set_control_param_no_mutex(codec, 1820 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1821} 1822 1823/* 1824 * Enable/Disable audio stream. 1825 */ 1826static void chipio_set_stream_control(struct hda_codec *codec, 1827 int streamid, int enable) 1828{ 1829 chipio_set_control_param_no_mutex(codec, 1830 CONTROL_PARAM_STREAM_ID, streamid); 1831 chipio_set_control_param_no_mutex(codec, 1832 CONTROL_PARAM_STREAM_CONTROL, enable); 1833} 1834 1835 1836/* 1837 * Set sampling rate of the connection point. NO MUTEX. 1838 */ 1839static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1840 int connid, enum ca0132_sample_rate rate) 1841{ 1842 chipio_set_control_param_no_mutex(codec, 1843 CONTROL_PARAM_CONN_POINT_ID, connid); 1844 chipio_set_control_param_no_mutex(codec, 1845 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1846} 1847 1848/* 1849 * Set sampling rate of the connection point. 1850 */ 1851static void chipio_set_conn_rate(struct hda_codec *codec, 1852 int connid, enum ca0132_sample_rate rate) 1853{ 1854 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1855 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1856 rate); 1857} 1858 1859/* 1860 * Writes to the 8051's internal address space directly instead of indirectly, 1861 * giving access to the special function registers located at addresses 1862 * 0x80-0xFF. 1863 */ 1864static void chipio_8051_write_direct(struct hda_codec *codec, 1865 unsigned int addr, unsigned int data) 1866{ 1867 unsigned int verb; 1868 1869 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1870 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1871} 1872 1873/* 1874 * Enable clocks. 1875 */ 1876static void chipio_enable_clocks(struct hda_codec *codec) 1877{ 1878 struct ca0132_spec *spec = codec->spec; 1879 1880 mutex_lock(&spec->chipio_mutex); 1881 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1882 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1883 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1884 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1885 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1886 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1887 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1888 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1889 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1890 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1891 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1892 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1893 mutex_unlock(&spec->chipio_mutex); 1894} 1895 1896/* 1897 * CA0132 DSP IO stuffs 1898 */ 1899static int dspio_send(struct hda_codec *codec, unsigned int reg, 1900 unsigned int data) 1901{ 1902 int res; 1903 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1904 1905 /* send bits of data specified by reg to dsp */ 1906 do { 1907 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1908 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1909 return res; 1910 msleep(20); 1911 } while (time_before(jiffies, timeout)); 1912 1913 return -EIO; 1914} 1915 1916/* 1917 * Wait for DSP to be ready for commands 1918 */ 1919static void dspio_write_wait(struct hda_codec *codec) 1920{ 1921 int status; 1922 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1923 1924 do { 1925 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1926 VENDOR_DSPIO_STATUS, 0); 1927 if ((status == VENDOR_STATUS_DSPIO_OK) || 1928 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1929 break; 1930 msleep(1); 1931 } while (time_before(jiffies, timeout)); 1932} 1933 1934/* 1935 * Write SCP data to DSP 1936 */ 1937static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1938{ 1939 struct ca0132_spec *spec = codec->spec; 1940 int status; 1941 1942 dspio_write_wait(codec); 1943 1944 mutex_lock(&spec->chipio_mutex); 1945 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1946 scp_data & 0xffff); 1947 if (status < 0) 1948 goto error; 1949 1950 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1951 scp_data >> 16); 1952 if (status < 0) 1953 goto error; 1954 1955 /* OK, now check if the write itself has executed*/ 1956 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1957 VENDOR_DSPIO_STATUS, 0); 1958error: 1959 mutex_unlock(&spec->chipio_mutex); 1960 1961 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1962 -EIO : 0; 1963} 1964 1965/* 1966 * Write multiple SCP data to DSP 1967 */ 1968static int dspio_write_multiple(struct hda_codec *codec, 1969 unsigned int *buffer, unsigned int size) 1970{ 1971 int status = 0; 1972 unsigned int count; 1973 1974 if (buffer == NULL) 1975 return -EINVAL; 1976 1977 count = 0; 1978 while (count < size) { 1979 status = dspio_write(codec, *buffer++); 1980 if (status != 0) 1981 break; 1982 count++; 1983 } 1984 1985 return status; 1986} 1987 1988static int dspio_read(struct hda_codec *codec, unsigned int *data) 1989{ 1990 int status; 1991 1992 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1993 if (status == -EIO) 1994 return status; 1995 1996 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1997 if (status == -EIO || 1998 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1999 return -EIO; 2000 2001 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2002 VENDOR_DSPIO_SCP_READ_DATA, 0); 2003 2004 return 0; 2005} 2006 2007static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2008 unsigned int *buf_size, unsigned int size_count) 2009{ 2010 int status = 0; 2011 unsigned int size = *buf_size; 2012 unsigned int count; 2013 unsigned int skip_count; 2014 unsigned int dummy; 2015 2016 if (buffer == NULL) 2017 return -1; 2018 2019 count = 0; 2020 while (count < size && count < size_count) { 2021 status = dspio_read(codec, buffer++); 2022 if (status != 0) 2023 break; 2024 count++; 2025 } 2026 2027 skip_count = count; 2028 if (status == 0) { 2029 while (skip_count < size) { 2030 status = dspio_read(codec, &dummy); 2031 if (status != 0) 2032 break; 2033 skip_count++; 2034 } 2035 } 2036 *buf_size = count; 2037 2038 return status; 2039} 2040 2041/* 2042 * Construct the SCP header using corresponding fields 2043 */ 2044static inline unsigned int 2045make_scp_header(unsigned int target_id, unsigned int source_id, 2046 unsigned int get_flag, unsigned int req, 2047 unsigned int device_flag, unsigned int resp_flag, 2048 unsigned int error_flag, unsigned int data_size) 2049{ 2050 unsigned int header = 0; 2051 2052 header = (data_size & 0x1f) << 27; 2053 header |= (error_flag & 0x01) << 26; 2054 header |= (resp_flag & 0x01) << 25; 2055 header |= (device_flag & 0x01) << 24; 2056 header |= (req & 0x7f) << 17; 2057 header |= (get_flag & 0x01) << 16; 2058 header |= (source_id & 0xff) << 8; 2059 header |= target_id & 0xff; 2060 2061 return header; 2062} 2063 2064/* 2065 * Extract corresponding fields from SCP header 2066 */ 2067static inline void 2068extract_scp_header(unsigned int header, 2069 unsigned int *target_id, unsigned int *source_id, 2070 unsigned int *get_flag, unsigned int *req, 2071 unsigned int *device_flag, unsigned int *resp_flag, 2072 unsigned int *error_flag, unsigned int *data_size) 2073{ 2074 if (data_size) 2075 *data_size = (header >> 27) & 0x1f; 2076 if (error_flag) 2077 *error_flag = (header >> 26) & 0x01; 2078 if (resp_flag) 2079 *resp_flag = (header >> 25) & 0x01; 2080 if (device_flag) 2081 *device_flag = (header >> 24) & 0x01; 2082 if (req) 2083 *req = (header >> 17) & 0x7f; 2084 if (get_flag) 2085 *get_flag = (header >> 16) & 0x01; 2086 if (source_id) 2087 *source_id = (header >> 8) & 0xff; 2088 if (target_id) 2089 *target_id = header & 0xff; 2090} 2091 2092#define SCP_MAX_DATA_WORDS (16) 2093 2094/* Structure to contain any SCP message */ 2095struct scp_msg { 2096 unsigned int hdr; 2097 unsigned int data[SCP_MAX_DATA_WORDS]; 2098}; 2099 2100static void dspio_clear_response_queue(struct hda_codec *codec) 2101{ 2102 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2103 unsigned int dummy = 0; 2104 int status; 2105 2106 /* clear all from the response queue */ 2107 do { 2108 status = dspio_read(codec, &dummy); 2109 } while (status == 0 && time_before(jiffies, timeout)); 2110} 2111 2112static int dspio_get_response_data(struct hda_codec *codec) 2113{ 2114 struct ca0132_spec *spec = codec->spec; 2115 unsigned int data = 0; 2116 unsigned int count; 2117 2118 if (dspio_read(codec, &data) < 0) 2119 return -EIO; 2120 2121 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2122 spec->scp_resp_header = data; 2123 spec->scp_resp_count = data >> 27; 2124 count = spec->wait_num_data; 2125 dspio_read_multiple(codec, spec->scp_resp_data, 2126 &spec->scp_resp_count, count); 2127 return 0; 2128 } 2129 2130 return -EIO; 2131} 2132 2133/* 2134 * Send SCP message to DSP 2135 */ 2136static int dspio_send_scp_message(struct hda_codec *codec, 2137 unsigned char *send_buf, 2138 unsigned int send_buf_size, 2139 unsigned char *return_buf, 2140 unsigned int return_buf_size, 2141 unsigned int *bytes_returned) 2142{ 2143 struct ca0132_spec *spec = codec->spec; 2144 int status = -1; 2145 unsigned int scp_send_size = 0; 2146 unsigned int total_size; 2147 bool waiting_for_resp = false; 2148 unsigned int header; 2149 struct scp_msg *ret_msg; 2150 unsigned int resp_src_id, resp_target_id; 2151 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2152 2153 if (bytes_returned) 2154 *bytes_returned = 0; 2155 2156 /* get scp header from buffer */ 2157 header = *((unsigned int *)send_buf); 2158 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2159 &device_flag, NULL, NULL, &data_size); 2160 scp_send_size = data_size + 1; 2161 total_size = (scp_send_size * 4); 2162 2163 if (send_buf_size < total_size) 2164 return -EINVAL; 2165 2166 if (get_flag || device_flag) { 2167 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2168 return -EINVAL; 2169 2170 spec->wait_scp_header = *((unsigned int *)send_buf); 2171 2172 /* swap source id with target id */ 2173 resp_target_id = src_id; 2174 resp_src_id = target_id; 2175 spec->wait_scp_header &= 0xffff0000; 2176 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2177 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2178 spec->wait_scp = 1; 2179 waiting_for_resp = true; 2180 } 2181 2182 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2183 scp_send_size); 2184 if (status < 0) { 2185 spec->wait_scp = 0; 2186 return status; 2187 } 2188 2189 if (waiting_for_resp) { 2190 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2191 memset(return_buf, 0, return_buf_size); 2192 do { 2193 msleep(20); 2194 } while (spec->wait_scp && time_before(jiffies, timeout)); 2195 waiting_for_resp = false; 2196 if (!spec->wait_scp) { 2197 ret_msg = (struct scp_msg *)return_buf; 2198 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2199 memcpy(&ret_msg->data, spec->scp_resp_data, 2200 spec->wait_num_data); 2201 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2202 status = 0; 2203 } else { 2204 status = -EIO; 2205 } 2206 spec->wait_scp = 0; 2207 } 2208 2209 return status; 2210} 2211 2212/** 2213 * Prepare and send the SCP message to DSP 2214 * @codec: the HDA codec 2215 * @mod_id: ID of the DSP module to send the command 2216 * @src_id: ID of the source 2217 * @req: ID of request to send to the DSP module 2218 * @dir: SET or GET 2219 * @data: pointer to the data to send with the request, request specific 2220 * @len: length of the data, in bytes 2221 * @reply: point to the buffer to hold data returned for a reply 2222 * @reply_len: length of the reply buffer returned from GET 2223 * 2224 * Returns zero or a negative error code. 2225 */ 2226static int dspio_scp(struct hda_codec *codec, 2227 int mod_id, int src_id, int req, int dir, const void *data, 2228 unsigned int len, void *reply, unsigned int *reply_len) 2229{ 2230 int status = 0; 2231 struct scp_msg scp_send, scp_reply; 2232 unsigned int ret_bytes, send_size, ret_size; 2233 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2234 unsigned int reply_data_size; 2235 2236 memset(&scp_send, 0, sizeof(scp_send)); 2237 memset(&scp_reply, 0, sizeof(scp_reply)); 2238 2239 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2240 return -EINVAL; 2241 2242 if (dir == SCP_GET && reply == NULL) { 2243 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2244 return -EINVAL; 2245 } 2246 2247 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2248 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2249 return -EINVAL; 2250 } 2251 2252 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2253 0, 0, 0, len/sizeof(unsigned int)); 2254 if (data != NULL && len > 0) { 2255 len = min((unsigned int)(sizeof(scp_send.data)), len); 2256 memcpy(scp_send.data, data, len); 2257 } 2258 2259 ret_bytes = 0; 2260 send_size = sizeof(unsigned int) + len; 2261 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2262 send_size, (unsigned char *)&scp_reply, 2263 sizeof(scp_reply), &ret_bytes); 2264 2265 if (status < 0) { 2266 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2267 return status; 2268 } 2269 2270 /* extract send and reply headers members */ 2271 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2272 NULL, NULL, NULL, NULL, NULL); 2273 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2274 &reply_resp_flag, &reply_error_flag, 2275 &reply_data_size); 2276 2277 if (!send_get_flag) 2278 return 0; 2279 2280 if (reply_resp_flag && !reply_error_flag) { 2281 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2282 / sizeof(unsigned int); 2283 2284 if (*reply_len < ret_size*sizeof(unsigned int)) { 2285 codec_dbg(codec, "reply too long for buf\n"); 2286 return -EINVAL; 2287 } else if (ret_size != reply_data_size) { 2288 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2289 return -EINVAL; 2290 } else if (!reply) { 2291 codec_dbg(codec, "NULL reply\n"); 2292 return -EINVAL; 2293 } else { 2294 *reply_len = ret_size*sizeof(unsigned int); 2295 memcpy(reply, scp_reply.data, *reply_len); 2296 } 2297 } else { 2298 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2299 return -EIO; 2300 } 2301 2302 return status; 2303} 2304 2305/* 2306 * Set DSP parameters 2307 */ 2308static int dspio_set_param(struct hda_codec *codec, int mod_id, 2309 int src_id, int req, const void *data, unsigned int len) 2310{ 2311 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2312 NULL); 2313} 2314 2315static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2316 int req, const unsigned int data) 2317{ 2318 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2319 sizeof(unsigned int)); 2320} 2321 2322static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 2323 int req, const unsigned int data) 2324{ 2325 return dspio_set_param(codec, mod_id, 0x00, req, &data, 2326 sizeof(unsigned int)); 2327} 2328 2329/* 2330 * Allocate a DSP DMA channel via an SCP message 2331 */ 2332static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2333{ 2334 int status = 0; 2335 unsigned int size = sizeof(*dma_chan); 2336 2337 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2338 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2339 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2340 dma_chan, &size); 2341 2342 if (status < 0) { 2343 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2344 return status; 2345 } 2346 2347 if ((*dma_chan + 1) == 0) { 2348 codec_dbg(codec, "no free dma channels to allocate\n"); 2349 return -EBUSY; 2350 } 2351 2352 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2353 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2354 2355 return status; 2356} 2357 2358/* 2359 * Free a DSP DMA via an SCP message 2360 */ 2361static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2362{ 2363 int status = 0; 2364 unsigned int dummy = 0; 2365 2366 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2367 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2368 2369 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2370 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2371 sizeof(dma_chan), NULL, &dummy); 2372 2373 if (status < 0) { 2374 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2375 return status; 2376 } 2377 2378 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2379 2380 return status; 2381} 2382 2383/* 2384 * (Re)start the DSP 2385 */ 2386static int dsp_set_run_state(struct hda_codec *codec) 2387{ 2388 unsigned int dbg_ctrl_reg; 2389 unsigned int halt_state; 2390 int err; 2391 2392 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2393 if (err < 0) 2394 return err; 2395 2396 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2397 DSP_DBGCNTL_STATE_LOBIT; 2398 2399 if (halt_state != 0) { 2400 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2401 DSP_DBGCNTL_SS_MASK); 2402 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2403 dbg_ctrl_reg); 2404 if (err < 0) 2405 return err; 2406 2407 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2408 DSP_DBGCNTL_EXEC_MASK; 2409 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2410 dbg_ctrl_reg); 2411 if (err < 0) 2412 return err; 2413 } 2414 2415 return 0; 2416} 2417 2418/* 2419 * Reset the DSP 2420 */ 2421static int dsp_reset(struct hda_codec *codec) 2422{ 2423 unsigned int res; 2424 int retry = 20; 2425 2426 codec_dbg(codec, "dsp_reset\n"); 2427 do { 2428 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2429 retry--; 2430 } while (res == -EIO && retry); 2431 2432 if (!retry) { 2433 codec_dbg(codec, "dsp_reset timeout\n"); 2434 return -EIO; 2435 } 2436 2437 return 0; 2438} 2439 2440/* 2441 * Convert chip address to DSP address 2442 */ 2443static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2444 bool *code, bool *yram) 2445{ 2446 *code = *yram = false; 2447 2448 if (UC_RANGE(chip_addx, 1)) { 2449 *code = true; 2450 return UC_OFF(chip_addx); 2451 } else if (X_RANGE_ALL(chip_addx, 1)) { 2452 return X_OFF(chip_addx); 2453 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2454 *yram = true; 2455 return Y_OFF(chip_addx); 2456 } 2457 2458 return INVALID_CHIP_ADDRESS; 2459} 2460 2461/* 2462 * Check if the DSP DMA is active 2463 */ 2464static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2465{ 2466 unsigned int dma_chnlstart_reg; 2467 2468 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2469 2470 return ((dma_chnlstart_reg & (1 << 2471 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2472} 2473 2474static int dsp_dma_setup_common(struct hda_codec *codec, 2475 unsigned int chip_addx, 2476 unsigned int dma_chan, 2477 unsigned int port_map_mask, 2478 bool ovly) 2479{ 2480 int status = 0; 2481 unsigned int chnl_prop; 2482 unsigned int dsp_addx; 2483 unsigned int active; 2484 bool code, yram; 2485 2486 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2487 2488 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2489 codec_dbg(codec, "dma chan num invalid\n"); 2490 return -EINVAL; 2491 } 2492 2493 if (dsp_is_dma_active(codec, dma_chan)) { 2494 codec_dbg(codec, "dma already active\n"); 2495 return -EBUSY; 2496 } 2497 2498 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2499 2500 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2501 codec_dbg(codec, "invalid chip addr\n"); 2502 return -ENXIO; 2503 } 2504 2505 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2506 active = 0; 2507 2508 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2509 2510 if (ovly) { 2511 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2512 &chnl_prop); 2513 2514 if (status < 0) { 2515 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2516 return status; 2517 } 2518 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2519 } 2520 2521 if (!code) 2522 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2523 else 2524 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2525 2526 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2527 2528 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2529 if (status < 0) { 2530 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2531 return status; 2532 } 2533 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2534 2535 if (ovly) { 2536 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2537 &active); 2538 2539 if (status < 0) { 2540 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2541 return status; 2542 } 2543 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2544 } 2545 2546 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2547 DSPDMAC_ACTIVE_AAR_MASK; 2548 2549 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2550 if (status < 0) { 2551 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2552 return status; 2553 } 2554 2555 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2556 2557 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2558 port_map_mask); 2559 if (status < 0) { 2560 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2561 return status; 2562 } 2563 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2564 2565 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2566 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2567 if (status < 0) { 2568 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2569 return status; 2570 } 2571 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2572 2573 codec_dbg(codec, 2574 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2575 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2576 chip_addx, dsp_addx, dma_chan, 2577 port_map_mask, chnl_prop, active); 2578 2579 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2580 2581 return 0; 2582} 2583 2584/* 2585 * Setup the DSP DMA per-transfer-specific registers 2586 */ 2587static int dsp_dma_setup(struct hda_codec *codec, 2588 unsigned int chip_addx, 2589 unsigned int count, 2590 unsigned int dma_chan) 2591{ 2592 int status = 0; 2593 bool code, yram; 2594 unsigned int dsp_addx; 2595 unsigned int addr_field; 2596 unsigned int incr_field; 2597 unsigned int base_cnt; 2598 unsigned int cur_cnt; 2599 unsigned int dma_cfg = 0; 2600 unsigned int adr_ofs = 0; 2601 unsigned int xfr_cnt = 0; 2602 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2603 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2604 2605 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2606 2607 if (count > max_dma_count) { 2608 codec_dbg(codec, "count too big\n"); 2609 return -EINVAL; 2610 } 2611 2612 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2613 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2614 codec_dbg(codec, "invalid chip addr\n"); 2615 return -ENXIO; 2616 } 2617 2618 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2619 2620 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2621 incr_field = 0; 2622 2623 if (!code) { 2624 addr_field <<= 1; 2625 if (yram) 2626 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2627 2628 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2629 } 2630 2631 dma_cfg = addr_field + incr_field; 2632 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2633 dma_cfg); 2634 if (status < 0) { 2635 codec_dbg(codec, "write DMACFG Reg fail\n"); 2636 return status; 2637 } 2638 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2639 2640 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2641 (code ? 0 : 1)); 2642 2643 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2644 adr_ofs); 2645 if (status < 0) { 2646 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2647 return status; 2648 } 2649 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2650 2651 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2652 2653 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2654 2655 xfr_cnt = base_cnt | cur_cnt; 2656 2657 status = chipio_write(codec, 2658 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2659 if (status < 0) { 2660 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2661 return status; 2662 } 2663 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2664 2665 codec_dbg(codec, 2666 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2667 "ADROFS=0x%x, XFRCNT=0x%x\n", 2668 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2669 2670 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2671 2672 return 0; 2673} 2674 2675/* 2676 * Start the DSP DMA 2677 */ 2678static int dsp_dma_start(struct hda_codec *codec, 2679 unsigned int dma_chan, bool ovly) 2680{ 2681 unsigned int reg = 0; 2682 int status = 0; 2683 2684 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2685 2686 if (ovly) { 2687 status = chipio_read(codec, 2688 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2689 2690 if (status < 0) { 2691 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2692 return status; 2693 } 2694 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2695 2696 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2697 DSPDMAC_CHNLSTART_DIS_MASK); 2698 } 2699 2700 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2701 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2702 if (status < 0) { 2703 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2704 return status; 2705 } 2706 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2707 2708 return status; 2709} 2710 2711/* 2712 * Stop the DSP DMA 2713 */ 2714static int dsp_dma_stop(struct hda_codec *codec, 2715 unsigned int dma_chan, bool ovly) 2716{ 2717 unsigned int reg = 0; 2718 int status = 0; 2719 2720 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2721 2722 if (ovly) { 2723 status = chipio_read(codec, 2724 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2725 2726 if (status < 0) { 2727 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2728 return status; 2729 } 2730 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2731 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2732 DSPDMAC_CHNLSTART_DIS_MASK); 2733 } 2734 2735 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2736 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2737 if (status < 0) { 2738 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2739 return status; 2740 } 2741 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2742 2743 return status; 2744} 2745 2746/** 2747 * Allocate router ports 2748 * 2749 * @codec: the HDA codec 2750 * @num_chans: number of channels in the stream 2751 * @ports_per_channel: number of ports per channel 2752 * @start_device: start device 2753 * @port_map: pointer to the port list to hold the allocated ports 2754 * 2755 * Returns zero or a negative error code. 2756 */ 2757static int dsp_allocate_router_ports(struct hda_codec *codec, 2758 unsigned int num_chans, 2759 unsigned int ports_per_channel, 2760 unsigned int start_device, 2761 unsigned int *port_map) 2762{ 2763 int status = 0; 2764 int res; 2765 u8 val; 2766 2767 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2768 if (status < 0) 2769 return status; 2770 2771 val = start_device << 6; 2772 val |= (ports_per_channel - 1) << 4; 2773 val |= num_chans - 1; 2774 2775 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2776 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2777 val); 2778 2779 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2780 VENDOR_CHIPIO_PORT_ALLOC_SET, 2781 MEM_CONNID_DSP); 2782 2783 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2784 if (status < 0) 2785 return status; 2786 2787 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2788 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2789 2790 *port_map = res; 2791 2792 return (res < 0) ? res : 0; 2793} 2794 2795/* 2796 * Free router ports 2797 */ 2798static int dsp_free_router_ports(struct hda_codec *codec) 2799{ 2800 int status = 0; 2801 2802 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2803 if (status < 0) 2804 return status; 2805 2806 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2807 VENDOR_CHIPIO_PORT_FREE_SET, 2808 MEM_CONNID_DSP); 2809 2810 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2811 2812 return status; 2813} 2814 2815/* 2816 * Allocate DSP ports for the download stream 2817 */ 2818static int dsp_allocate_ports(struct hda_codec *codec, 2819 unsigned int num_chans, 2820 unsigned int rate_multi, unsigned int *port_map) 2821{ 2822 int status; 2823 2824 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2825 2826 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2827 codec_dbg(codec, "bad rate multiple\n"); 2828 return -EINVAL; 2829 } 2830 2831 status = dsp_allocate_router_ports(codec, num_chans, 2832 rate_multi, 0, port_map); 2833 2834 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2835 2836 return status; 2837} 2838 2839static int dsp_allocate_ports_format(struct hda_codec *codec, 2840 const unsigned short fmt, 2841 unsigned int *port_map) 2842{ 2843 int status; 2844 unsigned int num_chans; 2845 2846 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2847 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2848 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2849 2850 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2851 codec_dbg(codec, "bad rate multiple\n"); 2852 return -EINVAL; 2853 } 2854 2855 num_chans = get_hdafmt_chs(fmt) + 1; 2856 2857 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2858 2859 return status; 2860} 2861 2862/* 2863 * free DSP ports 2864 */ 2865static int dsp_free_ports(struct hda_codec *codec) 2866{ 2867 int status; 2868 2869 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2870 2871 status = dsp_free_router_ports(codec); 2872 if (status < 0) { 2873 codec_dbg(codec, "free router ports fail\n"); 2874 return status; 2875 } 2876 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2877 2878 return status; 2879} 2880 2881/* 2882 * HDA DMA engine stuffs for DSP code download 2883 */ 2884struct dma_engine { 2885 struct hda_codec *codec; 2886 unsigned short m_converter_format; 2887 struct snd_dma_buffer *dmab; 2888 unsigned int buf_size; 2889}; 2890 2891 2892enum dma_state { 2893 DMA_STATE_STOP = 0, 2894 DMA_STATE_RUN = 1 2895}; 2896 2897static int dma_convert_to_hda_format(struct hda_codec *codec, 2898 unsigned int sample_rate, 2899 unsigned short channels, 2900 unsigned short *hda_format) 2901{ 2902 unsigned int format_val; 2903 2904 format_val = snd_hdac_calc_stream_format(sample_rate, 2905 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2906 2907 if (hda_format) 2908 *hda_format = (unsigned short)format_val; 2909 2910 return 0; 2911} 2912 2913/* 2914 * Reset DMA for DSP download 2915 */ 2916static int dma_reset(struct dma_engine *dma) 2917{ 2918 struct hda_codec *codec = dma->codec; 2919 struct ca0132_spec *spec = codec->spec; 2920 int status; 2921 2922 if (dma->dmab->area) 2923 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2924 2925 status = snd_hda_codec_load_dsp_prepare(codec, 2926 dma->m_converter_format, 2927 dma->buf_size, 2928 dma->dmab); 2929 if (status < 0) 2930 return status; 2931 spec->dsp_stream_id = status; 2932 return 0; 2933} 2934 2935static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2936{ 2937 bool cmd; 2938 2939 switch (state) { 2940 case DMA_STATE_STOP: 2941 cmd = false; 2942 break; 2943 case DMA_STATE_RUN: 2944 cmd = true; 2945 break; 2946 default: 2947 return 0; 2948 } 2949 2950 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2951 return 0; 2952} 2953 2954static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2955{ 2956 return dma->dmab->bytes; 2957} 2958 2959static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2960{ 2961 return dma->dmab->area; 2962} 2963 2964static int dma_xfer(struct dma_engine *dma, 2965 const unsigned int *data, 2966 unsigned int count) 2967{ 2968 memcpy(dma->dmab->area, data, count); 2969 return 0; 2970} 2971 2972static void dma_get_converter_format( 2973 struct dma_engine *dma, 2974 unsigned short *format) 2975{ 2976 if (format) 2977 *format = dma->m_converter_format; 2978} 2979 2980static unsigned int dma_get_stream_id(struct dma_engine *dma) 2981{ 2982 struct ca0132_spec *spec = dma->codec->spec; 2983 2984 return spec->dsp_stream_id; 2985} 2986 2987struct dsp_image_seg { 2988 u32 magic; 2989 u32 chip_addr; 2990 u32 count; 2991 u32 data[]; 2992}; 2993 2994static const u32 g_magic_value = 0x4c46584d; 2995static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2996 2997static bool is_valid(const struct dsp_image_seg *p) 2998{ 2999 return p->magic == g_magic_value; 3000} 3001 3002static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3003{ 3004 return g_chip_addr_magic_value == p->chip_addr; 3005} 3006 3007static bool is_last(const struct dsp_image_seg *p) 3008{ 3009 return p->count == 0; 3010} 3011 3012static size_t dsp_sizeof(const struct dsp_image_seg *p) 3013{ 3014 return struct_size(p, data, p->count); 3015} 3016 3017static const struct dsp_image_seg *get_next_seg_ptr( 3018 const struct dsp_image_seg *p) 3019{ 3020 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3021} 3022 3023/* 3024 * CA0132 chip DSP transfer stuffs. For DSP download. 3025 */ 3026#define INVALID_DMA_CHANNEL (~0U) 3027 3028/* 3029 * Program a list of address/data pairs via the ChipIO widget. 3030 * The segment data is in the format of successive pairs of words. 3031 * These are repeated as indicated by the segment's count field. 3032 */ 3033static int dspxfr_hci_write(struct hda_codec *codec, 3034 const struct dsp_image_seg *fls) 3035{ 3036 int status; 3037 const u32 *data; 3038 unsigned int count; 3039 3040 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3041 codec_dbg(codec, "hci_write invalid params\n"); 3042 return -EINVAL; 3043 } 3044 3045 count = fls->count; 3046 data = (u32 *)(fls->data); 3047 while (count >= 2) { 3048 status = chipio_write(codec, data[0], data[1]); 3049 if (status < 0) { 3050 codec_dbg(codec, "hci_write chipio failed\n"); 3051 return status; 3052 } 3053 count -= 2; 3054 data += 2; 3055 } 3056 return 0; 3057} 3058 3059/** 3060 * Write a block of data into DSP code or data RAM using pre-allocated 3061 * DMA engine. 3062 * 3063 * @codec: the HDA codec 3064 * @fls: pointer to a fast load image 3065 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3066 * no relocation 3067 * @dma_engine: pointer to DMA engine to be used for DSP download 3068 * @dma_chan: The number of DMA channels used for DSP download 3069 * @port_map_mask: port mapping 3070 * @ovly: TRUE if overlay format is required 3071 * 3072 * Returns zero or a negative error code. 3073 */ 3074static int dspxfr_one_seg(struct hda_codec *codec, 3075 const struct dsp_image_seg *fls, 3076 unsigned int reloc, 3077 struct dma_engine *dma_engine, 3078 unsigned int dma_chan, 3079 unsigned int port_map_mask, 3080 bool ovly) 3081{ 3082 int status = 0; 3083 bool comm_dma_setup_done = false; 3084 const unsigned int *data; 3085 unsigned int chip_addx; 3086 unsigned int words_to_write; 3087 unsigned int buffer_size_words; 3088 unsigned char *buffer_addx; 3089 unsigned short hda_format; 3090 unsigned int sample_rate_div; 3091 unsigned int sample_rate_mul; 3092 unsigned int num_chans; 3093 unsigned int hda_frame_size_words; 3094 unsigned int remainder_words; 3095 const u32 *data_remainder; 3096 u32 chip_addx_remainder; 3097 unsigned int run_size_words; 3098 const struct dsp_image_seg *hci_write = NULL; 3099 unsigned long timeout; 3100 bool dma_active; 3101 3102 if (fls == NULL) 3103 return -EINVAL; 3104 if (is_hci_prog_list_seg(fls)) { 3105 hci_write = fls; 3106 fls = get_next_seg_ptr(fls); 3107 } 3108 3109 if (hci_write && (!fls || is_last(fls))) { 3110 codec_dbg(codec, "hci_write\n"); 3111 return dspxfr_hci_write(codec, hci_write); 3112 } 3113 3114 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3115 codec_dbg(codec, "Invalid Params\n"); 3116 return -EINVAL; 3117 } 3118 3119 data = fls->data; 3120 chip_addx = fls->chip_addr; 3121 words_to_write = fls->count; 3122 3123 if (!words_to_write) 3124 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3125 if (reloc) 3126 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3127 3128 if (!UC_RANGE(chip_addx, words_to_write) && 3129 !X_RANGE_ALL(chip_addx, words_to_write) && 3130 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3131 codec_dbg(codec, "Invalid chip_addx Params\n"); 3132 return -EINVAL; 3133 } 3134 3135 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3136 sizeof(u32); 3137 3138 buffer_addx = dma_get_buffer_addr(dma_engine); 3139 3140 if (buffer_addx == NULL) { 3141 codec_dbg(codec, "dma_engine buffer NULL\n"); 3142 return -EINVAL; 3143 } 3144 3145 dma_get_converter_format(dma_engine, &hda_format); 3146 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3147 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3148 num_chans = get_hdafmt_chs(hda_format) + 1; 3149 3150 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3151 (num_chans * sample_rate_mul / sample_rate_div)); 3152 3153 if (hda_frame_size_words == 0) { 3154 codec_dbg(codec, "frmsz zero\n"); 3155 return -EINVAL; 3156 } 3157 3158 buffer_size_words = min(buffer_size_words, 3159 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3160 65536 : 32768)); 3161 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3162 codec_dbg(codec, 3163 "chpadr=0x%08x frmsz=%u nchan=%u " 3164 "rate_mul=%u div=%u bufsz=%u\n", 3165 chip_addx, hda_frame_size_words, num_chans, 3166 sample_rate_mul, sample_rate_div, buffer_size_words); 3167 3168 if (buffer_size_words < hda_frame_size_words) { 3169 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3170 return -EINVAL; 3171 } 3172 3173 remainder_words = words_to_write % hda_frame_size_words; 3174 data_remainder = data; 3175 chip_addx_remainder = chip_addx; 3176 3177 data += remainder_words; 3178 chip_addx += remainder_words*sizeof(u32); 3179 words_to_write -= remainder_words; 3180 3181 while (words_to_write != 0) { 3182 run_size_words = min(buffer_size_words, words_to_write); 3183 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3184 words_to_write, run_size_words, remainder_words); 3185 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3186 if (!comm_dma_setup_done) { 3187 status = dsp_dma_stop(codec, dma_chan, ovly); 3188 if (status < 0) 3189 return status; 3190 status = dsp_dma_setup_common(codec, chip_addx, 3191 dma_chan, port_map_mask, ovly); 3192 if (status < 0) 3193 return status; 3194 comm_dma_setup_done = true; 3195 } 3196 3197 status = dsp_dma_setup(codec, chip_addx, 3198 run_size_words, dma_chan); 3199 if (status < 0) 3200 return status; 3201 status = dsp_dma_start(codec, dma_chan, ovly); 3202 if (status < 0) 3203 return status; 3204 if (!dsp_is_dma_active(codec, dma_chan)) { 3205 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3206 return -EIO; 3207 } 3208 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3209 if (status < 0) 3210 return status; 3211 if (remainder_words != 0) { 3212 status = chipio_write_multiple(codec, 3213 chip_addx_remainder, 3214 data_remainder, 3215 remainder_words); 3216 if (status < 0) 3217 return status; 3218 remainder_words = 0; 3219 } 3220 if (hci_write) { 3221 status = dspxfr_hci_write(codec, hci_write); 3222 if (status < 0) 3223 return status; 3224 hci_write = NULL; 3225 } 3226 3227 timeout = jiffies + msecs_to_jiffies(2000); 3228 do { 3229 dma_active = dsp_is_dma_active(codec, dma_chan); 3230 if (!dma_active) 3231 break; 3232 msleep(20); 3233 } while (time_before(jiffies, timeout)); 3234 if (dma_active) 3235 break; 3236 3237 codec_dbg(codec, "+++++ DMA complete\n"); 3238 dma_set_state(dma_engine, DMA_STATE_STOP); 3239 status = dma_reset(dma_engine); 3240 3241 if (status < 0) 3242 return status; 3243 3244 data += run_size_words; 3245 chip_addx += run_size_words*sizeof(u32); 3246 words_to_write -= run_size_words; 3247 } 3248 3249 if (remainder_words != 0) { 3250 status = chipio_write_multiple(codec, chip_addx_remainder, 3251 data_remainder, remainder_words); 3252 } 3253 3254 return status; 3255} 3256 3257/** 3258 * Write the entire DSP image of a DSP code/data overlay to DSP memories 3259 * 3260 * @codec: the HDA codec 3261 * @fls_data: pointer to a fast load image 3262 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3263 * no relocation 3264 * @sample_rate: sampling rate of the stream used for DSP download 3265 * @channels: channels of the stream used for DSP download 3266 * @ovly: TRUE if overlay format is required 3267 * 3268 * Returns zero or a negative error code. 3269 */ 3270static int dspxfr_image(struct hda_codec *codec, 3271 const struct dsp_image_seg *fls_data, 3272 unsigned int reloc, 3273 unsigned int sample_rate, 3274 unsigned short channels, 3275 bool ovly) 3276{ 3277 struct ca0132_spec *spec = codec->spec; 3278 int status; 3279 unsigned short hda_format = 0; 3280 unsigned int response; 3281 unsigned char stream_id = 0; 3282 struct dma_engine *dma_engine; 3283 unsigned int dma_chan; 3284 unsigned int port_map_mask; 3285 3286 if (fls_data == NULL) 3287 return -EINVAL; 3288 3289 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3290 if (!dma_engine) 3291 return -ENOMEM; 3292 3293 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3294 if (!dma_engine->dmab) { 3295 kfree(dma_engine); 3296 return -ENOMEM; 3297 } 3298 3299 dma_engine->codec = codec; 3300 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3301 dma_engine->m_converter_format = hda_format; 3302 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3303 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3304 3305 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3306 3307 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3308 hda_format, &response); 3309 3310 if (status < 0) { 3311 codec_dbg(codec, "set converter format fail\n"); 3312 goto exit; 3313 } 3314 3315 status = snd_hda_codec_load_dsp_prepare(codec, 3316 dma_engine->m_converter_format, 3317 dma_engine->buf_size, 3318 dma_engine->dmab); 3319 if (status < 0) 3320 goto exit; 3321 spec->dsp_stream_id = status; 3322 3323 if (ovly) { 3324 status = dspio_alloc_dma_chan(codec, &dma_chan); 3325 if (status < 0) { 3326 codec_dbg(codec, "alloc dmachan fail\n"); 3327 dma_chan = INVALID_DMA_CHANNEL; 3328 goto exit; 3329 } 3330 } 3331 3332 port_map_mask = 0; 3333 status = dsp_allocate_ports_format(codec, hda_format, 3334 &port_map_mask); 3335 if (status < 0) { 3336 codec_dbg(codec, "alloc ports fail\n"); 3337 goto exit; 3338 } 3339 3340 stream_id = dma_get_stream_id(dma_engine); 3341 status = codec_set_converter_stream_channel(codec, 3342 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3343 if (status < 0) { 3344 codec_dbg(codec, "set stream chan fail\n"); 3345 goto exit; 3346 } 3347 3348 while ((fls_data != NULL) && !is_last(fls_data)) { 3349 if (!is_valid(fls_data)) { 3350 codec_dbg(codec, "FLS check fail\n"); 3351 status = -EINVAL; 3352 goto exit; 3353 } 3354 status = dspxfr_one_seg(codec, fls_data, reloc, 3355 dma_engine, dma_chan, 3356 port_map_mask, ovly); 3357 if (status < 0) 3358 break; 3359 3360 if (is_hci_prog_list_seg(fls_data)) 3361 fls_data = get_next_seg_ptr(fls_data); 3362 3363 if ((fls_data != NULL) && !is_last(fls_data)) 3364 fls_data = get_next_seg_ptr(fls_data); 3365 } 3366 3367 if (port_map_mask != 0) 3368 status = dsp_free_ports(codec); 3369 3370 if (status < 0) 3371 goto exit; 3372 3373 status = codec_set_converter_stream_channel(codec, 3374 WIDGET_CHIP_CTRL, 0, 0, &response); 3375 3376exit: 3377 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3378 dspio_free_dma_chan(codec, dma_chan); 3379 3380 if (dma_engine->dmab->area) 3381 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3382 kfree(dma_engine->dmab); 3383 kfree(dma_engine); 3384 3385 return status; 3386} 3387 3388/* 3389 * CA0132 DSP download stuffs. 3390 */ 3391static void dspload_post_setup(struct hda_codec *codec) 3392{ 3393 struct ca0132_spec *spec = codec->spec; 3394 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3395 if (!ca0132_use_alt_functions(spec)) { 3396 /*set DSP speaker to 2.0 configuration*/ 3397 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3398 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3399 3400 /*update write pointer*/ 3401 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3402 } 3403} 3404 3405/** 3406 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3407 * 3408 * @codec: the HDA codec 3409 * @fls: pointer to a fast load image 3410 * @ovly: TRUE if overlay format is required 3411 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3412 * no relocation 3413 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3414 * @router_chans: number of audio router channels to be allocated (0 means use 3415 * internal defaults; max is 32) 3416 * 3417 * Download DSP from a DSP Image Fast Load structure. This structure is a 3418 * linear, non-constant sized element array of structures, each of which 3419 * contain the count of the data to be loaded, the data itself, and the 3420 * corresponding starting chip address of the starting data location. 3421 * Returns zero or a negative error code. 3422 */ 3423static int dspload_image(struct hda_codec *codec, 3424 const struct dsp_image_seg *fls, 3425 bool ovly, 3426 unsigned int reloc, 3427 bool autostart, 3428 int router_chans) 3429{ 3430 int status = 0; 3431 unsigned int sample_rate; 3432 unsigned short channels; 3433 3434 codec_dbg(codec, "---- dspload_image begin ------\n"); 3435 if (router_chans == 0) { 3436 if (!ovly) 3437 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3438 else 3439 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3440 } 3441 3442 sample_rate = 48000; 3443 channels = (unsigned short)router_chans; 3444 3445 while (channels > 16) { 3446 sample_rate *= 2; 3447 channels /= 2; 3448 } 3449 3450 do { 3451 codec_dbg(codec, "Ready to program DMA\n"); 3452 if (!ovly) 3453 status = dsp_reset(codec); 3454 3455 if (status < 0) 3456 break; 3457 3458 codec_dbg(codec, "dsp_reset() complete\n"); 3459 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3460 ovly); 3461 3462 if (status < 0) 3463 break; 3464 3465 codec_dbg(codec, "dspxfr_image() complete\n"); 3466 if (autostart && !ovly) { 3467 dspload_post_setup(codec); 3468 status = dsp_set_run_state(codec); 3469 } 3470 3471 codec_dbg(codec, "LOAD FINISHED\n"); 3472 } while (0); 3473 3474 return status; 3475} 3476 3477#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3478static bool dspload_is_loaded(struct hda_codec *codec) 3479{ 3480 unsigned int data = 0; 3481 int status = 0; 3482 3483 status = chipio_read(codec, 0x40004, &data); 3484 if ((status < 0) || (data != 1)) 3485 return false; 3486 3487 return true; 3488} 3489#else 3490#define dspload_is_loaded(codec) false 3491#endif 3492 3493static bool dspload_wait_loaded(struct hda_codec *codec) 3494{ 3495 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3496 3497 do { 3498 if (dspload_is_loaded(codec)) { 3499 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3500 return true; 3501 } 3502 msleep(20); 3503 } while (time_before(jiffies, timeout)); 3504 3505 codec_err(codec, "ca0132 failed to download DSP\n"); 3506 return false; 3507} 3508 3509/* 3510 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3511 * based cards, and has a second mmio region, region2, that's used for special 3512 * commands. 3513 */ 3514 3515/* 3516 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3517 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3518 * The first eight bits are just the number of the pin. So far, I've only seen 3519 * this number go to 7. 3520 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3521 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3522 * then off to send that bit. 3523 */ 3524static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3525 bool enable) 3526{ 3527 struct ca0132_spec *spec = codec->spec; 3528 unsigned short gpio_data; 3529 3530 gpio_data = gpio_pin & 0xF; 3531 gpio_data |= ((enable << 8) & 0x100); 3532 3533 writew(gpio_data, spec->mem_base + 0x320); 3534} 3535 3536/* 3537 * Special pci region2 commands that are only used by the AE-5. They follow 3538 * a set format, and require reads at certain points to seemingly 'clear' 3539 * the response data. My first tests didn't do these reads, and would cause 3540 * the card to get locked up until the memory was read. These commands 3541 * seem to work with three distinct values that I've taken to calling group, 3542 * target-id, and value. 3543 */ 3544static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3545 unsigned int target, unsigned int value) 3546{ 3547 struct ca0132_spec *spec = codec->spec; 3548 unsigned int write_val; 3549 3550 writel(0x0000007e, spec->mem_base + 0x210); 3551 readl(spec->mem_base + 0x210); 3552 writel(0x0000005a, spec->mem_base + 0x210); 3553 readl(spec->mem_base + 0x210); 3554 readl(spec->mem_base + 0x210); 3555 3556 writel(0x00800005, spec->mem_base + 0x20c); 3557 writel(group, spec->mem_base + 0x804); 3558 3559 writel(0x00800005, spec->mem_base + 0x20c); 3560 write_val = (target & 0xff); 3561 write_val |= (value << 8); 3562 3563 3564 writel(write_val, spec->mem_base + 0x204); 3565 /* 3566 * Need delay here or else it goes too fast and works inconsistently. 3567 */ 3568 msleep(20); 3569 3570 readl(spec->mem_base + 0x860); 3571 readl(spec->mem_base + 0x854); 3572 readl(spec->mem_base + 0x840); 3573 3574 writel(0x00800004, spec->mem_base + 0x20c); 3575 writel(0x00000000, spec->mem_base + 0x210); 3576 readl(spec->mem_base + 0x210); 3577 readl(spec->mem_base + 0x210); 3578} 3579 3580/* 3581 * This second type of command is used for setting the sound filter type. 3582 */ 3583static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3584 unsigned int group, unsigned int target, unsigned int value) 3585{ 3586 struct ca0132_spec *spec = codec->spec; 3587 unsigned int write_val; 3588 3589 writel(0x0000007e, spec->mem_base + 0x210); 3590 readl(spec->mem_base + 0x210); 3591 writel(0x0000005a, spec->mem_base + 0x210); 3592 readl(spec->mem_base + 0x210); 3593 readl(spec->mem_base + 0x210); 3594 3595 writel(0x00800003, spec->mem_base + 0x20c); 3596 writel(group, spec->mem_base + 0x804); 3597 3598 writel(0x00800005, spec->mem_base + 0x20c); 3599 write_val = (target & 0xff); 3600 write_val |= (value << 8); 3601 3602 3603 writel(write_val, spec->mem_base + 0x204); 3604 msleep(20); 3605 readl(spec->mem_base + 0x860); 3606 readl(spec->mem_base + 0x854); 3607 readl(spec->mem_base + 0x840); 3608 3609 writel(0x00800004, spec->mem_base + 0x20c); 3610 writel(0x00000000, spec->mem_base + 0x210); 3611 readl(spec->mem_base + 0x210); 3612 readl(spec->mem_base + 0x210); 3613} 3614 3615/* 3616 * Setup GPIO for the other variants of Core3D. 3617 */ 3618 3619/* 3620 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3621 * the card shows as having no GPIO pins. 3622 */ 3623static void ca0132_gpio_init(struct hda_codec *codec) 3624{ 3625 struct ca0132_spec *spec = codec->spec; 3626 3627 switch (ca0132_quirk(spec)) { 3628 case QUIRK_SBZ: 3629 case QUIRK_AE5: 3630 case QUIRK_AE7: 3631 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3632 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3633 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3634 break; 3635 case QUIRK_R3DI: 3636 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3637 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3638 break; 3639 default: 3640 break; 3641 } 3642 3643} 3644 3645/* Sets the GPIO for audio output. */ 3646static void ca0132_gpio_setup(struct hda_codec *codec) 3647{ 3648 struct ca0132_spec *spec = codec->spec; 3649 3650 switch (ca0132_quirk(spec)) { 3651 case QUIRK_SBZ: 3652 snd_hda_codec_write(codec, 0x01, 0, 3653 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3654 snd_hda_codec_write(codec, 0x01, 0, 3655 AC_VERB_SET_GPIO_MASK, 0x07); 3656 snd_hda_codec_write(codec, 0x01, 0, 3657 AC_VERB_SET_GPIO_DATA, 0x04); 3658 snd_hda_codec_write(codec, 0x01, 0, 3659 AC_VERB_SET_GPIO_DATA, 0x06); 3660 break; 3661 case QUIRK_R3DI: 3662 snd_hda_codec_write(codec, 0x01, 0, 3663 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3664 snd_hda_codec_write(codec, 0x01, 0, 3665 AC_VERB_SET_GPIO_MASK, 0x1F); 3666 snd_hda_codec_write(codec, 0x01, 0, 3667 AC_VERB_SET_GPIO_DATA, 0x0C); 3668 break; 3669 default: 3670 break; 3671 } 3672} 3673 3674/* 3675 * GPIO control functions for the Recon3D integrated. 3676 */ 3677 3678enum r3di_gpio_bit { 3679 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3680 R3DI_MIC_SELECT_BIT = 1, 3681 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3682 R3DI_OUT_SELECT_BIT = 2, 3683 /* 3684 * I dunno what this actually does, but it stays on until the dsp 3685 * is downloaded. 3686 */ 3687 R3DI_GPIO_DSP_DOWNLOADING = 3, 3688 /* 3689 * Same as above, no clue what it does, but it comes on after the dsp 3690 * is downloaded. 3691 */ 3692 R3DI_GPIO_DSP_DOWNLOADED = 4 3693}; 3694 3695enum r3di_mic_select { 3696 /* Set GPIO bit 1 to 0 for rear mic */ 3697 R3DI_REAR_MIC = 0, 3698 /* Set GPIO bit 1 to 1 for front microphone*/ 3699 R3DI_FRONT_MIC = 1 3700}; 3701 3702enum r3di_out_select { 3703 /* Set GPIO bit 2 to 0 for headphone */ 3704 R3DI_HEADPHONE_OUT = 0, 3705 /* Set GPIO bit 2 to 1 for speaker */ 3706 R3DI_LINE_OUT = 1 3707}; 3708enum r3di_dsp_status { 3709 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3710 R3DI_DSP_DOWNLOADING = 0, 3711 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3712 R3DI_DSP_DOWNLOADED = 1 3713}; 3714 3715 3716static void r3di_gpio_mic_set(struct hda_codec *codec, 3717 enum r3di_mic_select cur_mic) 3718{ 3719 unsigned int cur_gpio; 3720 3721 /* Get the current GPIO Data setup */ 3722 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3723 3724 switch (cur_mic) { 3725 case R3DI_REAR_MIC: 3726 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3727 break; 3728 case R3DI_FRONT_MIC: 3729 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3730 break; 3731 } 3732 snd_hda_codec_write(codec, codec->core.afg, 0, 3733 AC_VERB_SET_GPIO_DATA, cur_gpio); 3734} 3735 3736static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3737 enum r3di_dsp_status dsp_status) 3738{ 3739 unsigned int cur_gpio; 3740 3741 /* Get the current GPIO Data setup */ 3742 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3743 3744 switch (dsp_status) { 3745 case R3DI_DSP_DOWNLOADING: 3746 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3747 snd_hda_codec_write(codec, codec->core.afg, 0, 3748 AC_VERB_SET_GPIO_DATA, cur_gpio); 3749 break; 3750 case R3DI_DSP_DOWNLOADED: 3751 /* Set DOWNLOADING bit to 0. */ 3752 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3753 3754 snd_hda_codec_write(codec, codec->core.afg, 0, 3755 AC_VERB_SET_GPIO_DATA, cur_gpio); 3756 3757 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3758 break; 3759 } 3760 3761 snd_hda_codec_write(codec, codec->core.afg, 0, 3762 AC_VERB_SET_GPIO_DATA, cur_gpio); 3763} 3764 3765/* 3766 * PCM callbacks 3767 */ 3768static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3769 struct hda_codec *codec, 3770 unsigned int stream_tag, 3771 unsigned int format, 3772 struct snd_pcm_substream *substream) 3773{ 3774 struct ca0132_spec *spec = codec->spec; 3775 3776 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3777 3778 return 0; 3779} 3780 3781static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3782 struct hda_codec *codec, 3783 struct snd_pcm_substream *substream) 3784{ 3785 struct ca0132_spec *spec = codec->spec; 3786 3787 if (spec->dsp_state == DSP_DOWNLOADING) 3788 return 0; 3789 3790 /*If Playback effects are on, allow stream some time to flush 3791 *effects tail*/ 3792 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3793 msleep(50); 3794 3795 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3796 3797 return 0; 3798} 3799 3800static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3801 struct hda_codec *codec, 3802 struct snd_pcm_substream *substream) 3803{ 3804 struct ca0132_spec *spec = codec->spec; 3805 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3806 struct snd_pcm_runtime *runtime = substream->runtime; 3807 3808 if (spec->dsp_state != DSP_DOWNLOADED) 3809 return 0; 3810 3811 /* Add latency if playback enhancement and either effect is enabled. */ 3812 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3813 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3814 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3815 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3816 } 3817 3818 /* Applying Speaker EQ adds latency as well. */ 3819 if (spec->cur_out_type == SPEAKER_OUT) 3820 latency += DSP_SPEAKER_OUT_LATENCY; 3821 3822 return (latency * runtime->rate) / 1000; 3823} 3824 3825/* 3826 * Digital out 3827 */ 3828static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3829 struct hda_codec *codec, 3830 struct snd_pcm_substream *substream) 3831{ 3832 struct ca0132_spec *spec = codec->spec; 3833 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3834} 3835 3836static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3837 struct hda_codec *codec, 3838 unsigned int stream_tag, 3839 unsigned int format, 3840 struct snd_pcm_substream *substream) 3841{ 3842 struct ca0132_spec *spec = codec->spec; 3843 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3844 stream_tag, format, substream); 3845} 3846 3847static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3848 struct hda_codec *codec, 3849 struct snd_pcm_substream *substream) 3850{ 3851 struct ca0132_spec *spec = codec->spec; 3852 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3853} 3854 3855static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3856 struct hda_codec *codec, 3857 struct snd_pcm_substream *substream) 3858{ 3859 struct ca0132_spec *spec = codec->spec; 3860 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3861} 3862 3863/* 3864 * Analog capture 3865 */ 3866static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3867 struct hda_codec *codec, 3868 unsigned int stream_tag, 3869 unsigned int format, 3870 struct snd_pcm_substream *substream) 3871{ 3872 snd_hda_codec_setup_stream(codec, hinfo->nid, 3873 stream_tag, 0, format); 3874 3875 return 0; 3876} 3877 3878static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3879 struct hda_codec *codec, 3880 struct snd_pcm_substream *substream) 3881{ 3882 struct ca0132_spec *spec = codec->spec; 3883 3884 if (spec->dsp_state == DSP_DOWNLOADING) 3885 return 0; 3886 3887 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3888 return 0; 3889} 3890 3891static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3892 struct hda_codec *codec, 3893 struct snd_pcm_substream *substream) 3894{ 3895 struct ca0132_spec *spec = codec->spec; 3896 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3897 struct snd_pcm_runtime *runtime = substream->runtime; 3898 3899 if (spec->dsp_state != DSP_DOWNLOADED) 3900 return 0; 3901 3902 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3903 latency += DSP_CRYSTAL_VOICE_LATENCY; 3904 3905 return (latency * runtime->rate) / 1000; 3906} 3907 3908/* 3909 * Controls stuffs. 3910 */ 3911 3912/* 3913 * Mixer controls helpers. 3914 */ 3915#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3916 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3917 .name = xname, \ 3918 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3919 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3920 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3921 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3922 .info = ca0132_volume_info, \ 3923 .get = ca0132_volume_get, \ 3924 .put = ca0132_volume_put, \ 3925 .tlv = { .c = ca0132_volume_tlv }, \ 3926 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3927 3928/* 3929 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3930 * volume put, which is used for setting the DSP volume. This was done because 3931 * the ca0132 functions were taking too much time and causing lag. 3932 */ 3933#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3934 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3935 .name = xname, \ 3936 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3937 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3938 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3939 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3940 .info = snd_hda_mixer_amp_volume_info, \ 3941 .get = snd_hda_mixer_amp_volume_get, \ 3942 .put = ca0132_alt_volume_put, \ 3943 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3944 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3945 3946#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3947 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3948 .name = xname, \ 3949 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3950 .info = snd_hda_mixer_amp_switch_info, \ 3951 .get = ca0132_switch_get, \ 3952 .put = ca0132_switch_put, \ 3953 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3954 3955/* stereo */ 3956#define CA0132_CODEC_VOL(xname, nid, dir) \ 3957 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3958#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3959 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3960#define CA0132_CODEC_MUTE(xname, nid, dir) \ 3961 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3962 3963/* lookup tables */ 3964/* 3965 * Lookup table with decibel values for the DSP. When volume is changed in 3966 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3967 * these values have decimal points, probably because the Windows driver 3968 * actually uses floating point. We can't here, so I made a lookup table of 3969 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3970 * DAC's, and 9 is the maximum. 3971 */ 3972static const unsigned int float_vol_db_lookup[] = { 39730xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 39740xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 39750xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 39760xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 39770xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 39780xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 39790xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 39800xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 39810xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 39820xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 39830xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 39840xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 39850xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 39860xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 39870xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 39880x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 39890x40C00000, 0x40E00000, 0x41000000, 0x41100000 3990}; 3991 3992/* 3993 * This table counts from float 0 to 1 in increments of .01, which is 3994 * useful for a few different sliders. 3995 */ 3996static const unsigned int float_zero_to_one_lookup[] = { 39970x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 39980x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 39990x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 40000x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 40010x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 40020x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 40030x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 40040x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 40050x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 40060x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 40070x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 40080x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 40090x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 40100x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 40110x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 40120x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 40130x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4014}; 4015 4016/* 4017 * This table counts from float 10 to 1000, which is the range of the x-bass 4018 * crossover slider in Windows. 4019 */ 4020static const unsigned int float_xbass_xover_lookup[] = { 40210x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 40220x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 40230x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 40240x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 40250x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 40260x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 40270x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 40280x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 40290x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 40300x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 40310x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 40320x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 40330x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 40340x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 40350x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 40360x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 40370x44728000, 0x44750000, 0x44778000, 0x447A0000 4038}; 4039 4040/* The following are for tuning of products */ 4041#ifdef ENABLE_TUNING_CONTROLS 4042 4043static const unsigned int voice_focus_vals_lookup[] = { 40440x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 40450x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 40460x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 40470x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 40480x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 40490x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 40500x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 40510x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 40520x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 40530x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 40540x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 40550x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 40560x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 40570x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 40580x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 40590x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 40600x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 40610x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 40620x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 40630x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 40640x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 40650x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 40660x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 40670x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 40680x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 40690x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 40700x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4071}; 4072 4073static const unsigned int mic_svm_vals_lookup[] = { 40740x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 40750x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 40760x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 40770x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 40780x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 40790x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 40800x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 40810x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 40820x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 40830x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 40840x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 40850x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 40860x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 40870x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 40880x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 40890x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 40900x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4091}; 4092 4093static const unsigned int equalizer_vals_lookup[] = { 40940xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 40950xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 40960xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 40970xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 40980x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 40990x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 41000x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 41010x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 41020x41C00000 4103}; 4104 4105static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4106 const unsigned int *lookup, int idx) 4107{ 4108 int i = 0; 4109 4110 for (i = 0; i < TUNING_CTLS_COUNT; i++) 4111 if (nid == ca0132_tuning_ctls[i].nid) 4112 goto found; 4113 4114 return -EINVAL; 4115found: 4116 snd_hda_power_up(codec); 4117 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4118 ca0132_tuning_ctls[i].req, 4119 &(lookup[idx]), sizeof(unsigned int)); 4120 snd_hda_power_down(codec); 4121 4122 return 1; 4123} 4124 4125static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4126 struct snd_ctl_elem_value *ucontrol) 4127{ 4128 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4129 struct ca0132_spec *spec = codec->spec; 4130 hda_nid_t nid = get_amp_nid(kcontrol); 4131 long *valp = ucontrol->value.integer.value; 4132 int idx = nid - TUNING_CTL_START_NID; 4133 4134 *valp = spec->cur_ctl_vals[idx]; 4135 return 0; 4136} 4137 4138static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4139 struct snd_ctl_elem_info *uinfo) 4140{ 4141 int chs = get_amp_channels(kcontrol); 4142 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4143 uinfo->count = chs == 3 ? 2 : 1; 4144 uinfo->value.integer.min = 20; 4145 uinfo->value.integer.max = 180; 4146 uinfo->value.integer.step = 1; 4147 4148 return 0; 4149} 4150 4151static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4152 struct snd_ctl_elem_value *ucontrol) 4153{ 4154 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4155 struct ca0132_spec *spec = codec->spec; 4156 hda_nid_t nid = get_amp_nid(kcontrol); 4157 long *valp = ucontrol->value.integer.value; 4158 int idx; 4159 4160 idx = nid - TUNING_CTL_START_NID; 4161 /* any change? */ 4162 if (spec->cur_ctl_vals[idx] == *valp) 4163 return 0; 4164 4165 spec->cur_ctl_vals[idx] = *valp; 4166 4167 idx = *valp - 20; 4168 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4169 4170 return 1; 4171} 4172 4173static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4174 struct snd_ctl_elem_info *uinfo) 4175{ 4176 int chs = get_amp_channels(kcontrol); 4177 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4178 uinfo->count = chs == 3 ? 2 : 1; 4179 uinfo->value.integer.min = 0; 4180 uinfo->value.integer.max = 100; 4181 uinfo->value.integer.step = 1; 4182 4183 return 0; 4184} 4185 4186static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4187 struct snd_ctl_elem_value *ucontrol) 4188{ 4189 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4190 struct ca0132_spec *spec = codec->spec; 4191 hda_nid_t nid = get_amp_nid(kcontrol); 4192 long *valp = ucontrol->value.integer.value; 4193 int idx; 4194 4195 idx = nid - TUNING_CTL_START_NID; 4196 /* any change? */ 4197 if (spec->cur_ctl_vals[idx] == *valp) 4198 return 0; 4199 4200 spec->cur_ctl_vals[idx] = *valp; 4201 4202 idx = *valp; 4203 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4204 4205 return 0; 4206} 4207 4208static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4209 struct snd_ctl_elem_info *uinfo) 4210{ 4211 int chs = get_amp_channels(kcontrol); 4212 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4213 uinfo->count = chs == 3 ? 2 : 1; 4214 uinfo->value.integer.min = 0; 4215 uinfo->value.integer.max = 48; 4216 uinfo->value.integer.step = 1; 4217 4218 return 0; 4219} 4220 4221static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4222 struct snd_ctl_elem_value *ucontrol) 4223{ 4224 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4225 struct ca0132_spec *spec = codec->spec; 4226 hda_nid_t nid = get_amp_nid(kcontrol); 4227 long *valp = ucontrol->value.integer.value; 4228 int idx; 4229 4230 idx = nid - TUNING_CTL_START_NID; 4231 /* any change? */ 4232 if (spec->cur_ctl_vals[idx] == *valp) 4233 return 0; 4234 4235 spec->cur_ctl_vals[idx] = *valp; 4236 4237 idx = *valp; 4238 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4239 4240 return 1; 4241} 4242 4243static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4244static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4245 4246static int add_tuning_control(struct hda_codec *codec, 4247 hda_nid_t pnid, hda_nid_t nid, 4248 const char *name, int dir) 4249{ 4250 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4251 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4252 struct snd_kcontrol_new knew = 4253 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4254 4255 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4256 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4257 knew.tlv.c = 0; 4258 knew.tlv.p = 0; 4259 switch (pnid) { 4260 case VOICE_FOCUS: 4261 knew.info = voice_focus_ctl_info; 4262 knew.get = tuning_ctl_get; 4263 knew.put = voice_focus_ctl_put; 4264 knew.tlv.p = voice_focus_db_scale; 4265 break; 4266 case MIC_SVM: 4267 knew.info = mic_svm_ctl_info; 4268 knew.get = tuning_ctl_get; 4269 knew.put = mic_svm_ctl_put; 4270 break; 4271 case EQUALIZER: 4272 knew.info = equalizer_ctl_info; 4273 knew.get = tuning_ctl_get; 4274 knew.put = equalizer_ctl_put; 4275 knew.tlv.p = eq_db_scale; 4276 break; 4277 default: 4278 return 0; 4279 } 4280 knew.private_value = 4281 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4282 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4283 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4284} 4285 4286static int add_tuning_ctls(struct hda_codec *codec) 4287{ 4288 int i; 4289 int err; 4290 4291 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4292 err = add_tuning_control(codec, 4293 ca0132_tuning_ctls[i].parent_nid, 4294 ca0132_tuning_ctls[i].nid, 4295 ca0132_tuning_ctls[i].name, 4296 ca0132_tuning_ctls[i].direct); 4297 if (err < 0) 4298 return err; 4299 } 4300 4301 return 0; 4302} 4303 4304static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4305{ 4306 struct ca0132_spec *spec = codec->spec; 4307 int i; 4308 4309 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4310 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4311 /* SVM level defaults to 0.74. */ 4312 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4313 4314 /* EQ defaults to 0dB. */ 4315 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4316 spec->cur_ctl_vals[i] = 24; 4317} 4318#endif /*ENABLE_TUNING_CONTROLS*/ 4319 4320/* 4321 * Select the active output. 4322 * If autodetect is enabled, output will be selected based on jack detection. 4323 * If jack inserted, headphone will be selected, else built-in speakers 4324 * If autodetect is disabled, output will be selected based on selection. 4325 */ 4326static int ca0132_select_out(struct hda_codec *codec) 4327{ 4328 struct ca0132_spec *spec = codec->spec; 4329 unsigned int pin_ctl; 4330 int jack_present; 4331 int auto_jack; 4332 unsigned int tmp; 4333 int err; 4334 4335 codec_dbg(codec, "ca0132_select_out\n"); 4336 4337 snd_hda_power_up_pm(codec); 4338 4339 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4340 4341 if (auto_jack) 4342 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4343 else 4344 jack_present = 4345 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4346 4347 if (jack_present) 4348 spec->cur_out_type = HEADPHONE_OUT; 4349 else 4350 spec->cur_out_type = SPEAKER_OUT; 4351 4352 if (spec->cur_out_type == SPEAKER_OUT) { 4353 codec_dbg(codec, "ca0132_select_out speaker\n"); 4354 /*speaker out config*/ 4355 tmp = FLOAT_ONE; 4356 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4357 if (err < 0) 4358 goto exit; 4359 /*enable speaker EQ*/ 4360 tmp = FLOAT_ONE; 4361 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4362 if (err < 0) 4363 goto exit; 4364 4365 /* Setup EAPD */ 4366 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4367 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4368 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4369 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4370 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4371 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4372 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4373 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4374 4375 /* disable headphone node */ 4376 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4377 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4378 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4379 pin_ctl & ~PIN_HP); 4380 /* enable speaker node */ 4381 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4382 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4383 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4384 pin_ctl | PIN_OUT); 4385 } else { 4386 codec_dbg(codec, "ca0132_select_out hp\n"); 4387 /*headphone out config*/ 4388 tmp = FLOAT_ZERO; 4389 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4390 if (err < 0) 4391 goto exit; 4392 /*disable speaker EQ*/ 4393 tmp = FLOAT_ZERO; 4394 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4395 if (err < 0) 4396 goto exit; 4397 4398 /* Setup EAPD */ 4399 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4400 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4401 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4402 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4403 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4404 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4405 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4406 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4407 4408 /* disable speaker*/ 4409 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4410 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4411 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4412 pin_ctl & ~PIN_HP); 4413 /* enable headphone*/ 4414 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4415 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4416 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4417 pin_ctl | PIN_HP); 4418 } 4419 4420exit: 4421 snd_hda_power_down_pm(codec); 4422 4423 return err < 0 ? err : 0; 4424} 4425 4426static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4427static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4428static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4429 4430static void ae5_mmio_select_out(struct hda_codec *codec) 4431{ 4432 struct ca0132_spec *spec = codec->spec; 4433 const struct ae_ca0113_output_set *out_cmds; 4434 unsigned int i; 4435 4436 if (ca0132_quirk(spec) == QUIRK_AE5) 4437 out_cmds = &ae5_ca0113_output_presets; 4438 else 4439 out_cmds = &ae7_ca0113_output_presets; 4440 4441 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4442 ca0113_mmio_command_set(codec, out_cmds->group[i], 4443 out_cmds->target[i], 4444 out_cmds->vals[spec->cur_out_type][i]); 4445} 4446 4447static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4448{ 4449 struct ca0132_spec *spec = codec->spec; 4450 int quirk = ca0132_quirk(spec); 4451 unsigned int tmp; 4452 int err; 4453 4454 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4455 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4456 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4457 return 0; 4458 4459 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4460 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4461 err = dspio_set_uint_param(codec, 0x96, 4462 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4463 if (err < 0) 4464 return err; 4465 4466 /* When setting full-range rear, both rear and center/lfe are set. */ 4467 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4468 err = dspio_set_uint_param(codec, 0x96, 4469 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4470 if (err < 0) 4471 return err; 4472 4473 err = dspio_set_uint_param(codec, 0x96, 4474 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4475 if (err < 0) 4476 return err; 4477 4478 /* 4479 * Only the AE series cards set this value when setting full-range, 4480 * and it's always 1.0f. 4481 */ 4482 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4483 err = dspio_set_uint_param(codec, 0x96, 4484 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4485 if (err < 0) 4486 return err; 4487 } 4488 4489 return 0; 4490} 4491 4492static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4493 bool val) 4494{ 4495 struct ca0132_spec *spec = codec->spec; 4496 unsigned int tmp; 4497 int err; 4498 4499 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4500 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4501 tmp = FLOAT_ONE; 4502 else 4503 tmp = FLOAT_ZERO; 4504 4505 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4506 if (err < 0) 4507 return err; 4508 4509 /* If it is enabled, make sure to set the crossover frequency. */ 4510 if (tmp) { 4511 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4512 err = dspio_set_uint_param(codec, 0x96, 4513 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4514 if (err < 0) 4515 return err; 4516 } 4517 4518 return 0; 4519} 4520 4521/* 4522 * These are the commands needed to setup output on each of the different card 4523 * types. 4524 */ 4525static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4526 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4527{ 4528 struct ca0132_spec *spec = codec->spec; 4529 int quirk = ca0132_quirk(spec); 4530 unsigned int i; 4531 4532 *quirk_data = NULL; 4533 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4534 if (quirk_out_set_data[i].quirk_id == quirk) { 4535 *quirk_data = &quirk_out_set_data[i]; 4536 return; 4537 } 4538 } 4539} 4540 4541static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4542{ 4543 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4544 const struct ca0132_alt_out_set_info *out_info; 4545 struct ca0132_spec *spec = codec->spec; 4546 unsigned int i, gpio_data; 4547 int err; 4548 4549 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4550 if (!quirk_data) 4551 return 0; 4552 4553 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4554 if (quirk_data->is_ae_series) 4555 ae5_mmio_select_out(codec); 4556 4557 if (out_info->has_hda_gpio) { 4558 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4559 AC_VERB_GET_GPIO_DATA, 0); 4560 4561 if (out_info->hda_gpio_set) 4562 gpio_data |= (1 << out_info->hda_gpio_pin); 4563 else 4564 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4565 4566 snd_hda_codec_write(codec, codec->core.afg, 0, 4567 AC_VERB_SET_GPIO_DATA, gpio_data); 4568 } 4569 4570 if (out_info->mmio_gpio_count) { 4571 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4572 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4573 out_info->mmio_gpio_set[i]); 4574 } 4575 } 4576 4577 if (out_info->scp_cmds_count) { 4578 for (i = 0; i < out_info->scp_cmds_count; i++) { 4579 err = dspio_set_uint_param(codec, 4580 out_info->scp_cmd_mid[i], 4581 out_info->scp_cmd_req[i], 4582 out_info->scp_cmd_val[i]); 4583 if (err < 0) 4584 return err; 4585 } 4586 } 4587 4588 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4589 4590 if (out_info->has_chipio_write) { 4591 chipio_write(codec, out_info->chipio_write_addr, 4592 out_info->chipio_write_data); 4593 } 4594 4595 if (quirk_data->has_headphone_gain) { 4596 if (spec->cur_out_type != HEADPHONE_OUT) { 4597 if (quirk_data->is_ae_series) 4598 ae5_headphone_gain_set(codec, 2); 4599 else 4600 zxr_headphone_gain_set(codec, 0); 4601 } else { 4602 if (quirk_data->is_ae_series) 4603 ae5_headphone_gain_set(codec, 4604 spec->ae5_headphone_gain_val); 4605 else 4606 zxr_headphone_gain_set(codec, 4607 spec->zxr_gain_set); 4608 } 4609 } 4610 4611 return 0; 4612} 4613 4614static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4615 bool out_enable, bool hp_enable) 4616{ 4617 unsigned int pin_ctl; 4618 4619 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4620 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4621 4622 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4623 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4624 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4625} 4626 4627/* 4628 * This function behaves similarly to the ca0132_select_out funciton above, 4629 * except with a few differences. It adds the ability to select the current 4630 * output with an enumerated control "output source" if the auto detect 4631 * mute switch is set to off. If the auto detect mute switch is enabled, it 4632 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4633 * It also adds the ability to auto-detect the front headphone port. 4634 */ 4635static int ca0132_alt_select_out(struct hda_codec *codec) 4636{ 4637 struct ca0132_spec *spec = codec->spec; 4638 unsigned int tmp, outfx_set; 4639 int jack_present; 4640 int auto_jack; 4641 int err; 4642 /* Default Headphone is rear headphone */ 4643 hda_nid_t headphone_nid = spec->out_pins[1]; 4644 4645 codec_dbg(codec, "%s\n", __func__); 4646 4647 snd_hda_power_up_pm(codec); 4648 4649 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4650 4651 /* 4652 * If headphone rear or front is plugged in, set to headphone. 4653 * If neither is plugged in, set to rear line out. Only if 4654 * hp/speaker auto detect is enabled. 4655 */ 4656 if (auto_jack) { 4657 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4658 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4659 4660 if (jack_present) 4661 spec->cur_out_type = HEADPHONE_OUT; 4662 else 4663 spec->cur_out_type = SPEAKER_OUT; 4664 } else 4665 spec->cur_out_type = spec->out_enum_val; 4666 4667 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4668 4669 /* Begin DSP output switch, mute DSP volume. */ 4670 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4671 if (err < 0) 4672 goto exit; 4673 4674 if (ca0132_alt_select_out_quirk_set(codec) < 0) 4675 goto exit; 4676 4677 switch (spec->cur_out_type) { 4678 case SPEAKER_OUT: 4679 codec_dbg(codec, "%s speaker\n", __func__); 4680 4681 /* Enable EAPD */ 4682 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4683 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4684 4685 /* Disable headphone node. */ 4686 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4687 /* Set front L-R to output. */ 4688 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4689 /* Set Center/LFE to output. */ 4690 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4691 /* Set rear surround to output. */ 4692 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4693 4694 /* 4695 * Without PlayEnhancement being enabled, if we've got a 2.0 4696 * setup, set it to floating point eight to disable any DSP 4697 * processing effects. 4698 */ 4699 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4700 tmp = FLOAT_EIGHT; 4701 else 4702 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4703 4704 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4705 if (err < 0) 4706 goto exit; 4707 4708 break; 4709 case HEADPHONE_OUT: 4710 codec_dbg(codec, "%s hp\n", __func__); 4711 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4712 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4713 4714 /* Disable all speaker nodes. */ 4715 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4716 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4717 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4718 4719 /* enable headphone, either front or rear */ 4720 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4721 headphone_nid = spec->out_pins[2]; 4722 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4723 headphone_nid = spec->out_pins[1]; 4724 4725 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4726 4727 if (outfx_set) 4728 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4729 else 4730 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4731 4732 if (err < 0) 4733 goto exit; 4734 break; 4735 } 4736 /* 4737 * If output effects are enabled, set the X-Bass effect value again to 4738 * make sure that it's properly enabled/disabled for speaker 4739 * configurations with an LFE channel. 4740 */ 4741 if (outfx_set) 4742 ca0132_effects_set(codec, X_BASS, 4743 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4744 4745 /* Set speaker EQ bypass attenuation to 0. */ 4746 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4747 if (err < 0) 4748 goto exit; 4749 4750 /* 4751 * Although unused on all cards but the AE series, this is always set 4752 * to zero when setting the output. 4753 */ 4754 err = dspio_set_uint_param(codec, 0x96, 4755 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4756 if (err < 0) 4757 goto exit; 4758 4759 if (spec->cur_out_type == SPEAKER_OUT) 4760 err = ca0132_alt_surround_set_bass_redirection(codec, 4761 spec->bass_redirection_val); 4762 else 4763 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4764 4765 /* Unmute DSP now that we're done with output selection. */ 4766 err = dspio_set_uint_param(codec, 0x96, 4767 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4768 if (err < 0) 4769 goto exit; 4770 4771 if (spec->cur_out_type == SPEAKER_OUT) { 4772 err = ca0132_alt_set_full_range_speaker(codec); 4773 if (err < 0) 4774 goto exit; 4775 } 4776 4777exit: 4778 snd_hda_power_down_pm(codec); 4779 4780 return err < 0 ? err : 0; 4781} 4782 4783static void ca0132_unsol_hp_delayed(struct work_struct *work) 4784{ 4785 struct ca0132_spec *spec = container_of( 4786 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4787 struct hda_jack_tbl *jack; 4788 4789 if (ca0132_use_alt_functions(spec)) 4790 ca0132_alt_select_out(spec->codec); 4791 else 4792 ca0132_select_out(spec->codec); 4793 4794 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4795 if (jack) { 4796 jack->block_report = 0; 4797 snd_hda_jack_report_sync(spec->codec); 4798 } 4799} 4800 4801static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4802static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4803static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4804static int stop_mic1(struct hda_codec *codec); 4805static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4806static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4807 4808/* 4809 * Select the active VIP source 4810 */ 4811static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4812{ 4813 struct ca0132_spec *spec = codec->spec; 4814 unsigned int tmp; 4815 4816 if (spec->dsp_state != DSP_DOWNLOADED) 4817 return 0; 4818 4819 /* if CrystalVoice if off, vipsource should be 0 */ 4820 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4821 (val == 0)) { 4822 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4823 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4824 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4825 if (spec->cur_mic_type == DIGITAL_MIC) 4826 tmp = FLOAT_TWO; 4827 else 4828 tmp = FLOAT_ONE; 4829 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4830 tmp = FLOAT_ZERO; 4831 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4832 } else { 4833 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4834 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4835 if (spec->cur_mic_type == DIGITAL_MIC) 4836 tmp = FLOAT_TWO; 4837 else 4838 tmp = FLOAT_ONE; 4839 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4840 tmp = FLOAT_ONE; 4841 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4842 msleep(20); 4843 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4844 } 4845 4846 return 1; 4847} 4848 4849static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4850{ 4851 struct ca0132_spec *spec = codec->spec; 4852 unsigned int tmp; 4853 4854 if (spec->dsp_state != DSP_DOWNLOADED) 4855 return 0; 4856 4857 codec_dbg(codec, "%s\n", __func__); 4858 4859 chipio_set_stream_control(codec, 0x03, 0); 4860 chipio_set_stream_control(codec, 0x04, 0); 4861 4862 /* if CrystalVoice is off, vipsource should be 0 */ 4863 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4864 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4865 codec_dbg(codec, "%s: off.", __func__); 4866 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4867 4868 tmp = FLOAT_ZERO; 4869 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4870 4871 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4872 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4873 if (ca0132_quirk(spec) == QUIRK_R3DI) 4874 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4875 4876 4877 if (spec->in_enum_val == REAR_LINE_IN) 4878 tmp = FLOAT_ZERO; 4879 else { 4880 if (ca0132_quirk(spec) == QUIRK_SBZ) 4881 tmp = FLOAT_THREE; 4882 else 4883 tmp = FLOAT_ONE; 4884 } 4885 4886 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4887 4888 } else { 4889 codec_dbg(codec, "%s: on.", __func__); 4890 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4891 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4892 if (ca0132_quirk(spec) == QUIRK_R3DI) 4893 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4894 4895 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4896 tmp = FLOAT_TWO; 4897 else 4898 tmp = FLOAT_ONE; 4899 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4900 4901 tmp = FLOAT_ONE; 4902 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4903 4904 msleep(20); 4905 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4906 } 4907 4908 chipio_set_stream_control(codec, 0x03, 1); 4909 chipio_set_stream_control(codec, 0x04, 1); 4910 4911 return 1; 4912} 4913 4914/* 4915 * Select the active microphone. 4916 * If autodetect is enabled, mic will be selected based on jack detection. 4917 * If jack inserted, ext.mic will be selected, else built-in mic 4918 * If autodetect is disabled, mic will be selected based on selection. 4919 */ 4920static int ca0132_select_mic(struct hda_codec *codec) 4921{ 4922 struct ca0132_spec *spec = codec->spec; 4923 int jack_present; 4924 int auto_jack; 4925 4926 codec_dbg(codec, "ca0132_select_mic\n"); 4927 4928 snd_hda_power_up_pm(codec); 4929 4930 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4931 4932 if (auto_jack) 4933 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4934 else 4935 jack_present = 4936 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4937 4938 if (jack_present) 4939 spec->cur_mic_type = LINE_MIC_IN; 4940 else 4941 spec->cur_mic_type = DIGITAL_MIC; 4942 4943 if (spec->cur_mic_type == DIGITAL_MIC) { 4944 /* enable digital Mic */ 4945 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4946 ca0132_set_dmic(codec, 1); 4947 ca0132_mic_boost_set(codec, 0); 4948 /* set voice focus */ 4949 ca0132_effects_set(codec, VOICE_FOCUS, 4950 spec->effects_switch 4951 [VOICE_FOCUS - EFFECT_START_NID]); 4952 } else { 4953 /* disable digital Mic */ 4954 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4955 ca0132_set_dmic(codec, 0); 4956 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4957 /* disable voice focus */ 4958 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4959 } 4960 4961 snd_hda_power_down_pm(codec); 4962 4963 return 0; 4964} 4965 4966/* 4967 * Select the active input. 4968 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4969 * The front mic has no jack-detection, so the only way to switch to it 4970 * is to do it manually in alsamixer. 4971 */ 4972static int ca0132_alt_select_in(struct hda_codec *codec) 4973{ 4974 struct ca0132_spec *spec = codec->spec; 4975 unsigned int tmp; 4976 4977 codec_dbg(codec, "%s\n", __func__); 4978 4979 snd_hda_power_up_pm(codec); 4980 4981 chipio_set_stream_control(codec, 0x03, 0); 4982 chipio_set_stream_control(codec, 0x04, 0); 4983 4984 spec->cur_mic_type = spec->in_enum_val; 4985 4986 switch (spec->cur_mic_type) { 4987 case REAR_MIC: 4988 switch (ca0132_quirk(spec)) { 4989 case QUIRK_SBZ: 4990 case QUIRK_R3D: 4991 ca0113_mmio_gpio_set(codec, 0, false); 4992 tmp = FLOAT_THREE; 4993 break; 4994 case QUIRK_ZXR: 4995 tmp = FLOAT_THREE; 4996 break; 4997 case QUIRK_R3DI: 4998 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4999 tmp = FLOAT_ONE; 5000 break; 5001 case QUIRK_AE5: 5002 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5003 tmp = FLOAT_THREE; 5004 break; 5005 case QUIRK_AE7: 5006 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5007 tmp = FLOAT_THREE; 5008 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5009 SR_96_000); 5010 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5011 SR_96_000); 5012 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5013 break; 5014 default: 5015 tmp = FLOAT_ONE; 5016 break; 5017 } 5018 5019 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5020 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5021 if (ca0132_quirk(spec) == QUIRK_R3DI) 5022 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5023 5024 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5025 5026 chipio_set_stream_control(codec, 0x03, 1); 5027 chipio_set_stream_control(codec, 0x04, 1); 5028 switch (ca0132_quirk(spec)) { 5029 case QUIRK_SBZ: 5030 chipio_write(codec, 0x18B098, 0x0000000C); 5031 chipio_write(codec, 0x18B09C, 0x0000000C); 5032 break; 5033 case QUIRK_ZXR: 5034 chipio_write(codec, 0x18B098, 0x0000000C); 5035 chipio_write(codec, 0x18B09C, 0x000000CC); 5036 break; 5037 case QUIRK_AE5: 5038 chipio_write(codec, 0x18B098, 0x0000000C); 5039 chipio_write(codec, 0x18B09C, 0x0000004C); 5040 break; 5041 default: 5042 break; 5043 } 5044 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5045 break; 5046 case REAR_LINE_IN: 5047 ca0132_mic_boost_set(codec, 0); 5048 switch (ca0132_quirk(spec)) { 5049 case QUIRK_SBZ: 5050 case QUIRK_R3D: 5051 ca0113_mmio_gpio_set(codec, 0, false); 5052 break; 5053 case QUIRK_R3DI: 5054 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5055 break; 5056 case QUIRK_AE5: 5057 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5058 break; 5059 case QUIRK_AE7: 5060 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5061 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5062 SR_96_000); 5063 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5064 SR_96_000); 5065 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5066 break; 5067 default: 5068 break; 5069 } 5070 5071 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5072 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5073 if (ca0132_quirk(spec) == QUIRK_R3DI) 5074 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5075 5076 if (ca0132_quirk(spec) == QUIRK_AE7) 5077 tmp = FLOAT_THREE; 5078 else 5079 tmp = FLOAT_ZERO; 5080 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5081 5082 switch (ca0132_quirk(spec)) { 5083 case QUIRK_SBZ: 5084 case QUIRK_AE5: 5085 chipio_write(codec, 0x18B098, 0x00000000); 5086 chipio_write(codec, 0x18B09C, 0x00000000); 5087 break; 5088 default: 5089 break; 5090 } 5091 chipio_set_stream_control(codec, 0x03, 1); 5092 chipio_set_stream_control(codec, 0x04, 1); 5093 break; 5094 case FRONT_MIC: 5095 switch (ca0132_quirk(spec)) { 5096 case QUIRK_SBZ: 5097 case QUIRK_R3D: 5098 ca0113_mmio_gpio_set(codec, 0, true); 5099 ca0113_mmio_gpio_set(codec, 5, false); 5100 tmp = FLOAT_THREE; 5101 break; 5102 case QUIRK_R3DI: 5103 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5104 tmp = FLOAT_ONE; 5105 break; 5106 case QUIRK_AE5: 5107 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5108 tmp = FLOAT_THREE; 5109 break; 5110 default: 5111 tmp = FLOAT_ONE; 5112 break; 5113 } 5114 5115 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5116 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5117 if (ca0132_quirk(spec) == QUIRK_R3DI) 5118 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5119 5120 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5121 5122 chipio_set_stream_control(codec, 0x03, 1); 5123 chipio_set_stream_control(codec, 0x04, 1); 5124 5125 switch (ca0132_quirk(spec)) { 5126 case QUIRK_SBZ: 5127 chipio_write(codec, 0x18B098, 0x0000000C); 5128 chipio_write(codec, 0x18B09C, 0x000000CC); 5129 break; 5130 case QUIRK_AE5: 5131 chipio_write(codec, 0x18B098, 0x0000000C); 5132 chipio_write(codec, 0x18B09C, 0x0000004C); 5133 break; 5134 default: 5135 break; 5136 } 5137 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5138 break; 5139 } 5140 ca0132_cvoice_switch_set(codec); 5141 5142 snd_hda_power_down_pm(codec); 5143 return 0; 5144} 5145 5146/* 5147 * Check if VNODE settings take effect immediately. 5148 */ 5149static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5150 hda_nid_t vnid, 5151 hda_nid_t *shared_nid) 5152{ 5153 struct ca0132_spec *spec = codec->spec; 5154 hda_nid_t nid; 5155 5156 switch (vnid) { 5157 case VNID_SPK: 5158 nid = spec->shared_out_nid; 5159 break; 5160 case VNID_MIC: 5161 nid = spec->shared_mic_nid; 5162 break; 5163 default: 5164 return false; 5165 } 5166 5167 if (shared_nid) 5168 *shared_nid = nid; 5169 5170 return true; 5171} 5172 5173/* 5174* The following functions are control change helpers. 5175* They return 0 if no changed. Return 1 if changed. 5176*/ 5177static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5178{ 5179 struct ca0132_spec *spec = codec->spec; 5180 unsigned int tmp; 5181 5182 /* based on CrystalVoice state to enable VoiceFX. */ 5183 if (enable) { 5184 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5185 FLOAT_ONE : FLOAT_ZERO; 5186 } else { 5187 tmp = FLOAT_ZERO; 5188 } 5189 5190 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5191 ca0132_voicefx.reqs[0], tmp); 5192 5193 return 1; 5194} 5195 5196/* 5197 * Set the effects parameters 5198 */ 5199static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5200{ 5201 struct ca0132_spec *spec = codec->spec; 5202 unsigned int on, tmp, channel_cfg; 5203 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5204 int err = 0; 5205 int idx = nid - EFFECT_START_NID; 5206 5207 if ((idx < 0) || (idx >= num_fx)) 5208 return 0; /* no changed */ 5209 5210 /* for out effect, qualify with PE */ 5211 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5212 /* if PE if off, turn off out effects. */ 5213 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5214 val = 0; 5215 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5216 channel_cfg = spec->channel_cfg_val; 5217 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5218 channel_cfg != SPEAKER_CHANNELS_4_0) 5219 val = 0; 5220 } 5221 } 5222 5223 /* for in effect, qualify with CrystalVoice */ 5224 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5225 /* if CrystalVoice if off, turn off in effects. */ 5226 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5227 val = 0; 5228 5229 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5230 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5231 val = 0; 5232 5233 /* If Voice Focus on SBZ, set to two channel. */ 5234 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5235 && (spec->cur_mic_type != REAR_LINE_IN)) { 5236 if (spec->effects_switch[CRYSTAL_VOICE - 5237 EFFECT_START_NID]) { 5238 5239 if (spec->effects_switch[VOICE_FOCUS - 5240 EFFECT_START_NID]) { 5241 tmp = FLOAT_TWO; 5242 val = 1; 5243 } else 5244 tmp = FLOAT_ONE; 5245 5246 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5247 } 5248 } 5249 /* 5250 * For SBZ noise reduction, there's an extra command 5251 * to module ID 0x47. No clue why. 5252 */ 5253 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5254 && (spec->cur_mic_type != REAR_LINE_IN)) { 5255 if (spec->effects_switch[CRYSTAL_VOICE - 5256 EFFECT_START_NID]) { 5257 if (spec->effects_switch[NOISE_REDUCTION - 5258 EFFECT_START_NID]) 5259 tmp = FLOAT_ONE; 5260 else 5261 tmp = FLOAT_ZERO; 5262 } else 5263 tmp = FLOAT_ZERO; 5264 5265 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5266 } 5267 5268 /* If rear line in disable effects. */ 5269 if (ca0132_use_alt_functions(spec) && 5270 spec->in_enum_val == REAR_LINE_IN) 5271 val = 0; 5272 } 5273 5274 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5275 nid, val); 5276 5277 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5278 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5279 ca0132_effects[idx].reqs[0], on); 5280 5281 if (err < 0) 5282 return 0; /* no changed */ 5283 5284 return 1; 5285} 5286 5287/* 5288 * Turn on/off Playback Enhancements 5289 */ 5290static int ca0132_pe_switch_set(struct hda_codec *codec) 5291{ 5292 struct ca0132_spec *spec = codec->spec; 5293 hda_nid_t nid; 5294 int i, ret = 0; 5295 5296 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5297 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5298 5299 if (ca0132_use_alt_functions(spec)) 5300 ca0132_alt_select_out(codec); 5301 5302 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5303 nid = OUT_EFFECT_START_NID; 5304 /* PE affects all out effects */ 5305 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5306 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5307 5308 return ret; 5309} 5310 5311/* Check if Mic1 is streaming, if so, stop streaming */ 5312static int stop_mic1(struct hda_codec *codec) 5313{ 5314 struct ca0132_spec *spec = codec->spec; 5315 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5316 AC_VERB_GET_CONV, 0); 5317 if (oldval != 0) 5318 snd_hda_codec_write(codec, spec->adcs[0], 0, 5319 AC_VERB_SET_CHANNEL_STREAMID, 5320 0); 5321 return oldval; 5322} 5323 5324/* Resume Mic1 streaming if it was stopped. */ 5325static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5326{ 5327 struct ca0132_spec *spec = codec->spec; 5328 /* Restore the previous stream and channel */ 5329 if (oldval != 0) 5330 snd_hda_codec_write(codec, spec->adcs[0], 0, 5331 AC_VERB_SET_CHANNEL_STREAMID, 5332 oldval); 5333} 5334 5335/* 5336 * Turn on/off CrystalVoice 5337 */ 5338static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5339{ 5340 struct ca0132_spec *spec = codec->spec; 5341 hda_nid_t nid; 5342 int i, ret = 0; 5343 unsigned int oldval; 5344 5345 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5346 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5347 5348 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5349 nid = IN_EFFECT_START_NID; 5350 /* CrystalVoice affects all in effects */ 5351 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5352 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5353 5354 /* including VoiceFX */ 5355 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5356 5357 /* set correct vipsource */ 5358 oldval = stop_mic1(codec); 5359 if (ca0132_use_alt_functions(spec)) 5360 ret |= ca0132_alt_set_vipsource(codec, 1); 5361 else 5362 ret |= ca0132_set_vipsource(codec, 1); 5363 resume_mic1(codec, oldval); 5364 return ret; 5365} 5366 5367static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5368{ 5369 struct ca0132_spec *spec = codec->spec; 5370 int ret = 0; 5371 5372 if (val) /* on */ 5373 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5374 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5375 else /* off */ 5376 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5377 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5378 5379 return ret; 5380} 5381 5382static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5383{ 5384 struct ca0132_spec *spec = codec->spec; 5385 int ret = 0; 5386 5387 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5388 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5389 return ret; 5390} 5391 5392static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5393{ 5394 unsigned int i; 5395 5396 for (i = 0; i < 4; i++) 5397 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5398 ae5_headphone_gain_presets[val].vals[i]); 5399 return 0; 5400} 5401 5402/* 5403 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5404 * amplifier to handle a 600 ohm load. 5405 */ 5406static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5407{ 5408 ca0113_mmio_gpio_set(codec, 1, val); 5409 5410 return 0; 5411} 5412 5413static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5414 struct snd_ctl_elem_value *ucontrol) 5415{ 5416 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5417 hda_nid_t nid = get_amp_nid(kcontrol); 5418 hda_nid_t shared_nid = 0; 5419 bool effective; 5420 int ret = 0; 5421 struct ca0132_spec *spec = codec->spec; 5422 int auto_jack; 5423 5424 if (nid == VNID_HP_SEL) { 5425 auto_jack = 5426 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5427 if (!auto_jack) { 5428 if (ca0132_use_alt_functions(spec)) 5429 ca0132_alt_select_out(codec); 5430 else 5431 ca0132_select_out(codec); 5432 } 5433 return 1; 5434 } 5435 5436 if (nid == VNID_AMIC1_SEL) { 5437 auto_jack = 5438 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5439 if (!auto_jack) 5440 ca0132_select_mic(codec); 5441 return 1; 5442 } 5443 5444 if (nid == VNID_HP_ASEL) { 5445 if (ca0132_use_alt_functions(spec)) 5446 ca0132_alt_select_out(codec); 5447 else 5448 ca0132_select_out(codec); 5449 return 1; 5450 } 5451 5452 if (nid == VNID_AMIC1_ASEL) { 5453 ca0132_select_mic(codec); 5454 return 1; 5455 } 5456 5457 /* if effective conditions, then update hw immediately. */ 5458 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5459 if (effective) { 5460 int dir = get_amp_direction(kcontrol); 5461 int ch = get_amp_channels(kcontrol); 5462 unsigned long pval; 5463 5464 mutex_lock(&codec->control_mutex); 5465 pval = kcontrol->private_value; 5466 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5467 0, dir); 5468 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5469 kcontrol->private_value = pval; 5470 mutex_unlock(&codec->control_mutex); 5471 } 5472 5473 return ret; 5474} 5475/* End of control change helpers. */ 5476 5477static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5478 long idx) 5479{ 5480 snd_hda_power_up(codec); 5481 5482 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5483 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5484 5485 snd_hda_power_down(codec); 5486} 5487 5488/* 5489 * Below I've added controls to mess with the effect levels, I've only enabled 5490 * them on the Sound Blaster Z, but they would probably also work on the 5491 * Chromebook. I figured they were probably tuned specifically for it, and left 5492 * out for a reason. 5493 */ 5494 5495/* Sets DSP effect level from the sliders above the controls */ 5496 5497static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5498 const unsigned int *lookup, int idx) 5499{ 5500 int i = 0; 5501 unsigned int y; 5502 /* 5503 * For X_BASS, req 2 is actually crossover freq instead of 5504 * effect level 5505 */ 5506 if (nid == X_BASS) 5507 y = 2; 5508 else 5509 y = 1; 5510 5511 snd_hda_power_up(codec); 5512 if (nid == XBASS_XOVER) { 5513 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5514 if (ca0132_effects[i].nid == X_BASS) 5515 break; 5516 5517 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5518 ca0132_effects[i].reqs[1], 5519 &(lookup[idx - 1]), sizeof(unsigned int)); 5520 } else { 5521 /* Find the actual effect structure */ 5522 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5523 if (nid == ca0132_effects[i].nid) 5524 break; 5525 5526 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5527 ca0132_effects[i].reqs[y], 5528 &(lookup[idx]), sizeof(unsigned int)); 5529 } 5530 5531 snd_hda_power_down(codec); 5532 5533 return 0; 5534} 5535 5536static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5537 struct snd_ctl_elem_value *ucontrol) 5538{ 5539 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5540 struct ca0132_spec *spec = codec->spec; 5541 long *valp = ucontrol->value.integer.value; 5542 hda_nid_t nid = get_amp_nid(kcontrol); 5543 5544 if (nid == BASS_REDIRECTION_XOVER) 5545 *valp = spec->bass_redirect_xover_freq; 5546 else 5547 *valp = spec->xbass_xover_freq; 5548 5549 return 0; 5550} 5551 5552static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5553 struct snd_ctl_elem_value *ucontrol) 5554{ 5555 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5556 struct ca0132_spec *spec = codec->spec; 5557 hda_nid_t nid = get_amp_nid(kcontrol); 5558 long *valp = ucontrol->value.integer.value; 5559 int idx = nid - OUT_EFFECT_START_NID; 5560 5561 *valp = spec->fx_ctl_val[idx]; 5562 return 0; 5563} 5564 5565/* 5566 * The X-bass crossover starts at 10hz, so the min is 1. The 5567 * frequency is set in multiples of 10. 5568 */ 5569static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5570 struct snd_ctl_elem_info *uinfo) 5571{ 5572 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5573 uinfo->count = 1; 5574 uinfo->value.integer.min = 1; 5575 uinfo->value.integer.max = 100; 5576 uinfo->value.integer.step = 1; 5577 5578 return 0; 5579} 5580 5581static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5582 struct snd_ctl_elem_info *uinfo) 5583{ 5584 int chs = get_amp_channels(kcontrol); 5585 5586 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5587 uinfo->count = chs == 3 ? 2 : 1; 5588 uinfo->value.integer.min = 0; 5589 uinfo->value.integer.max = 100; 5590 uinfo->value.integer.step = 1; 5591 5592 return 0; 5593} 5594 5595static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5596 struct snd_ctl_elem_value *ucontrol) 5597{ 5598 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5599 struct ca0132_spec *spec = codec->spec; 5600 hda_nid_t nid = get_amp_nid(kcontrol); 5601 long *valp = ucontrol->value.integer.value; 5602 long *cur_val; 5603 int idx; 5604 5605 if (nid == BASS_REDIRECTION_XOVER) 5606 cur_val = &spec->bass_redirect_xover_freq; 5607 else 5608 cur_val = &spec->xbass_xover_freq; 5609 5610 /* any change? */ 5611 if (*cur_val == *valp) 5612 return 0; 5613 5614 *cur_val = *valp; 5615 5616 idx = *valp; 5617 if (nid == BASS_REDIRECTION_XOVER) 5618 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5619 else 5620 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5621 5622 return 0; 5623} 5624 5625static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5626 struct snd_ctl_elem_value *ucontrol) 5627{ 5628 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5629 struct ca0132_spec *spec = codec->spec; 5630 hda_nid_t nid = get_amp_nid(kcontrol); 5631 long *valp = ucontrol->value.integer.value; 5632 int idx; 5633 5634 idx = nid - EFFECT_START_NID; 5635 /* any change? */ 5636 if (spec->fx_ctl_val[idx] == *valp) 5637 return 0; 5638 5639 spec->fx_ctl_val[idx] = *valp; 5640 5641 idx = *valp; 5642 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5643 5644 return 0; 5645} 5646 5647 5648/* 5649 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5650 * only has off or full 30 dB, and didn't like making a volume slider that has 5651 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5652 */ 5653#define MIC_BOOST_NUM_OF_STEPS 4 5654#define MIC_BOOST_ENUM_MAX_STRLEN 10 5655 5656static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5657 struct snd_ctl_elem_info *uinfo) 5658{ 5659 char *sfx = "dB"; 5660 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5661 5662 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5663 uinfo->count = 1; 5664 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5665 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5666 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5667 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5668 strcpy(uinfo->value.enumerated.name, namestr); 5669 return 0; 5670} 5671 5672static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5673 struct snd_ctl_elem_value *ucontrol) 5674{ 5675 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5676 struct ca0132_spec *spec = codec->spec; 5677 5678 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5679 return 0; 5680} 5681 5682static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5683 struct snd_ctl_elem_value *ucontrol) 5684{ 5685 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5686 struct ca0132_spec *spec = codec->spec; 5687 int sel = ucontrol->value.enumerated.item[0]; 5688 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5689 5690 if (sel >= items) 5691 return 0; 5692 5693 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5694 sel); 5695 5696 spec->mic_boost_enum_val = sel; 5697 5698 if (spec->in_enum_val != REAR_LINE_IN) 5699 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5700 5701 return 1; 5702} 5703 5704/* 5705 * Sound BlasterX AE-5 Headphone Gain Controls. 5706 */ 5707#define AE5_HEADPHONE_GAIN_MAX 3 5708static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5709 struct snd_ctl_elem_info *uinfo) 5710{ 5711 char *sfx = " Ohms)"; 5712 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5713 5714 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5715 uinfo->count = 1; 5716 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5717 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5718 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5719 sprintf(namestr, "%s %s", 5720 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5721 sfx); 5722 strcpy(uinfo->value.enumerated.name, namestr); 5723 return 0; 5724} 5725 5726static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5727 struct snd_ctl_elem_value *ucontrol) 5728{ 5729 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5730 struct ca0132_spec *spec = codec->spec; 5731 5732 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5733 return 0; 5734} 5735 5736static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5737 struct snd_ctl_elem_value *ucontrol) 5738{ 5739 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5740 struct ca0132_spec *spec = codec->spec; 5741 int sel = ucontrol->value.enumerated.item[0]; 5742 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5743 5744 if (sel >= items) 5745 return 0; 5746 5747 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5748 sel); 5749 5750 spec->ae5_headphone_gain_val = sel; 5751 5752 if (spec->out_enum_val == HEADPHONE_OUT) 5753 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5754 5755 return 1; 5756} 5757 5758/* 5759 * Sound BlasterX AE-5 sound filter enumerated control. 5760 */ 5761#define AE5_SOUND_FILTER_MAX 3 5762 5763static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5764 struct snd_ctl_elem_info *uinfo) 5765{ 5766 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5767 5768 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5769 uinfo->count = 1; 5770 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5771 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5772 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5773 sprintf(namestr, "%s", 5774 ae5_filter_presets[uinfo->value.enumerated.item].name); 5775 strcpy(uinfo->value.enumerated.name, namestr); 5776 return 0; 5777} 5778 5779static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5780 struct snd_ctl_elem_value *ucontrol) 5781{ 5782 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5783 struct ca0132_spec *spec = codec->spec; 5784 5785 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5786 return 0; 5787} 5788 5789static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5790 struct snd_ctl_elem_value *ucontrol) 5791{ 5792 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5793 struct ca0132_spec *spec = codec->spec; 5794 int sel = ucontrol->value.enumerated.item[0]; 5795 unsigned int items = AE5_SOUND_FILTER_MAX; 5796 5797 if (sel >= items) 5798 return 0; 5799 5800 codec_dbg(codec, "ae5_sound_filter: %s\n", 5801 ae5_filter_presets[sel].name); 5802 5803 spec->ae5_filter_val = sel; 5804 5805 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5806 ae5_filter_presets[sel].val); 5807 5808 return 1; 5809} 5810 5811/* 5812 * Input Select Control for alternative ca0132 codecs. This exists because 5813 * front microphone has no auto-detect, and we need a way to set the rear 5814 * as line-in 5815 */ 5816static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5817 struct snd_ctl_elem_info *uinfo) 5818{ 5819 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5820 uinfo->count = 1; 5821 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5822 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5823 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5824 strcpy(uinfo->value.enumerated.name, 5825 in_src_str[uinfo->value.enumerated.item]); 5826 return 0; 5827} 5828 5829static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5830 struct snd_ctl_elem_value *ucontrol) 5831{ 5832 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5833 struct ca0132_spec *spec = codec->spec; 5834 5835 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5836 return 0; 5837} 5838 5839static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5840 struct snd_ctl_elem_value *ucontrol) 5841{ 5842 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5843 struct ca0132_spec *spec = codec->spec; 5844 int sel = ucontrol->value.enumerated.item[0]; 5845 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5846 5847 /* 5848 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5849 * line-in. 5850 */ 5851 if (ca0132_quirk(spec) == QUIRK_AE7) 5852 items = 2; 5853 5854 if (sel >= items) 5855 return 0; 5856 5857 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5858 sel, in_src_str[sel]); 5859 5860 spec->in_enum_val = sel; 5861 5862 ca0132_alt_select_in(codec); 5863 5864 return 1; 5865} 5866 5867/* Sound Blaster Z Output Select Control */ 5868static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5869 struct snd_ctl_elem_info *uinfo) 5870{ 5871 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5872 uinfo->count = 1; 5873 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5874 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5875 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5876 strcpy(uinfo->value.enumerated.name, 5877 out_type_str[uinfo->value.enumerated.item]); 5878 return 0; 5879} 5880 5881static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5882 struct snd_ctl_elem_value *ucontrol) 5883{ 5884 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5885 struct ca0132_spec *spec = codec->spec; 5886 5887 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5888 return 0; 5889} 5890 5891static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5892 struct snd_ctl_elem_value *ucontrol) 5893{ 5894 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5895 struct ca0132_spec *spec = codec->spec; 5896 int sel = ucontrol->value.enumerated.item[0]; 5897 unsigned int items = NUM_OF_OUTPUTS; 5898 unsigned int auto_jack; 5899 5900 if (sel >= items) 5901 return 0; 5902 5903 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 5904 sel, out_type_str[sel]); 5905 5906 spec->out_enum_val = sel; 5907 5908 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5909 5910 if (!auto_jack) 5911 ca0132_alt_select_out(codec); 5912 5913 return 1; 5914} 5915 5916/* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 5917static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 5918 struct snd_ctl_elem_info *uinfo) 5919{ 5920 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 5921 5922 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5923 uinfo->count = 1; 5924 uinfo->value.enumerated.items = items; 5925 if (uinfo->value.enumerated.item >= items) 5926 uinfo->value.enumerated.item = items - 1; 5927 strcpy(uinfo->value.enumerated.name, 5928 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 5929 return 0; 5930} 5931 5932static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 5933 struct snd_ctl_elem_value *ucontrol) 5934{ 5935 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5936 struct ca0132_spec *spec = codec->spec; 5937 5938 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 5939 return 0; 5940} 5941 5942static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 5943 struct snd_ctl_elem_value *ucontrol) 5944{ 5945 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5946 struct ca0132_spec *spec = codec->spec; 5947 int sel = ucontrol->value.enumerated.item[0]; 5948 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 5949 5950 if (sel >= items) 5951 return 0; 5952 5953 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 5954 sel, speaker_channel_cfgs[sel].name); 5955 5956 spec->channel_cfg_val = sel; 5957 5958 if (spec->out_enum_val == SPEAKER_OUT) 5959 ca0132_alt_select_out(codec); 5960 5961 return 1; 5962} 5963 5964/* 5965 * Smart Volume output setting control. Three different settings, Normal, 5966 * which takes the value from the smart volume slider. The two others, loud 5967 * and night, disregard the slider value and have uneditable values. 5968 */ 5969#define NUM_OF_SVM_SETTINGS 3 5970static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 5971 5972static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5973 struct snd_ctl_elem_info *uinfo) 5974{ 5975 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5976 uinfo->count = 1; 5977 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5978 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5979 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5980 strcpy(uinfo->value.enumerated.name, 5981 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5982 return 0; 5983} 5984 5985static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5986 struct snd_ctl_elem_value *ucontrol) 5987{ 5988 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5989 struct ca0132_spec *spec = codec->spec; 5990 5991 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5992 return 0; 5993} 5994 5995static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5996 struct snd_ctl_elem_value *ucontrol) 5997{ 5998 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5999 struct ca0132_spec *spec = codec->spec; 6000 int sel = ucontrol->value.enumerated.item[0]; 6001 unsigned int items = NUM_OF_SVM_SETTINGS; 6002 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6003 unsigned int tmp; 6004 6005 if (sel >= items) 6006 return 0; 6007 6008 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6009 sel, out_svm_set_enum_str[sel]); 6010 6011 spec->smart_volume_setting = sel; 6012 6013 switch (sel) { 6014 case 0: 6015 tmp = FLOAT_ZERO; 6016 break; 6017 case 1: 6018 tmp = FLOAT_ONE; 6019 break; 6020 case 2: 6021 tmp = FLOAT_TWO; 6022 break; 6023 default: 6024 tmp = FLOAT_ZERO; 6025 break; 6026 } 6027 /* Req 2 is the Smart Volume Setting req. */ 6028 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6029 ca0132_effects[idx].reqs[2], tmp); 6030 return 1; 6031} 6032 6033/* Sound Blaster Z EQ preset controls */ 6034static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6035 struct snd_ctl_elem_info *uinfo) 6036{ 6037 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6038 6039 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6040 uinfo->count = 1; 6041 uinfo->value.enumerated.items = items; 6042 if (uinfo->value.enumerated.item >= items) 6043 uinfo->value.enumerated.item = items - 1; 6044 strcpy(uinfo->value.enumerated.name, 6045 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6046 return 0; 6047} 6048 6049static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6050 struct snd_ctl_elem_value *ucontrol) 6051{ 6052 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6053 struct ca0132_spec *spec = codec->spec; 6054 6055 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6056 return 0; 6057} 6058 6059static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6060 struct snd_ctl_elem_value *ucontrol) 6061{ 6062 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6063 struct ca0132_spec *spec = codec->spec; 6064 int i, err = 0; 6065 int sel = ucontrol->value.enumerated.item[0]; 6066 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6067 6068 if (sel >= items) 6069 return 0; 6070 6071 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6072 ca0132_alt_eq_presets[sel].name); 6073 /* 6074 * Idx 0 is default. 6075 * Default needs to qualify with CrystalVoice state. 6076 */ 6077 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6078 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6079 ca0132_alt_eq_enum.reqs[i], 6080 ca0132_alt_eq_presets[sel].vals[i]); 6081 if (err < 0) 6082 break; 6083 } 6084 6085 if (err >= 0) 6086 spec->eq_preset_val = sel; 6087 6088 return 1; 6089} 6090 6091static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6092 struct snd_ctl_elem_info *uinfo) 6093{ 6094 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6095 6096 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6097 uinfo->count = 1; 6098 uinfo->value.enumerated.items = items; 6099 if (uinfo->value.enumerated.item >= items) 6100 uinfo->value.enumerated.item = items - 1; 6101 strcpy(uinfo->value.enumerated.name, 6102 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6103 return 0; 6104} 6105 6106static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6107 struct snd_ctl_elem_value *ucontrol) 6108{ 6109 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6110 struct ca0132_spec *spec = codec->spec; 6111 6112 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6113 return 0; 6114} 6115 6116static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6117 struct snd_ctl_elem_value *ucontrol) 6118{ 6119 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6120 struct ca0132_spec *spec = codec->spec; 6121 int i, err = 0; 6122 int sel = ucontrol->value.enumerated.item[0]; 6123 6124 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6125 return 0; 6126 6127 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6128 sel, ca0132_voicefx_presets[sel].name); 6129 6130 /* 6131 * Idx 0 is default. 6132 * Default needs to qualify with CrystalVoice state. 6133 */ 6134 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6135 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6136 ca0132_voicefx.reqs[i], 6137 ca0132_voicefx_presets[sel].vals[i]); 6138 if (err < 0) 6139 break; 6140 } 6141 6142 if (err >= 0) { 6143 spec->voicefx_val = sel; 6144 /* enable voice fx */ 6145 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6146 } 6147 6148 return 1; 6149} 6150 6151static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6152 struct snd_ctl_elem_value *ucontrol) 6153{ 6154 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6155 struct ca0132_spec *spec = codec->spec; 6156 hda_nid_t nid = get_amp_nid(kcontrol); 6157 int ch = get_amp_channels(kcontrol); 6158 long *valp = ucontrol->value.integer.value; 6159 6160 /* vnode */ 6161 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6162 if (ch & 1) { 6163 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6164 valp++; 6165 } 6166 if (ch & 2) { 6167 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6168 valp++; 6169 } 6170 return 0; 6171 } 6172 6173 /* effects, include PE and CrystalVoice */ 6174 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6175 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6176 return 0; 6177 } 6178 6179 /* mic boost */ 6180 if (nid == spec->input_pins[0]) { 6181 *valp = spec->cur_mic_boost; 6182 return 0; 6183 } 6184 6185 if (nid == ZXR_HEADPHONE_GAIN) { 6186 *valp = spec->zxr_gain_set; 6187 return 0; 6188 } 6189 6190 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6191 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6192 return 0; 6193 } 6194 6195 if (nid == BASS_REDIRECTION) { 6196 *valp = spec->bass_redirection_val; 6197 return 0; 6198 } 6199 6200 return 0; 6201} 6202 6203static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6204 struct snd_ctl_elem_value *ucontrol) 6205{ 6206 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6207 struct ca0132_spec *spec = codec->spec; 6208 hda_nid_t nid = get_amp_nid(kcontrol); 6209 int ch = get_amp_channels(kcontrol); 6210 long *valp = ucontrol->value.integer.value; 6211 int changed = 1; 6212 6213 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6214 nid, *valp); 6215 6216 snd_hda_power_up(codec); 6217 /* vnode */ 6218 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6219 if (ch & 1) { 6220 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6221 valp++; 6222 } 6223 if (ch & 2) { 6224 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6225 valp++; 6226 } 6227 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 6228 goto exit; 6229 } 6230 6231 /* PE */ 6232 if (nid == PLAY_ENHANCEMENT) { 6233 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6234 changed = ca0132_pe_switch_set(codec); 6235 goto exit; 6236 } 6237 6238 /* CrystalVoice */ 6239 if (nid == CRYSTAL_VOICE) { 6240 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6241 changed = ca0132_cvoice_switch_set(codec); 6242 goto exit; 6243 } 6244 6245 /* out and in effects */ 6246 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6247 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6248 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6249 changed = ca0132_effects_set(codec, nid, *valp); 6250 goto exit; 6251 } 6252 6253 /* mic boost */ 6254 if (nid == spec->input_pins[0]) { 6255 spec->cur_mic_boost = *valp; 6256 if (ca0132_use_alt_functions(spec)) { 6257 if (spec->in_enum_val != REAR_LINE_IN) 6258 changed = ca0132_mic_boost_set(codec, *valp); 6259 } else { 6260 /* Mic boost does not apply to Digital Mic */ 6261 if (spec->cur_mic_type != DIGITAL_MIC) 6262 changed = ca0132_mic_boost_set(codec, *valp); 6263 } 6264 6265 goto exit; 6266 } 6267 6268 if (nid == ZXR_HEADPHONE_GAIN) { 6269 spec->zxr_gain_set = *valp; 6270 if (spec->cur_out_type == HEADPHONE_OUT) 6271 changed = zxr_headphone_gain_set(codec, *valp); 6272 else 6273 changed = 0; 6274 6275 goto exit; 6276 } 6277 6278 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6279 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6280 if (spec->cur_out_type == SPEAKER_OUT) 6281 ca0132_alt_set_full_range_speaker(codec); 6282 6283 changed = 0; 6284 } 6285 6286 if (nid == BASS_REDIRECTION) { 6287 spec->bass_redirection_val = *valp; 6288 if (spec->cur_out_type == SPEAKER_OUT) 6289 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6290 6291 changed = 0; 6292 } 6293 6294exit: 6295 snd_hda_power_down(codec); 6296 return changed; 6297} 6298 6299/* 6300 * Volume related 6301 */ 6302/* 6303 * Sets the internal DSP decibel level to match the DAC for output, and the 6304 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6305 * all alternative codecs set DSP playback volume. 6306 */ 6307static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6308{ 6309 struct ca0132_spec *spec = codec->spec; 6310 unsigned int dsp_dir; 6311 unsigned int lookup_val; 6312 6313 if (nid == VNID_SPK) 6314 dsp_dir = DSP_VOL_OUT; 6315 else 6316 dsp_dir = DSP_VOL_IN; 6317 6318 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6319 6320 dspio_set_uint_param(codec, 6321 ca0132_alt_vol_ctls[dsp_dir].mid, 6322 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6323 float_vol_db_lookup[lookup_val]); 6324 6325 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6326 6327 dspio_set_uint_param(codec, 6328 ca0132_alt_vol_ctls[dsp_dir].mid, 6329 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6330 float_vol_db_lookup[lookup_val]); 6331 6332 dspio_set_uint_param(codec, 6333 ca0132_alt_vol_ctls[dsp_dir].mid, 6334 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6335} 6336 6337static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6338 struct snd_ctl_elem_info *uinfo) 6339{ 6340 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6341 struct ca0132_spec *spec = codec->spec; 6342 hda_nid_t nid = get_amp_nid(kcontrol); 6343 int ch = get_amp_channels(kcontrol); 6344 int dir = get_amp_direction(kcontrol); 6345 unsigned long pval; 6346 int err; 6347 6348 switch (nid) { 6349 case VNID_SPK: 6350 /* follow shared_out info */ 6351 nid = spec->shared_out_nid; 6352 mutex_lock(&codec->control_mutex); 6353 pval = kcontrol->private_value; 6354 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6355 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6356 kcontrol->private_value = pval; 6357 mutex_unlock(&codec->control_mutex); 6358 break; 6359 case VNID_MIC: 6360 /* follow shared_mic info */ 6361 nid = spec->shared_mic_nid; 6362 mutex_lock(&codec->control_mutex); 6363 pval = kcontrol->private_value; 6364 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6365 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6366 kcontrol->private_value = pval; 6367 mutex_unlock(&codec->control_mutex); 6368 break; 6369 default: 6370 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6371 } 6372 return err; 6373} 6374 6375static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6376 struct snd_ctl_elem_value *ucontrol) 6377{ 6378 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6379 struct ca0132_spec *spec = codec->spec; 6380 hda_nid_t nid = get_amp_nid(kcontrol); 6381 int ch = get_amp_channels(kcontrol); 6382 long *valp = ucontrol->value.integer.value; 6383 6384 /* store the left and right volume */ 6385 if (ch & 1) { 6386 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6387 valp++; 6388 } 6389 if (ch & 2) { 6390 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6391 valp++; 6392 } 6393 return 0; 6394} 6395 6396static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6397 struct snd_ctl_elem_value *ucontrol) 6398{ 6399 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6400 struct ca0132_spec *spec = codec->spec; 6401 hda_nid_t nid = get_amp_nid(kcontrol); 6402 int ch = get_amp_channels(kcontrol); 6403 long *valp = ucontrol->value.integer.value; 6404 hda_nid_t shared_nid = 0; 6405 bool effective; 6406 int changed = 1; 6407 6408 /* store the left and right volume */ 6409 if (ch & 1) { 6410 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6411 valp++; 6412 } 6413 if (ch & 2) { 6414 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6415 valp++; 6416 } 6417 6418 /* if effective conditions, then update hw immediately. */ 6419 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6420 if (effective) { 6421 int dir = get_amp_direction(kcontrol); 6422 unsigned long pval; 6423 6424 snd_hda_power_up(codec); 6425 mutex_lock(&codec->control_mutex); 6426 pval = kcontrol->private_value; 6427 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6428 0, dir); 6429 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6430 kcontrol->private_value = pval; 6431 mutex_unlock(&codec->control_mutex); 6432 snd_hda_power_down(codec); 6433 } 6434 6435 return changed; 6436} 6437 6438/* 6439 * This function is the same as the one above, because using an if statement 6440 * inside of the above volume control for the DSP volume would cause too much 6441 * lag. This is a lot more smooth. 6442 */ 6443static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6444 struct snd_ctl_elem_value *ucontrol) 6445{ 6446 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6447 struct ca0132_spec *spec = codec->spec; 6448 hda_nid_t nid = get_amp_nid(kcontrol); 6449 int ch = get_amp_channels(kcontrol); 6450 long *valp = ucontrol->value.integer.value; 6451 hda_nid_t vnid = 0; 6452 int changed; 6453 6454 switch (nid) { 6455 case 0x02: 6456 vnid = VNID_SPK; 6457 break; 6458 case 0x07: 6459 vnid = VNID_MIC; 6460 break; 6461 } 6462 6463 /* store the left and right volume */ 6464 if (ch & 1) { 6465 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6466 valp++; 6467 } 6468 if (ch & 2) { 6469 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6470 valp++; 6471 } 6472 6473 snd_hda_power_up(codec); 6474 ca0132_alt_dsp_volume_put(codec, vnid); 6475 mutex_lock(&codec->control_mutex); 6476 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6477 mutex_unlock(&codec->control_mutex); 6478 snd_hda_power_down(codec); 6479 6480 return changed; 6481} 6482 6483static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6484 unsigned int size, unsigned int __user *tlv) 6485{ 6486 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6487 struct ca0132_spec *spec = codec->spec; 6488 hda_nid_t nid = get_amp_nid(kcontrol); 6489 int ch = get_amp_channels(kcontrol); 6490 int dir = get_amp_direction(kcontrol); 6491 unsigned long pval; 6492 int err; 6493 6494 switch (nid) { 6495 case VNID_SPK: 6496 /* follow shared_out tlv */ 6497 nid = spec->shared_out_nid; 6498 mutex_lock(&codec->control_mutex); 6499 pval = kcontrol->private_value; 6500 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6501 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6502 kcontrol->private_value = pval; 6503 mutex_unlock(&codec->control_mutex); 6504 break; 6505 case VNID_MIC: 6506 /* follow shared_mic tlv */ 6507 nid = spec->shared_mic_nid; 6508 mutex_lock(&codec->control_mutex); 6509 pval = kcontrol->private_value; 6510 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6511 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6512 kcontrol->private_value = pval; 6513 mutex_unlock(&codec->control_mutex); 6514 break; 6515 default: 6516 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6517 } 6518 return err; 6519} 6520 6521/* Add volume slider control for effect level */ 6522static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6523 const char *pfx, int dir) 6524{ 6525 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6526 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6527 struct snd_kcontrol_new knew = 6528 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6529 6530 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6531 6532 knew.tlv.c = NULL; 6533 6534 switch (nid) { 6535 case XBASS_XOVER: 6536 knew.info = ca0132_alt_xbass_xover_slider_info; 6537 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6538 knew.put = ca0132_alt_xbass_xover_slider_put; 6539 break; 6540 default: 6541 knew.info = ca0132_alt_effect_slider_info; 6542 knew.get = ca0132_alt_slider_ctl_get; 6543 knew.put = ca0132_alt_effect_slider_put; 6544 knew.private_value = 6545 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6546 break; 6547 } 6548 6549 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6550} 6551 6552/* 6553 * Added FX: prefix for the alternative codecs, because otherwise the surround 6554 * effect would conflict with the Surround sound volume control. Also seems more 6555 * clear as to what the switches do. Left alone for others. 6556 */ 6557static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6558 const char *pfx, int dir) 6559{ 6560 struct ca0132_spec *spec = codec->spec; 6561 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6562 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6563 struct snd_kcontrol_new knew = 6564 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6565 /* If using alt_controls, add FX: prefix. But, don't add FX: 6566 * prefix to OutFX or InFX enable controls. 6567 */ 6568 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6569 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6570 else 6571 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6572 6573 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6574} 6575 6576static int add_voicefx(struct hda_codec *codec) 6577{ 6578 struct snd_kcontrol_new knew = 6579 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6580 VOICEFX, 1, 0, HDA_INPUT); 6581 knew.info = ca0132_voicefx_info; 6582 knew.get = ca0132_voicefx_get; 6583 knew.put = ca0132_voicefx_put; 6584 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6585} 6586 6587/* Create the EQ Preset control */ 6588static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6589{ 6590 struct snd_kcontrol_new knew = 6591 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6592 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6593 knew.info = ca0132_alt_eq_preset_info; 6594 knew.get = ca0132_alt_eq_preset_get; 6595 knew.put = ca0132_alt_eq_preset_put; 6596 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6597 snd_ctl_new1(&knew, codec)); 6598} 6599 6600/* 6601 * Add enumerated control for the three different settings of the smart volume 6602 * output effect. Normal just uses the slider value, and loud and night are 6603 * their own things that ignore that value. 6604 */ 6605static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6606{ 6607 struct snd_kcontrol_new knew = 6608 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6609 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6610 knew.info = ca0132_alt_svm_setting_info; 6611 knew.get = ca0132_alt_svm_setting_get; 6612 knew.put = ca0132_alt_svm_setting_put; 6613 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6614 snd_ctl_new1(&knew, codec)); 6615 6616} 6617 6618/* 6619 * Create an Output Select enumerated control for codecs with surround 6620 * out capabilities. 6621 */ 6622static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6623{ 6624 struct snd_kcontrol_new knew = 6625 HDA_CODEC_MUTE_MONO("Output Select", 6626 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6627 knew.info = ca0132_alt_output_select_get_info; 6628 knew.get = ca0132_alt_output_select_get; 6629 knew.put = ca0132_alt_output_select_put; 6630 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6631 snd_ctl_new1(&knew, codec)); 6632} 6633 6634/* 6635 * Add a control for selecting channel count on speaker output. Setting this 6636 * allows the DSP to do bass redirection and channel upmixing on surround 6637 * configurations. 6638 */ 6639static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6640{ 6641 struct snd_kcontrol_new knew = 6642 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6643 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6644 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6645 knew.get = ca0132_alt_speaker_channel_cfg_get; 6646 knew.put = ca0132_alt_speaker_channel_cfg_put; 6647 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6648 snd_ctl_new1(&knew, codec)); 6649} 6650 6651/* 6652 * Full range front stereo and rear surround switches. When these are set to 6653 * full range, the lower frequencies from these channels are no longer 6654 * redirected to the LFE channel. 6655 */ 6656static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6657{ 6658 struct snd_kcontrol_new knew = 6659 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6660 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6661 6662 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6663 snd_ctl_new1(&knew, codec)); 6664} 6665 6666static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6667{ 6668 struct snd_kcontrol_new knew = 6669 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6670 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6671 6672 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6673 snd_ctl_new1(&knew, codec)); 6674} 6675 6676/* 6677 * Bass redirection redirects audio below the crossover frequency to the LFE 6678 * channel on speakers that are set as not being full-range. On configurations 6679 * without an LFE channel, it does nothing. Bass redirection seems to be the 6680 * replacement for X-Bass on configurations with an LFE channel. 6681 */ 6682static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6683{ 6684 const char *namestr = "Bass Redirection Crossover"; 6685 struct snd_kcontrol_new knew = 6686 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6687 HDA_OUTPUT); 6688 6689 knew.tlv.c = NULL; 6690 knew.info = ca0132_alt_xbass_xover_slider_info; 6691 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6692 knew.put = ca0132_alt_xbass_xover_slider_put; 6693 6694 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6695 snd_ctl_new1(&knew, codec)); 6696} 6697 6698static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6699{ 6700 const char *namestr = "Bass Redirection"; 6701 struct snd_kcontrol_new knew = 6702 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6703 HDA_OUTPUT); 6704 6705 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6706 snd_ctl_new1(&knew, codec)); 6707} 6708 6709/* 6710 * Create an Input Source enumerated control for the alternate ca0132 codecs 6711 * because the front microphone has no auto-detect, and Line-in has to be set 6712 * somehow. 6713 */ 6714static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6715{ 6716 struct snd_kcontrol_new knew = 6717 HDA_CODEC_MUTE_MONO("Input Source", 6718 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6719 knew.info = ca0132_alt_input_source_info; 6720 knew.get = ca0132_alt_input_source_get; 6721 knew.put = ca0132_alt_input_source_put; 6722 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6723 snd_ctl_new1(&knew, codec)); 6724} 6725 6726/* 6727 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6728 * more control than the original mic boost, which is either full 30dB or off. 6729 */ 6730static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6731{ 6732 struct snd_kcontrol_new knew = 6733 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6734 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6735 knew.info = ca0132_alt_mic_boost_info; 6736 knew.get = ca0132_alt_mic_boost_get; 6737 knew.put = ca0132_alt_mic_boost_put; 6738 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6739 snd_ctl_new1(&knew, codec)); 6740 6741} 6742 6743/* 6744 * Add headphone gain enumerated control for the AE-5. This switches between 6745 * three modes, low, medium, and high. When non-headphone outputs are selected, 6746 * it is automatically set to high. This is the same behavior as Windows. 6747 */ 6748static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6749{ 6750 struct snd_kcontrol_new knew = 6751 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6752 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6753 knew.info = ae5_headphone_gain_info; 6754 knew.get = ae5_headphone_gain_get; 6755 knew.put = ae5_headphone_gain_put; 6756 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6757 snd_ctl_new1(&knew, codec)); 6758} 6759 6760/* 6761 * Add sound filter enumerated control for the AE-5. This adds three different 6762 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6763 * read into it, it changes the DAC's interpolation filter. 6764 */ 6765static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6766{ 6767 struct snd_kcontrol_new knew = 6768 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6769 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6770 knew.info = ae5_sound_filter_info; 6771 knew.get = ae5_sound_filter_get; 6772 knew.put = ae5_sound_filter_put; 6773 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6774 snd_ctl_new1(&knew, codec)); 6775} 6776 6777static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6778{ 6779 struct snd_kcontrol_new knew = 6780 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6781 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6782 6783 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6784 snd_ctl_new1(&knew, codec)); 6785} 6786 6787/* 6788 * Need to create follower controls for the alternate codecs that have surround 6789 * capabilities. 6790 */ 6791static const char * const ca0132_alt_follower_pfxs[] = { 6792 "Front", "Surround", "Center", "LFE", NULL, 6793}; 6794 6795/* 6796 * Also need special channel map, because the default one is incorrect. 6797 * I think this has to do with the pin for rear surround being 0x11, 6798 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6799 */ 6800static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6801 { .channels = 2, 6802 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6803 { .channels = 4, 6804 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6805 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6806 { .channels = 6, 6807 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6808 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6809 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6810 { } 6811}; 6812 6813/* Add the correct chmap for streams with 6 channels. */ 6814static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6815{ 6816 int err = 0; 6817 struct hda_pcm *pcm; 6818 6819 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6820 struct hda_pcm_stream *hinfo = 6821 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6822 struct snd_pcm_chmap *chmap; 6823 const struct snd_pcm_chmap_elem *elem; 6824 6825 elem = ca0132_alt_chmaps; 6826 if (hinfo->channels_max == 6) { 6827 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6828 SNDRV_PCM_STREAM_PLAYBACK, 6829 elem, hinfo->channels_max, 0, &chmap); 6830 if (err < 0) 6831 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6832 } 6833 } 6834} 6835 6836/* 6837 * When changing Node IDs for Mixer Controls below, make sure to update 6838 * Node IDs in ca0132_config() as well. 6839 */ 6840static const struct snd_kcontrol_new ca0132_mixer[] = { 6841 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6842 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6843 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6844 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6845 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6846 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6847 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6848 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6849 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6850 0x12, 1, HDA_INPUT), 6851 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6852 VNID_HP_SEL, 1, HDA_OUTPUT), 6853 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6854 VNID_AMIC1_SEL, 1, HDA_INPUT), 6855 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6856 VNID_HP_ASEL, 1, HDA_OUTPUT), 6857 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6858 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6859 { } /* end */ 6860}; 6861 6862/* 6863 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6864 * surround controls. Also sets both the Front Playback and Capture Volume 6865 * controls to alt so they set the DSP's decibel level. 6866 */ 6867static const struct snd_kcontrol_new desktop_mixer[] = { 6868 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6869 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6870 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6871 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6872 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6873 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6874 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6875 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6876 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6877 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6878 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6879 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6880 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6881 VNID_HP_ASEL, 1, HDA_OUTPUT), 6882 { } /* end */ 6883}; 6884 6885/* 6886 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6887 * because it doesn't set decibel levels for the DSP for capture. 6888 */ 6889static const struct snd_kcontrol_new r3di_mixer[] = { 6890 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6891 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6892 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6893 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6894 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6895 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6896 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6897 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6898 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6899 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6900 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6901 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6902 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6903 VNID_HP_ASEL, 1, HDA_OUTPUT), 6904 { } /* end */ 6905}; 6906 6907static int ca0132_build_controls(struct hda_codec *codec) 6908{ 6909 struct ca0132_spec *spec = codec->spec; 6910 int i, num_fx, num_sliders; 6911 int err = 0; 6912 6913 /* Add Mixer controls */ 6914 for (i = 0; i < spec->num_mixers; i++) { 6915 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 6916 if (err < 0) 6917 return err; 6918 } 6919 /* Setup vmaster with surround followers for desktop ca0132 devices */ 6920 if (ca0132_use_alt_functions(spec)) { 6921 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 6922 spec->tlv); 6923 snd_hda_add_vmaster(codec, "Master Playback Volume", 6924 spec->tlv, ca0132_alt_follower_pfxs, 6925 "Playback Volume"); 6926 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 6927 NULL, ca0132_alt_follower_pfxs, 6928 "Playback Switch", 6929 true, &spec->vmaster_mute.sw_kctl); 6930 if (err < 0) 6931 return err; 6932 } 6933 6934 /* Add in and out effects controls. 6935 * VoiceFX, PE and CrystalVoice are added separately. 6936 */ 6937 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6938 for (i = 0; i < num_fx; i++) { 6939 /* Desktop cards break if Echo Cancellation is used. */ 6940 if (ca0132_use_pci_mmio(spec)) { 6941 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 6942 OUT_EFFECTS_COUNT)) 6943 continue; 6944 } 6945 6946 err = add_fx_switch(codec, ca0132_effects[i].nid, 6947 ca0132_effects[i].name, 6948 ca0132_effects[i].direct); 6949 if (err < 0) 6950 return err; 6951 } 6952 /* 6953 * If codec has use_alt_controls set to true, add effect level sliders, 6954 * EQ presets, and Smart Volume presets. Also, change names to add FX 6955 * prefix, and change PlayEnhancement and CrystalVoice to match. 6956 */ 6957 if (ca0132_use_alt_controls(spec)) { 6958 err = ca0132_alt_add_svm_enum(codec); 6959 if (err < 0) 6960 return err; 6961 6962 err = add_ca0132_alt_eq_presets(codec); 6963 if (err < 0) 6964 return err; 6965 6966 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6967 "Enable OutFX", 0); 6968 if (err < 0) 6969 return err; 6970 6971 err = add_fx_switch(codec, CRYSTAL_VOICE, 6972 "Enable InFX", 1); 6973 if (err < 0) 6974 return err; 6975 6976 num_sliders = OUT_EFFECTS_COUNT - 1; 6977 for (i = 0; i < num_sliders; i++) { 6978 err = ca0132_alt_add_effect_slider(codec, 6979 ca0132_effects[i].nid, 6980 ca0132_effects[i].name, 6981 ca0132_effects[i].direct); 6982 if (err < 0) 6983 return err; 6984 } 6985 6986 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 6987 "X-Bass Crossover", EFX_DIR_OUT); 6988 6989 if (err < 0) 6990 return err; 6991 } else { 6992 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6993 "PlayEnhancement", 0); 6994 if (err < 0) 6995 return err; 6996 6997 err = add_fx_switch(codec, CRYSTAL_VOICE, 6998 "CrystalVoice", 1); 6999 if (err < 0) 7000 return err; 7001 } 7002 err = add_voicefx(codec); 7003 if (err < 0) 7004 return err; 7005 7006 /* 7007 * If the codec uses alt_functions, you need the enumerated controls 7008 * to select the new outputs and inputs, plus add the new mic boost 7009 * setting control. 7010 */ 7011 if (ca0132_use_alt_functions(spec)) { 7012 err = ca0132_alt_add_output_enum(codec); 7013 if (err < 0) 7014 return err; 7015 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7016 if (err < 0) 7017 return err; 7018 err = ca0132_alt_add_front_full_range_switch(codec); 7019 if (err < 0) 7020 return err; 7021 err = ca0132_alt_add_rear_full_range_switch(codec); 7022 if (err < 0) 7023 return err; 7024 err = ca0132_alt_add_bass_redirection_crossover(codec); 7025 if (err < 0) 7026 return err; 7027 err = ca0132_alt_add_bass_redirection_switch(codec); 7028 if (err < 0) 7029 return err; 7030 err = ca0132_alt_add_mic_boost_enum(codec); 7031 if (err < 0) 7032 return err; 7033 /* 7034 * ZxR only has microphone input, there is no front panel 7035 * header on the card, and aux-in is handled by the DBPro board. 7036 */ 7037 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7038 err = ca0132_alt_add_input_enum(codec); 7039 if (err < 0) 7040 return err; 7041 } 7042 } 7043 7044 switch (ca0132_quirk(spec)) { 7045 case QUIRK_AE5: 7046 case QUIRK_AE7: 7047 err = ae5_add_headphone_gain_enum(codec); 7048 if (err < 0) 7049 return err; 7050 err = ae5_add_sound_filter_enum(codec); 7051 if (err < 0) 7052 return err; 7053 break; 7054 case QUIRK_ZXR: 7055 err = zxr_add_headphone_gain_switch(codec); 7056 if (err < 0) 7057 return err; 7058 break; 7059 default: 7060 break; 7061 } 7062 7063#ifdef ENABLE_TUNING_CONTROLS 7064 add_tuning_ctls(codec); 7065#endif 7066 7067 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7068 if (err < 0) 7069 return err; 7070 7071 if (spec->dig_out) { 7072 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7073 spec->dig_out); 7074 if (err < 0) 7075 return err; 7076 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7077 if (err < 0) 7078 return err; 7079 /* spec->multiout.share_spdif = 1; */ 7080 } 7081 7082 if (spec->dig_in) { 7083 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7084 if (err < 0) 7085 return err; 7086 } 7087 7088 if (ca0132_use_alt_functions(spec)) 7089 ca0132_alt_add_chmap_ctls(codec); 7090 7091 return 0; 7092} 7093 7094static int dbpro_build_controls(struct hda_codec *codec) 7095{ 7096 struct ca0132_spec *spec = codec->spec; 7097 int err = 0; 7098 7099 if (spec->dig_out) { 7100 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7101 spec->dig_out); 7102 if (err < 0) 7103 return err; 7104 } 7105 7106 if (spec->dig_in) { 7107 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7108 if (err < 0) 7109 return err; 7110 } 7111 7112 return 0; 7113} 7114 7115/* 7116 * PCM 7117 */ 7118static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7119 .substreams = 1, 7120 .channels_min = 2, 7121 .channels_max = 6, 7122 .ops = { 7123 .prepare = ca0132_playback_pcm_prepare, 7124 .cleanup = ca0132_playback_pcm_cleanup, 7125 .get_delay = ca0132_playback_pcm_delay, 7126 }, 7127}; 7128 7129static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7130 .substreams = 1, 7131 .channels_min = 2, 7132 .channels_max = 2, 7133 .ops = { 7134 .prepare = ca0132_capture_pcm_prepare, 7135 .cleanup = ca0132_capture_pcm_cleanup, 7136 .get_delay = ca0132_capture_pcm_delay, 7137 }, 7138}; 7139 7140static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7141 .substreams = 1, 7142 .channels_min = 2, 7143 .channels_max = 2, 7144 .ops = { 7145 .open = ca0132_dig_playback_pcm_open, 7146 .close = ca0132_dig_playback_pcm_close, 7147 .prepare = ca0132_dig_playback_pcm_prepare, 7148 .cleanup = ca0132_dig_playback_pcm_cleanup 7149 }, 7150}; 7151 7152static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7153 .substreams = 1, 7154 .channels_min = 2, 7155 .channels_max = 2, 7156}; 7157 7158static int ca0132_build_pcms(struct hda_codec *codec) 7159{ 7160 struct ca0132_spec *spec = codec->spec; 7161 struct hda_pcm *info; 7162 7163 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7164 if (!info) 7165 return -ENOMEM; 7166 if (ca0132_use_alt_functions(spec)) { 7167 info->own_chmap = true; 7168 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7169 = ca0132_alt_chmaps; 7170 } 7171 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7172 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7173 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7174 spec->multiout.max_channels; 7175 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7176 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7177 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7178 7179 /* With the DSP enabled, desktops don't use this ADC. */ 7180 if (!ca0132_use_alt_functions(spec)) { 7181 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7182 if (!info) 7183 return -ENOMEM; 7184 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7185 ca0132_pcm_analog_capture; 7186 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7187 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7188 } 7189 7190 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7191 if (!info) 7192 return -ENOMEM; 7193 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7194 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7195 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7196 7197 if (!spec->dig_out && !spec->dig_in) 7198 return 0; 7199 7200 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7201 if (!info) 7202 return -ENOMEM; 7203 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7204 if (spec->dig_out) { 7205 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7206 ca0132_pcm_digital_playback; 7207 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7208 } 7209 if (spec->dig_in) { 7210 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7211 ca0132_pcm_digital_capture; 7212 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7213 } 7214 7215 return 0; 7216} 7217 7218static int dbpro_build_pcms(struct hda_codec *codec) 7219{ 7220 struct ca0132_spec *spec = codec->spec; 7221 struct hda_pcm *info; 7222 7223 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7224 if (!info) 7225 return -ENOMEM; 7226 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7227 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7228 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7229 7230 7231 if (!spec->dig_out && !spec->dig_in) 7232 return 0; 7233 7234 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7235 if (!info) 7236 return -ENOMEM; 7237 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7238 if (spec->dig_out) { 7239 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7240 ca0132_pcm_digital_playback; 7241 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7242 } 7243 if (spec->dig_in) { 7244 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7245 ca0132_pcm_digital_capture; 7246 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7247 } 7248 7249 return 0; 7250} 7251 7252static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7253{ 7254 if (pin) { 7255 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7256 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7257 snd_hda_codec_write(codec, pin, 0, 7258 AC_VERB_SET_AMP_GAIN_MUTE, 7259 AMP_OUT_UNMUTE); 7260 } 7261 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7262 snd_hda_codec_write(codec, dac, 0, 7263 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7264} 7265 7266static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7267{ 7268 if (pin) { 7269 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7270 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7271 snd_hda_codec_write(codec, pin, 0, 7272 AC_VERB_SET_AMP_GAIN_MUTE, 7273 AMP_IN_UNMUTE(0)); 7274 } 7275 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7276 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7277 AMP_IN_UNMUTE(0)); 7278 7279 /* init to 0 dB and unmute. */ 7280 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7281 HDA_AMP_VOLMASK, 0x5a); 7282 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7283 HDA_AMP_MUTE, 0); 7284 } 7285} 7286 7287static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7288{ 7289 unsigned int caps; 7290 7291 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7292 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7293 snd_hda_override_amp_caps(codec, nid, dir, caps); 7294} 7295 7296/* 7297 * Switch between Digital built-in mic and analog mic. 7298 */ 7299static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7300{ 7301 struct ca0132_spec *spec = codec->spec; 7302 unsigned int tmp; 7303 u8 val; 7304 unsigned int oldval; 7305 7306 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7307 7308 oldval = stop_mic1(codec); 7309 ca0132_set_vipsource(codec, 0); 7310 if (enable) { 7311 /* set DMic input as 2-ch */ 7312 tmp = FLOAT_TWO; 7313 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7314 7315 val = spec->dmic_ctl; 7316 val |= 0x80; 7317 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7318 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7319 7320 if (!(spec->dmic_ctl & 0x20)) 7321 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7322 } else { 7323 /* set AMic input as mono */ 7324 tmp = FLOAT_ONE; 7325 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7326 7327 val = spec->dmic_ctl; 7328 /* clear bit7 and bit5 to disable dmic */ 7329 val &= 0x5f; 7330 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7331 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7332 7333 if (!(spec->dmic_ctl & 0x20)) 7334 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7335 } 7336 ca0132_set_vipsource(codec, 1); 7337 resume_mic1(codec, oldval); 7338} 7339 7340/* 7341 * Initialization for Digital Mic. 7342 */ 7343static void ca0132_init_dmic(struct hda_codec *codec) 7344{ 7345 struct ca0132_spec *spec = codec->spec; 7346 u8 val; 7347 7348 /* Setup Digital Mic here, but don't enable. 7349 * Enable based on jack detect. 7350 */ 7351 7352 /* MCLK uses MPIO1, set to enable. 7353 * Bit 2-0: MPIO select 7354 * Bit 3: set to disable 7355 * Bit 7-4: reserved 7356 */ 7357 val = 0x01; 7358 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7359 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7360 7361 /* Data1 uses MPIO3. Data2 not use 7362 * Bit 2-0: Data1 MPIO select 7363 * Bit 3: set disable Data1 7364 * Bit 6-4: Data2 MPIO select 7365 * Bit 7: set disable Data2 7366 */ 7367 val = 0x83; 7368 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7369 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7370 7371 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7372 * Bit 3-0: Channel mask 7373 * Bit 4: set for 48KHz, clear for 32KHz 7374 * Bit 5: mode 7375 * Bit 6: set to select Data2, clear for Data1 7376 * Bit 7: set to enable DMic, clear for AMic 7377 */ 7378 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7379 val = 0x33; 7380 else 7381 val = 0x23; 7382 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7383 spec->dmic_ctl = val; 7384 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7385 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7386} 7387 7388/* 7389 * Initialization for Analog Mic 2 7390 */ 7391static void ca0132_init_analog_mic2(struct hda_codec *codec) 7392{ 7393 struct ca0132_spec *spec = codec->spec; 7394 7395 mutex_lock(&spec->chipio_mutex); 7396 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7397 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 7398 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7399 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 7400 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7401 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 7402 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7403 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 7404 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7405 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 7406 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7407 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 7408 mutex_unlock(&spec->chipio_mutex); 7409} 7410 7411static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7412{ 7413 struct ca0132_spec *spec = codec->spec; 7414 int i; 7415 7416 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7417 snd_hda_codec_update_widgets(codec); 7418 7419 for (i = 0; i < spec->multiout.num_dacs; i++) 7420 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7421 7422 for (i = 0; i < spec->num_outputs; i++) 7423 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7424 7425 for (i = 0; i < spec->num_inputs; i++) { 7426 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7427 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7428 } 7429} 7430 7431/* 7432 * Default speaker tuning values setup for alternative codecs. 7433 */ 7434static const unsigned int sbz_default_delay_values[] = { 7435 /* Non-zero values are floating point 0.000198. */ 7436 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7437}; 7438 7439static const unsigned int zxr_default_delay_values[] = { 7440 /* Non-zero values are floating point 0.000220. */ 7441 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7442}; 7443 7444static const unsigned int ae5_default_delay_values[] = { 7445 /* Non-zero values are floating point 0.000100. */ 7446 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7447}; 7448 7449/* 7450 * If we never change these, probably only need them on initialization. 7451 */ 7452static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7453{ 7454 struct ca0132_spec *spec = codec->spec; 7455 unsigned int i, tmp, start_req, end_req; 7456 const unsigned int *values; 7457 7458 switch (ca0132_quirk(spec)) { 7459 case QUIRK_SBZ: 7460 values = sbz_default_delay_values; 7461 break; 7462 case QUIRK_ZXR: 7463 values = zxr_default_delay_values; 7464 break; 7465 case QUIRK_AE5: 7466 case QUIRK_AE7: 7467 values = ae5_default_delay_values; 7468 break; 7469 default: 7470 values = sbz_default_delay_values; 7471 break; 7472 } 7473 7474 tmp = FLOAT_ZERO; 7475 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7476 7477 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7478 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7479 for (i = start_req; i < end_req + 1; i++) 7480 dspio_set_uint_param(codec, 0x96, i, tmp); 7481 7482 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7483 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7484 for (i = start_req; i < end_req + 1; i++) 7485 dspio_set_uint_param(codec, 0x96, i, tmp); 7486 7487 7488 for (i = 0; i < 6; i++) 7489 dspio_set_uint_param(codec, 0x96, 7490 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7491} 7492 7493/* 7494 * Creates a dummy stream to bind the output to. This seems to have to be done 7495 * after changing the main outputs source and destination streams. 7496 */ 7497static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) 7498{ 7499 struct ca0132_spec *spec = codec->spec; 7500 unsigned int stream_format; 7501 7502 stream_format = snd_hdac_calc_stream_format(48000, 2, 7503 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 7504 7505 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 7506 0, stream_format); 7507 7508 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 7509} 7510 7511/* 7512 * Initialize mic for non-chromebook ca0132 implementations. 7513 */ 7514static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7515{ 7516 struct ca0132_spec *spec = codec->spec; 7517 unsigned int tmp; 7518 7519 /* Mic 1 Setup */ 7520 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7521 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7522 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7523 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7524 tmp = FLOAT_ONE; 7525 } else 7526 tmp = FLOAT_THREE; 7527 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7528 7529 /* Mic 2 setup (not present on desktop cards) */ 7530 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7531 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7532 if (ca0132_quirk(spec) == QUIRK_R3DI) 7533 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7534 tmp = FLOAT_ZERO; 7535 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7536} 7537 7538/* 7539 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7540 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7541 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7542 * having an updated DAC, which changes the destination to that DAC. 7543 */ 7544static void sbz_connect_streams(struct hda_codec *codec) 7545{ 7546 struct ca0132_spec *spec = codec->spec; 7547 7548 mutex_lock(&spec->chipio_mutex); 7549 7550 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7551 7552 chipio_set_stream_channels(codec, 0x0C, 6); 7553 chipio_set_stream_control(codec, 0x0C, 1); 7554 7555 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7556 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7557 7558 /* Setup stream 0x14 with it's source and destination points */ 7559 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7560 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7561 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7562 chipio_set_stream_channels(codec, 0x14, 2); 7563 chipio_set_stream_control(codec, 0x14, 1); 7564 7565 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7566 7567 mutex_unlock(&spec->chipio_mutex); 7568} 7569 7570/* 7571 * Write data through ChipIO to setup proper stream destinations. 7572 * Not sure how it exactly works, but it seems to direct data 7573 * to different destinations. Example is f8 to c0, e0 to c0. 7574 * All I know is, if you don't set these, you get no sound. 7575 */ 7576static void sbz_chipio_startup_data(struct hda_codec *codec) 7577{ 7578 struct ca0132_spec *spec = codec->spec; 7579 7580 mutex_lock(&spec->chipio_mutex); 7581 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7582 7583 /* These control audio output */ 7584 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 7585 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 7586 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 7587 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 7588 /* Signal to update I think */ 7589 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7590 7591 chipio_set_stream_channels(codec, 0x0C, 6); 7592 chipio_set_stream_control(codec, 0x0C, 1); 7593 /* No clue what these control */ 7594 if (ca0132_quirk(spec) == QUIRK_SBZ) { 7595 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 7596 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 7597 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 7598 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 7599 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 7600 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 7601 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 7602 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 7603 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 7604 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 7605 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 7606 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 7607 } else if (ca0132_quirk(spec) == QUIRK_ZXR) { 7608 chipio_write_no_mutex(codec, 0x190038, 0x000140c2); 7609 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); 7610 chipio_write_no_mutex(codec, 0x190040, 0x000150c4); 7611 chipio_write_no_mutex(codec, 0x190044, 0x000151c5); 7612 chipio_write_no_mutex(codec, 0x190050, 0x000142c8); 7613 chipio_write_no_mutex(codec, 0x190054, 0x000143c9); 7614 chipio_write_no_mutex(codec, 0x190058, 0x000152ca); 7615 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); 7616 } 7617 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7618 7619 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7620 mutex_unlock(&spec->chipio_mutex); 7621} 7622 7623/* 7624 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is 7625 * done after the DSP is loaded. 7626 */ 7627static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) 7628{ 7629 struct ca0132_spec *spec = codec->spec; 7630 unsigned int tmp, i; 7631 7632 /* 7633 * Gotta run these twice, or else mic works inconsistently. Not clear 7634 * why this is, but multiple tests have confirmed it. 7635 */ 7636 for (i = 0; i < 2; i++) { 7637 switch (ca0132_quirk(spec)) { 7638 case QUIRK_SBZ: 7639 case QUIRK_AE5: 7640 case QUIRK_AE7: 7641 tmp = 0x00000003; 7642 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7643 tmp = 0x00000000; 7644 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7645 tmp = 0x00000001; 7646 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7647 tmp = 0x00000004; 7648 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7649 tmp = 0x00000005; 7650 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7651 tmp = 0x00000000; 7652 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7653 break; 7654 case QUIRK_R3D: 7655 case QUIRK_R3DI: 7656 tmp = 0x00000000; 7657 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7658 tmp = 0x00000001; 7659 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7660 tmp = 0x00000004; 7661 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7662 tmp = 0x00000005; 7663 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7664 tmp = 0x00000000; 7665 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7666 break; 7667 default: 7668 break; 7669 } 7670 msleep(100); 7671 } 7672} 7673 7674static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7675{ 7676 struct ca0132_spec *spec = codec->spec; 7677 unsigned int tmp; 7678 7679 chipio_set_stream_control(codec, 0x03, 0); 7680 chipio_set_stream_control(codec, 0x04, 0); 7681 7682 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7683 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7684 7685 tmp = FLOAT_THREE; 7686 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7687 7688 chipio_set_stream_control(codec, 0x03, 1); 7689 chipio_set_stream_control(codec, 0x04, 1); 7690 7691 switch (ca0132_quirk(spec)) { 7692 case QUIRK_SBZ: 7693 chipio_write(codec, 0x18b098, 0x0000000c); 7694 chipio_write(codec, 0x18b09C, 0x0000000c); 7695 break; 7696 case QUIRK_AE5: 7697 chipio_write(codec, 0x18b098, 0x0000000c); 7698 chipio_write(codec, 0x18b09c, 0x0000004c); 7699 break; 7700 default: 7701 break; 7702 } 7703} 7704 7705static void ae5_post_dsp_register_set(struct hda_codec *codec) 7706{ 7707 struct ca0132_spec *spec = codec->spec; 7708 7709 chipio_8051_write_direct(codec, 0x93, 0x10); 7710 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7711 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 7712 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7713 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 7714 7715 writeb(0xff, spec->mem_base + 0x304); 7716 writeb(0xff, spec->mem_base + 0x304); 7717 writeb(0xff, spec->mem_base + 0x304); 7718 writeb(0xff, spec->mem_base + 0x304); 7719 writeb(0x00, spec->mem_base + 0x100); 7720 writeb(0xff, spec->mem_base + 0x304); 7721 writeb(0x00, spec->mem_base + 0x100); 7722 writeb(0xff, spec->mem_base + 0x304); 7723 writeb(0x00, spec->mem_base + 0x100); 7724 writeb(0xff, spec->mem_base + 0x304); 7725 writeb(0x00, spec->mem_base + 0x100); 7726 writeb(0xff, spec->mem_base + 0x304); 7727 7728 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7729 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7730 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7731} 7732 7733static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7734{ 7735 /* 7736 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7737 * which seems to be 'multichannel'. This is also mentioned in the 7738 * AE-5's registry values in Windows. 7739 */ 7740 chipio_set_control_param(codec, 3, 0); 7741 /* 7742 * I believe ASI is 'audio serial interface' and that it's used to 7743 * change colors on the external LED strip connected to the AE-5. 7744 */ 7745 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7746 7747 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7748 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7749 7750 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7751 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 7752 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7753 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 7754 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7755 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 7756} 7757 7758static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7759{ 7760 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7761 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 7762 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7763 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 7764 7765 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7766 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45); 7767 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7768 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc); 7769 7770 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7771 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40); 7772 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7773 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb); 7774 7775 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7776 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7777 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7778 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7779 7780 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7781 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51); 7782 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7783 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d); 7784} 7785 7786static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7787{ 7788 struct ca0132_spec *spec = codec->spec; 7789 7790 mutex_lock(&spec->chipio_mutex); 7791 7792 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7793 7794 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7795 7796 chipio_set_stream_channels(codec, 0x0C, 6); 7797 chipio_set_stream_control(codec, 0x0C, 1); 7798 7799 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7800 7801 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7802 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7803 chipio_set_stream_channels(codec, 0x18, 6); 7804 chipio_set_stream_control(codec, 0x18, 1); 7805 7806 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7807 7808 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7809 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7810 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7811 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7812 7813 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7814 7815 mutex_unlock(&spec->chipio_mutex); 7816} 7817 7818static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7819{ 7820 struct ca0132_spec *spec = codec->spec; 7821 7822 mutex_lock(&spec->chipio_mutex); 7823 7824 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7825 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7826 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7827 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7828 7829 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7830 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7831 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7832 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7833 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7834 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7835 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7836 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7837 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7838 ca0113_mmio_gpio_set(codec, 0, true); 7839 ca0113_mmio_gpio_set(codec, 1, true); 7840 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7841 7842 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7843 7844 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7845 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7846 7847 mutex_unlock(&spec->chipio_mutex); 7848} 7849 7850static const unsigned int ae7_port_set_data[] = { 7851 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5, 7852 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb 7853}; 7854 7855static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 7856{ 7857 struct ca0132_spec *spec = codec->spec; 7858 unsigned int i, count, addr; 7859 7860 mutex_lock(&spec->chipio_mutex); 7861 7862 chipio_set_stream_channels(codec, 0x0c, 6); 7863 chipio_set_stream_control(codec, 0x0c, 1); 7864 7865 count = ARRAY_SIZE(ae7_port_set_data); 7866 addr = 0x190030; 7867 for (i = 0; i < count; i++) { 7868 chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]); 7869 7870 /* Addresses are incremented by 4-bytes. */ 7871 addr += 0x04; 7872 } 7873 7874 /* 7875 * Port setting always ends with a write of 0x1 to address 0x19042c. 7876 */ 7877 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7878 7879 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7880 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 7881 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 7882 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 7883 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 7884 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 7885 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 7886 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 7887 7888 mutex_unlock(&spec->chipio_mutex); 7889} 7890 7891static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 7892{ 7893 struct ca0132_spec *spec = codec->spec; 7894 7895 mutex_lock(&spec->chipio_mutex); 7896 7897 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7898 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 7899 7900 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7901 chipio_set_stream_channels(codec, 0x0c, 6); 7902 chipio_set_stream_control(codec, 0x0c, 1); 7903 7904 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 7905 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 7906 7907 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7908 chipio_set_stream_channels(codec, 0x18, 6); 7909 chipio_set_stream_control(codec, 0x18, 1); 7910 7911 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7912 7913 mutex_unlock(&spec->chipio_mutex); 7914} 7915 7916static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 7917{ 7918 static const unsigned int addr[] = { 7919 0x41, 0x45, 0x40, 0x43, 0x51 7920 }; 7921 static const unsigned int data[] = { 7922 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 7923 }; 7924 unsigned int i; 7925 7926 for (i = 0; i < ARRAY_SIZE(addr); i++) { 7927 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7928 VENDOR_CHIPIO_8051_ADDRESS_LOW, addr[i]); 7929 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7930 VENDOR_CHIPIO_PLL_PMU_WRITE, data[i]); 7931 } 7932} 7933 7934static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 7935{ 7936 struct ca0132_spec *spec = codec->spec; 7937 static const unsigned int target[] = { 7938 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 7939 }; 7940 static const unsigned int data[] = { 7941 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 7942 }; 7943 unsigned int i; 7944 7945 mutex_lock(&spec->chipio_mutex); 7946 7947 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7948 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7949 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7950 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7951 7952 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7953 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7954 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7955 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7956 7957 ae7_post_dsp_pll_setup(codec); 7958 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7959 7960 for (i = 0; i < ARRAY_SIZE(target); i++) 7961 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 7962 7963 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 7964 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7965 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7966 7967 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 7968 chipio_set_stream_channels(codec, 0x21, 2); 7969 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 7970 7971 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 7972 /* 7973 * In the 8051's memory, this param is referred to as 'n2sid', which I 7974 * believe is 'node to streamID'. It seems to be a way to assign a 7975 * stream to a given HDA node. 7976 */ 7977 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 7978 7979 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 7980 7981 /* 7982 * Now, at this point on Windows, an actual stream is setup and 7983 * seemingly sends data to the HDA node 0x09, which is the digital 7984 * audio input node. This is left out here, because obviously I don't 7985 * know what data is being sent. Interestingly, the AE-5 seems to go 7986 * through the motions of getting here and never actually takes this 7987 * step, but the AE-7 does. 7988 */ 7989 7990 ca0113_mmio_gpio_set(codec, 0, 1); 7991 ca0113_mmio_gpio_set(codec, 1, 1); 7992 7993 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 7994 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 7995 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7996 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7997 7998 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 7999 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8000 8001 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8002 chipio_set_stream_channels(codec, 0x18, 6); 8003 8004 /* 8005 * Runs again, this has been repeated a few times, but I'm just 8006 * following what the Windows driver does. 8007 */ 8008 ae7_post_dsp_pll_setup(codec); 8009 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8010 8011 mutex_unlock(&spec->chipio_mutex); 8012} 8013 8014/* 8015 * The Windows driver has commands that seem to setup ASI, which I believe to 8016 * be some sort of audio serial interface. My current speculation is that it's 8017 * related to communicating with the new DAC. 8018 */ 8019static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8020{ 8021 chipio_8051_write_direct(codec, 0x93, 0x10); 8022 8023 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8024 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 8025 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8026 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 8027 8028 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8029 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8030 8031 chipio_set_control_param(codec, 3, 3); 8032 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8033 8034 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8035 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8036 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8037 8038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8039 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 8040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8041 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 8042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8043 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 8044 8045 ae7_post_dsp_pll_setup(codec); 8046 ae7_post_dsp_asi_stream_setup(codec); 8047 8048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8049 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 8050 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8051 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 8052 8053 ae7_post_dsp_asi_setup_ports(codec); 8054} 8055 8056/* 8057 * Setup default parameters for DSP 8058 */ 8059static void ca0132_setup_defaults(struct hda_codec *codec) 8060{ 8061 struct ca0132_spec *spec = codec->spec; 8062 unsigned int tmp; 8063 int num_fx; 8064 int idx, i; 8065 8066 if (spec->dsp_state != DSP_DOWNLOADED) 8067 return; 8068 8069 /* out, in effects + voicefx */ 8070 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8071 for (idx = 0; idx < num_fx; idx++) { 8072 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8073 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8074 ca0132_effects[idx].reqs[i], 8075 ca0132_effects[idx].def_vals[i]); 8076 } 8077 } 8078 8079 /*remove DSP headroom*/ 8080 tmp = FLOAT_ZERO; 8081 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8082 8083 /*set speaker EQ bypass attenuation*/ 8084 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8085 8086 /* set AMic1 and AMic2 as mono mic */ 8087 tmp = FLOAT_ONE; 8088 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8089 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8090 8091 /* set AMic1 as CrystalVoice input */ 8092 tmp = FLOAT_ONE; 8093 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8094 8095 /* set WUH source */ 8096 tmp = FLOAT_TWO; 8097 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8098} 8099 8100/* 8101 * Setup default parameters for Recon3D/Recon3Di DSP. 8102 */ 8103 8104static void r3d_setup_defaults(struct hda_codec *codec) 8105{ 8106 struct ca0132_spec *spec = codec->spec; 8107 unsigned int tmp; 8108 int num_fx; 8109 int idx, i; 8110 8111 if (spec->dsp_state != DSP_DOWNLOADED) 8112 return; 8113 8114 ca0132_alt_dsp_scp_startup(codec); 8115 ca0132_alt_init_analog_mics(codec); 8116 8117 /*remove DSP headroom*/ 8118 tmp = FLOAT_ZERO; 8119 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8120 8121 /* set WUH source */ 8122 tmp = FLOAT_TWO; 8123 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8124 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8125 8126 /* Set speaker source? */ 8127 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8128 8129 if (ca0132_quirk(spec) == QUIRK_R3DI) 8130 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8131 8132 /* Disable mute on Center/LFE. */ 8133 if (ca0132_quirk(spec) == QUIRK_R3D) { 8134 ca0113_mmio_gpio_set(codec, 2, false); 8135 ca0113_mmio_gpio_set(codec, 4, true); 8136 } 8137 8138 /* Setup effect defaults */ 8139 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8140 for (idx = 0; idx < num_fx; idx++) { 8141 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8142 dspio_set_uint_param(codec, 8143 ca0132_effects[idx].mid, 8144 ca0132_effects[idx].reqs[i], 8145 ca0132_effects[idx].def_vals[i]); 8146 } 8147 } 8148} 8149 8150/* 8151 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8152 * than the Chromebook setup. 8153 */ 8154static void sbz_setup_defaults(struct hda_codec *codec) 8155{ 8156 struct ca0132_spec *spec = codec->spec; 8157 unsigned int tmp; 8158 int num_fx; 8159 int idx, i; 8160 8161 if (spec->dsp_state != DSP_DOWNLOADED) 8162 return; 8163 8164 ca0132_alt_dsp_scp_startup(codec); 8165 ca0132_alt_init_analog_mics(codec); 8166 sbz_connect_streams(codec); 8167 sbz_chipio_startup_data(codec); 8168 8169 chipio_set_stream_control(codec, 0x03, 1); 8170 chipio_set_stream_control(codec, 0x04, 1); 8171 8172 /* 8173 * Sets internal input loopback to off, used to have a switch to 8174 * enable input loopback, but turned out to be way too buggy. 8175 */ 8176 tmp = FLOAT_ONE; 8177 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8178 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8179 8180 /*remove DSP headroom*/ 8181 tmp = FLOAT_ZERO; 8182 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8183 8184 /* set WUH source */ 8185 tmp = FLOAT_TWO; 8186 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8187 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8188 8189 /* Set speaker source? */ 8190 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8191 8192 ca0132_alt_dsp_initial_mic_setup(codec); 8193 8194 /* out, in effects + voicefx */ 8195 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8196 for (idx = 0; idx < num_fx; idx++) { 8197 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8198 dspio_set_uint_param(codec, 8199 ca0132_effects[idx].mid, 8200 ca0132_effects[idx].reqs[i], 8201 ca0132_effects[idx].def_vals[i]); 8202 } 8203 } 8204 8205 ca0132_alt_init_speaker_tuning(codec); 8206 8207 ca0132_alt_create_dummy_stream(codec); 8208} 8209 8210/* 8211 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8212 */ 8213static void ae5_setup_defaults(struct hda_codec *codec) 8214{ 8215 struct ca0132_spec *spec = codec->spec; 8216 unsigned int tmp; 8217 int num_fx; 8218 int idx, i; 8219 8220 if (spec->dsp_state != DSP_DOWNLOADED) 8221 return; 8222 8223 ca0132_alt_dsp_scp_startup(codec); 8224 ca0132_alt_init_analog_mics(codec); 8225 chipio_set_stream_control(codec, 0x03, 1); 8226 chipio_set_stream_control(codec, 0x04, 1); 8227 8228 /* New, unknown SCP req's */ 8229 tmp = FLOAT_ZERO; 8230 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8231 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8232 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8233 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8234 8235 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8236 ca0113_mmio_gpio_set(codec, 0, false); 8237 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8238 8239 /* Internal loopback off */ 8240 tmp = FLOAT_ONE; 8241 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8242 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8243 8244 /*remove DSP headroom*/ 8245 tmp = FLOAT_ZERO; 8246 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8247 8248 /* set WUH source */ 8249 tmp = FLOAT_TWO; 8250 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8251 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8252 8253 /* Set speaker source? */ 8254 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8255 8256 ca0132_alt_dsp_initial_mic_setup(codec); 8257 ae5_post_dsp_register_set(codec); 8258 ae5_post_dsp_param_setup(codec); 8259 ae5_post_dsp_pll_setup(codec); 8260 ae5_post_dsp_stream_setup(codec); 8261 ae5_post_dsp_startup_data(codec); 8262 8263 /* out, in effects + voicefx */ 8264 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8265 for (idx = 0; idx < num_fx; idx++) { 8266 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8267 dspio_set_uint_param(codec, 8268 ca0132_effects[idx].mid, 8269 ca0132_effects[idx].reqs[i], 8270 ca0132_effects[idx].def_vals[i]); 8271 } 8272 } 8273 8274 ca0132_alt_init_speaker_tuning(codec); 8275 8276 ca0132_alt_create_dummy_stream(codec); 8277} 8278 8279/* 8280 * Setup default parameters for the Sound Blaster AE-7 DSP. 8281 */ 8282static void ae7_setup_defaults(struct hda_codec *codec) 8283{ 8284 struct ca0132_spec *spec = codec->spec; 8285 unsigned int tmp; 8286 int num_fx; 8287 int idx, i; 8288 8289 if (spec->dsp_state != DSP_DOWNLOADED) 8290 return; 8291 8292 ca0132_alt_dsp_scp_startup(codec); 8293 ca0132_alt_init_analog_mics(codec); 8294 ae7_post_dsp_setup_ports(codec); 8295 8296 tmp = FLOAT_ZERO; 8297 dspio_set_uint_param(codec, 0x96, 8298 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8299 dspio_set_uint_param(codec, 0x96, 8300 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8301 8302 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8303 8304 /* New, unknown SCP req's */ 8305 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8306 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8307 8308 ca0113_mmio_gpio_set(codec, 0, false); 8309 8310 /* Internal loopback off */ 8311 tmp = FLOAT_ONE; 8312 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8313 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8314 8315 /*remove DSP headroom*/ 8316 tmp = FLOAT_ZERO; 8317 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8318 8319 /* set WUH source */ 8320 tmp = FLOAT_TWO; 8321 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8322 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8323 8324 /* Set speaker source? */ 8325 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8326 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8327 8328 /* 8329 * This is the second time we've called this, but this is seemingly 8330 * what Windows does. 8331 */ 8332 ca0132_alt_init_analog_mics(codec); 8333 8334 ae7_post_dsp_asi_setup(codec); 8335 8336 /* 8337 * Not sure why, but these are both set to 1. They're only set to 0 8338 * upon shutdown. 8339 */ 8340 ca0113_mmio_gpio_set(codec, 0, true); 8341 ca0113_mmio_gpio_set(codec, 1, true); 8342 8343 /* Volume control related. */ 8344 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8345 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8346 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8347 8348 /* out, in effects + voicefx */ 8349 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8350 for (idx = 0; idx < num_fx; idx++) { 8351 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8352 dspio_set_uint_param(codec, 8353 ca0132_effects[idx].mid, 8354 ca0132_effects[idx].reqs[i], 8355 ca0132_effects[idx].def_vals[i]); 8356 } 8357 } 8358 8359 ca0132_alt_init_speaker_tuning(codec); 8360 8361 ca0132_alt_create_dummy_stream(codec); 8362} 8363 8364/* 8365 * Initialization of flags in chip 8366 */ 8367static void ca0132_init_flags(struct hda_codec *codec) 8368{ 8369 struct ca0132_spec *spec = codec->spec; 8370 8371 if (ca0132_use_alt_functions(spec)) { 8372 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8373 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8374 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8375 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8376 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8377 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8378 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8379 chipio_set_control_flag(codec, 8380 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8381 chipio_set_control_flag(codec, 8382 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8383 } else { 8384 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8385 chipio_set_control_flag(codec, 8386 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8387 chipio_set_control_flag(codec, 8388 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8389 chipio_set_control_flag(codec, 8390 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8391 chipio_set_control_flag(codec, 8392 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8393 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8394 } 8395} 8396 8397/* 8398 * Initialization of parameters in chip 8399 */ 8400static void ca0132_init_params(struct hda_codec *codec) 8401{ 8402 struct ca0132_spec *spec = codec->spec; 8403 8404 if (ca0132_use_alt_functions(spec)) { 8405 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8406 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8407 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8408 chipio_set_control_param(codec, 0, 0); 8409 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8410 } 8411 8412 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8413 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8414} 8415 8416static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8417{ 8418 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8419 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8420 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8421 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8422 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8423 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8424 8425 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8426 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8427 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8428} 8429 8430static bool ca0132_download_dsp_images(struct hda_codec *codec) 8431{ 8432 bool dsp_loaded = false; 8433 struct ca0132_spec *spec = codec->spec; 8434 const struct dsp_image_seg *dsp_os_image; 8435 const struct firmware *fw_entry = NULL; 8436 /* 8437 * Alternate firmwares for different variants. The Recon3Di apparently 8438 * can use the default firmware, but I'll leave the option in case 8439 * it needs it again. 8440 */ 8441 switch (ca0132_quirk(spec)) { 8442 case QUIRK_SBZ: 8443 case QUIRK_R3D: 8444 case QUIRK_AE5: 8445 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8446 codec->card->dev) != 0) 8447 codec_dbg(codec, "Desktop firmware not found."); 8448 else 8449 codec_dbg(codec, "Desktop firmware selected."); 8450 break; 8451 case QUIRK_R3DI: 8452 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8453 codec->card->dev) != 0) 8454 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8455 else 8456 codec_dbg(codec, "Recon3Di firmware selected."); 8457 break; 8458 default: 8459 break; 8460 } 8461 /* 8462 * Use default ctefx.bin if no alt firmware is detected, or if none 8463 * exists for your particular codec. 8464 */ 8465 if (!fw_entry) { 8466 codec_dbg(codec, "Default firmware selected."); 8467 if (request_firmware(&fw_entry, EFX_FILE, 8468 codec->card->dev) != 0) 8469 return false; 8470 } 8471 8472 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8473 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8474 codec_err(codec, "ca0132 DSP load image failed\n"); 8475 goto exit_download; 8476 } 8477 8478 dsp_loaded = dspload_wait_loaded(codec); 8479 8480exit_download: 8481 release_firmware(fw_entry); 8482 8483 return dsp_loaded; 8484} 8485 8486static void ca0132_download_dsp(struct hda_codec *codec) 8487{ 8488 struct ca0132_spec *spec = codec->spec; 8489 8490#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8491 return; /* NOP */ 8492#endif 8493 8494 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8495 return; /* don't retry failures */ 8496 8497 chipio_enable_clocks(codec); 8498 if (spec->dsp_state != DSP_DOWNLOADED) { 8499 spec->dsp_state = DSP_DOWNLOADING; 8500 8501 if (!ca0132_download_dsp_images(codec)) 8502 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8503 else 8504 spec->dsp_state = DSP_DOWNLOADED; 8505 } 8506 8507 /* For codecs using alt functions, this is already done earlier */ 8508 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8509 ca0132_set_dsp_msr(codec, true); 8510} 8511 8512static void ca0132_process_dsp_response(struct hda_codec *codec, 8513 struct hda_jack_callback *callback) 8514{ 8515 struct ca0132_spec *spec = codec->spec; 8516 8517 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8518 snd_hda_power_up_pm(codec); 8519 if (spec->wait_scp) { 8520 if (dspio_get_response_data(codec) >= 0) 8521 spec->wait_scp = 0; 8522 } 8523 8524 dspio_clear_response_queue(codec); 8525 snd_hda_power_down_pm(codec); 8526} 8527 8528static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8529{ 8530 struct ca0132_spec *spec = codec->spec; 8531 struct hda_jack_tbl *tbl; 8532 8533 /* Delay enabling the HP amp, to let the mic-detection 8534 * state machine run. 8535 */ 8536 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8537 if (tbl) 8538 tbl->block_report = 1; 8539 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8540} 8541 8542static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8543{ 8544 struct ca0132_spec *spec = codec->spec; 8545 8546 if (ca0132_use_alt_functions(spec)) 8547 ca0132_alt_select_in(codec); 8548 else 8549 ca0132_select_mic(codec); 8550} 8551 8552static void ca0132_init_unsol(struct hda_codec *codec) 8553{ 8554 struct ca0132_spec *spec = codec->spec; 8555 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8556 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8557 amic_callback); 8558 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8559 ca0132_process_dsp_response); 8560 /* Front headphone jack detection */ 8561 if (ca0132_use_alt_functions(spec)) 8562 snd_hda_jack_detect_enable_callback(codec, 8563 spec->unsol_tag_front_hp, hp_callback); 8564} 8565 8566/* 8567 * Verbs tables. 8568 */ 8569 8570/* Sends before DSP download. */ 8571static const struct hda_verb ca0132_base_init_verbs[] = { 8572 /*enable ct extension*/ 8573 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8574 {} 8575}; 8576 8577/* Send at exit. */ 8578static const struct hda_verb ca0132_base_exit_verbs[] = { 8579 /*set afg to D3*/ 8580 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8581 /*disable ct extension*/ 8582 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8583 {} 8584}; 8585 8586/* Other verbs tables. Sends after DSP download. */ 8587 8588static const struct hda_verb ca0132_init_verbs0[] = { 8589 /* chip init verbs */ 8590 {0x15, 0x70D, 0xF0}, 8591 {0x15, 0x70E, 0xFE}, 8592 {0x15, 0x707, 0x75}, 8593 {0x15, 0x707, 0xD3}, 8594 {0x15, 0x707, 0x09}, 8595 {0x15, 0x707, 0x53}, 8596 {0x15, 0x707, 0xD4}, 8597 {0x15, 0x707, 0xEF}, 8598 {0x15, 0x707, 0x75}, 8599 {0x15, 0x707, 0xD3}, 8600 {0x15, 0x707, 0x09}, 8601 {0x15, 0x707, 0x02}, 8602 {0x15, 0x707, 0x37}, 8603 {0x15, 0x707, 0x78}, 8604 {0x15, 0x53C, 0xCE}, 8605 {0x15, 0x575, 0xC9}, 8606 {0x15, 0x53D, 0xCE}, 8607 {0x15, 0x5B7, 0xC9}, 8608 {0x15, 0x70D, 0xE8}, 8609 {0x15, 0x70E, 0xFE}, 8610 {0x15, 0x707, 0x02}, 8611 {0x15, 0x707, 0x68}, 8612 {0x15, 0x707, 0x62}, 8613 {0x15, 0x53A, 0xCE}, 8614 {0x15, 0x546, 0xC9}, 8615 {0x15, 0x53B, 0xCE}, 8616 {0x15, 0x5E8, 0xC9}, 8617 {} 8618}; 8619 8620/* Extra init verbs for desktop cards. */ 8621static const struct hda_verb ca0132_init_verbs1[] = { 8622 {0x15, 0x70D, 0x20}, 8623 {0x15, 0x70E, 0x19}, 8624 {0x15, 0x707, 0x00}, 8625 {0x15, 0x539, 0xCE}, 8626 {0x15, 0x546, 0xC9}, 8627 {0x15, 0x70D, 0xB7}, 8628 {0x15, 0x70E, 0x09}, 8629 {0x15, 0x707, 0x10}, 8630 {0x15, 0x70D, 0xAF}, 8631 {0x15, 0x70E, 0x09}, 8632 {0x15, 0x707, 0x01}, 8633 {0x15, 0x707, 0x05}, 8634 {0x15, 0x70D, 0x73}, 8635 {0x15, 0x70E, 0x09}, 8636 {0x15, 0x707, 0x14}, 8637 {0x15, 0x6FF, 0xC4}, 8638 {} 8639}; 8640 8641static void ca0132_init_chip(struct hda_codec *codec) 8642{ 8643 struct ca0132_spec *spec = codec->spec; 8644 int num_fx; 8645 int i; 8646 unsigned int on; 8647 8648 mutex_init(&spec->chipio_mutex); 8649 8650 spec->cur_out_type = SPEAKER_OUT; 8651 if (!ca0132_use_alt_functions(spec)) 8652 spec->cur_mic_type = DIGITAL_MIC; 8653 else 8654 spec->cur_mic_type = REAR_MIC; 8655 8656 spec->cur_mic_boost = 0; 8657 8658 for (i = 0; i < VNODES_COUNT; i++) { 8659 spec->vnode_lvol[i] = 0x5a; 8660 spec->vnode_rvol[i] = 0x5a; 8661 spec->vnode_lswitch[i] = 0; 8662 spec->vnode_rswitch[i] = 0; 8663 } 8664 8665 /* 8666 * Default states for effects are in ca0132_effects[]. 8667 */ 8668 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8669 for (i = 0; i < num_fx; i++) { 8670 on = (unsigned int)ca0132_effects[i].reqs[0]; 8671 spec->effects_switch[i] = on ? 1 : 0; 8672 } 8673 /* 8674 * Sets defaults for the effect slider controls, only for alternative 8675 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8676 */ 8677 if (ca0132_use_alt_controls(spec)) { 8678 /* Set speakers to default to full range. */ 8679 spec->speaker_range_val[0] = 1; 8680 spec->speaker_range_val[1] = 1; 8681 8682 spec->xbass_xover_freq = 8; 8683 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8684 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8685 8686 spec->bass_redirect_xover_freq = 8; 8687 } 8688 8689 spec->voicefx_val = 0; 8690 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8691 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8692 8693 /* 8694 * The ZxR doesn't have a front panel header, and it's line-in is on 8695 * the daughter board. So, there is no input enum control, and we need 8696 * to make sure that spec->in_enum_val is set properly. 8697 */ 8698 if (ca0132_quirk(spec) == QUIRK_ZXR) 8699 spec->in_enum_val = REAR_MIC; 8700 8701#ifdef ENABLE_TUNING_CONTROLS 8702 ca0132_init_tuning_defaults(codec); 8703#endif 8704} 8705 8706/* 8707 * Recon3Di exit specific commands. 8708 */ 8709/* prevents popping noise on shutdown */ 8710static void r3di_gpio_shutdown(struct hda_codec *codec) 8711{ 8712 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8713} 8714 8715/* 8716 * Sound Blaster Z exit specific commands. 8717 */ 8718static void sbz_region2_exit(struct hda_codec *codec) 8719{ 8720 struct ca0132_spec *spec = codec->spec; 8721 unsigned int i; 8722 8723 for (i = 0; i < 4; i++) 8724 writeb(0x0, spec->mem_base + 0x100); 8725 for (i = 0; i < 8; i++) 8726 writeb(0xb3, spec->mem_base + 0x304); 8727 8728 ca0113_mmio_gpio_set(codec, 0, false); 8729 ca0113_mmio_gpio_set(codec, 1, false); 8730 ca0113_mmio_gpio_set(codec, 4, true); 8731 ca0113_mmio_gpio_set(codec, 5, false); 8732 ca0113_mmio_gpio_set(codec, 7, false); 8733} 8734 8735static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8736{ 8737 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8738 unsigned int i; 8739 8740 snd_hda_codec_write(codec, 0x11, 0, 8741 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8742 8743 for (i = 0; i < ARRAY_SIZE(pins); i++) 8744 snd_hda_codec_write(codec, pins[i], 0, 8745 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8746} 8747 8748static void ca0132_clear_unsolicited(struct hda_codec *codec) 8749{ 8750 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8751 unsigned int i; 8752 8753 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8754 snd_hda_codec_write(codec, pins[i], 0, 8755 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8756 } 8757} 8758 8759/* On shutdown, sends commands in sets of three */ 8760static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8761 int mask, int data) 8762{ 8763 if (dir >= 0) 8764 snd_hda_codec_write(codec, 0x01, 0, 8765 AC_VERB_SET_GPIO_DIRECTION, dir); 8766 if (mask >= 0) 8767 snd_hda_codec_write(codec, 0x01, 0, 8768 AC_VERB_SET_GPIO_MASK, mask); 8769 8770 if (data >= 0) 8771 snd_hda_codec_write(codec, 0x01, 0, 8772 AC_VERB_SET_GPIO_DATA, data); 8773} 8774 8775static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8776{ 8777 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8778 unsigned int i; 8779 8780 for (i = 0; i < ARRAY_SIZE(pins); i++) 8781 snd_hda_codec_write(codec, pins[i], 0, 8782 AC_VERB_SET_POWER_STATE, 0x03); 8783} 8784 8785static void sbz_exit_chip(struct hda_codec *codec) 8786{ 8787 chipio_set_stream_control(codec, 0x03, 0); 8788 chipio_set_stream_control(codec, 0x04, 0); 8789 8790 /* Mess with GPIO */ 8791 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8792 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8793 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8794 8795 chipio_set_stream_control(codec, 0x14, 0); 8796 chipio_set_stream_control(codec, 0x0C, 0); 8797 8798 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8799 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8800 8801 chipio_write(codec, 0x18a020, 0x00000083); 8802 8803 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8804 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8805 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8806 8807 chipio_set_stream_control(codec, 0x0C, 0); 8808 8809 chipio_set_control_param(codec, 0x0D, 0x24); 8810 8811 ca0132_clear_unsolicited(codec); 8812 sbz_set_pin_ctl_default(codec); 8813 8814 snd_hda_codec_write(codec, 0x0B, 0, 8815 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8816 8817 sbz_region2_exit(codec); 8818} 8819 8820static void r3d_exit_chip(struct hda_codec *codec) 8821{ 8822 ca0132_clear_unsolicited(codec); 8823 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8824 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8825} 8826 8827static void ae5_exit_chip(struct hda_codec *codec) 8828{ 8829 chipio_set_stream_control(codec, 0x03, 0); 8830 chipio_set_stream_control(codec, 0x04, 0); 8831 8832 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8833 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8834 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8835 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8836 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8837 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 8838 ca0113_mmio_gpio_set(codec, 0, false); 8839 ca0113_mmio_gpio_set(codec, 1, false); 8840 8841 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8842 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8843 8844 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8845 8846 chipio_set_stream_control(codec, 0x18, 0); 8847 chipio_set_stream_control(codec, 0x0c, 0); 8848 8849 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 8850} 8851 8852static void ae7_exit_chip(struct hda_codec *codec) 8853{ 8854 chipio_set_stream_control(codec, 0x18, 0); 8855 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 8856 chipio_set_stream_channels(codec, 0x21, 0); 8857 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 8858 chipio_set_control_param(codec, 0x20, 0x01); 8859 8860 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8861 8862 chipio_set_stream_control(codec, 0x18, 0); 8863 chipio_set_stream_control(codec, 0x0c, 0); 8864 8865 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8866 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 8867 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8868 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8869 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 8870 ca0113_mmio_gpio_set(codec, 0, false); 8871 ca0113_mmio_gpio_set(codec, 1, false); 8872 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8873 8874 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8875 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8876} 8877 8878static void zxr_exit_chip(struct hda_codec *codec) 8879{ 8880 chipio_set_stream_control(codec, 0x03, 0); 8881 chipio_set_stream_control(codec, 0x04, 0); 8882 chipio_set_stream_control(codec, 0x14, 0); 8883 chipio_set_stream_control(codec, 0x0C, 0); 8884 8885 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8886 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8887 8888 chipio_write(codec, 0x18a020, 0x00000083); 8889 8890 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8891 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8892 8893 ca0132_clear_unsolicited(codec); 8894 sbz_set_pin_ctl_default(codec); 8895 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8896 8897 ca0113_mmio_gpio_set(codec, 5, false); 8898 ca0113_mmio_gpio_set(codec, 2, false); 8899 ca0113_mmio_gpio_set(codec, 3, false); 8900 ca0113_mmio_gpio_set(codec, 0, false); 8901 ca0113_mmio_gpio_set(codec, 4, true); 8902 ca0113_mmio_gpio_set(codec, 0, true); 8903 ca0113_mmio_gpio_set(codec, 5, true); 8904 ca0113_mmio_gpio_set(codec, 2, false); 8905 ca0113_mmio_gpio_set(codec, 3, false); 8906} 8907 8908static void ca0132_exit_chip(struct hda_codec *codec) 8909{ 8910 /* put any chip cleanup stuffs here. */ 8911 8912 if (dspload_is_loaded(codec)) 8913 dsp_reset(codec); 8914} 8915 8916/* 8917 * This fixes a problem that was hard to reproduce. Very rarely, I would 8918 * boot up, and there would be no sound, but the DSP indicated it had loaded 8919 * properly. I did a few memory dumps to see if anything was different, and 8920 * there were a few areas of memory uninitialized with a1a2a3a4. This function 8921 * checks if those areas are uninitialized, and if they are, it'll attempt to 8922 * reload the card 3 times. Usually it fixes by the second. 8923 */ 8924static void sbz_dsp_startup_check(struct hda_codec *codec) 8925{ 8926 struct ca0132_spec *spec = codec->spec; 8927 unsigned int dsp_data_check[4]; 8928 unsigned int cur_address = 0x390; 8929 unsigned int i; 8930 unsigned int failure = 0; 8931 unsigned int reload = 3; 8932 8933 if (spec->startup_check_entered) 8934 return; 8935 8936 spec->startup_check_entered = true; 8937 8938 for (i = 0; i < 4; i++) { 8939 chipio_read(codec, cur_address, &dsp_data_check[i]); 8940 cur_address += 0x4; 8941 } 8942 for (i = 0; i < 4; i++) { 8943 if (dsp_data_check[i] == 0xa1a2a3a4) 8944 failure = 1; 8945 } 8946 8947 codec_dbg(codec, "Startup Check: %d ", failure); 8948 if (failure) 8949 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 8950 /* 8951 * While the failure condition is true, and we haven't reached our 8952 * three reload limit, continue trying to reload the driver and 8953 * fix the issue. 8954 */ 8955 while (failure && (reload != 0)) { 8956 codec_info(codec, "Reloading... Tries left: %d", reload); 8957 sbz_exit_chip(codec); 8958 spec->dsp_state = DSP_DOWNLOAD_INIT; 8959 codec->patch_ops.init(codec); 8960 failure = 0; 8961 for (i = 0; i < 4; i++) { 8962 chipio_read(codec, cur_address, &dsp_data_check[i]); 8963 cur_address += 0x4; 8964 } 8965 for (i = 0; i < 4; i++) { 8966 if (dsp_data_check[i] == 0xa1a2a3a4) 8967 failure = 1; 8968 } 8969 reload--; 8970 } 8971 8972 if (!failure && reload < 3) 8973 codec_info(codec, "DSP fixed."); 8974 8975 if (!failure) 8976 return; 8977 8978 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 8979} 8980 8981/* 8982 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 8983 * extra precision for decibel values. If you had the dB value in floating point 8984 * you would take the value after the decimal point, multiply by 64, and divide 8985 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 8986 * implement fixed point or floating point dB volumes. For now, I'll set them 8987 * to 0 just incase a value has lingered from a boot into Windows. 8988 */ 8989static void ca0132_alt_vol_setup(struct hda_codec *codec) 8990{ 8991 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 8992 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 8993 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 8994 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 8995 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 8996 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 8997 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 8998 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 8999} 9000 9001/* 9002 * Extra commands that don't really fit anywhere else. 9003 */ 9004static void sbz_pre_dsp_setup(struct hda_codec *codec) 9005{ 9006 struct ca0132_spec *spec = codec->spec; 9007 9008 writel(0x00820680, spec->mem_base + 0x01C); 9009 writel(0x00820680, spec->mem_base + 0x01C); 9010 9011 chipio_write(codec, 0x18b0a4, 0x000000c2); 9012 9013 snd_hda_codec_write(codec, 0x11, 0, 9014 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9015} 9016 9017static void r3d_pre_dsp_setup(struct hda_codec *codec) 9018{ 9019 chipio_write(codec, 0x18b0a4, 0x000000c2); 9020 9021 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9022 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 9023 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9024 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 9025 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9026 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 9027 9028 snd_hda_codec_write(codec, 0x11, 0, 9029 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9030} 9031 9032static void r3di_pre_dsp_setup(struct hda_codec *codec) 9033{ 9034 chipio_write(codec, 0x18b0a4, 0x000000c2); 9035 9036 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9037 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 9038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9039 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 9040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9041 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 9042 9043 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9044 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 9045 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9046 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 9047 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9048 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 9049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9050 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 9051 9052 snd_hda_codec_write(codec, 0x11, 0, 9053 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9054} 9055 9056/* 9057 * These are sent before the DSP is downloaded. Not sure 9058 * what they do, or if they're necessary. Could possibly 9059 * be removed. Figure they're better to leave in. 9060 */ 9061static const unsigned int ca0113_mmio_init_address_sbz[] = { 9062 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9063 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9064}; 9065 9066static const unsigned int ca0113_mmio_init_data_sbz[] = { 9067 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9068 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9069 0x000000c1, 0x00000080 9070}; 9071 9072static const unsigned int ca0113_mmio_init_data_zxr[] = { 9073 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9074 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9075 0x000000c1, 0x00000080 9076}; 9077 9078static const unsigned int ca0113_mmio_init_address_ae5[] = { 9079 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9080 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9081 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9082 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9083}; 9084 9085static const unsigned int ca0113_mmio_init_data_ae5[] = { 9086 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9087 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9088 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9089 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9090 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9091 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9092 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9093 0x00000080, 0x00880680 9094}; 9095 9096static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9097{ 9098 struct ca0132_spec *spec = codec->spec; 9099 unsigned int tmp[2], i, count, cur_addr; 9100 const unsigned int *addr, *data; 9101 9102 addr = ca0113_mmio_init_address_sbz; 9103 for (i = 0; i < 3; i++) 9104 writel(0x00000000, spec->mem_base + addr[i]); 9105 9106 cur_addr = i; 9107 switch (ca0132_quirk(spec)) { 9108 case QUIRK_ZXR: 9109 tmp[0] = 0x00880480; 9110 tmp[1] = 0x00000080; 9111 break; 9112 case QUIRK_SBZ: 9113 tmp[0] = 0x00820680; 9114 tmp[1] = 0x00000083; 9115 break; 9116 case QUIRK_R3D: 9117 tmp[0] = 0x00880680; 9118 tmp[1] = 0x00000083; 9119 break; 9120 default: 9121 tmp[0] = 0x00000000; 9122 tmp[1] = 0x00000000; 9123 break; 9124 } 9125 9126 for (i = 0; i < 2; i++) 9127 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9128 9129 cur_addr += i; 9130 9131 switch (ca0132_quirk(spec)) { 9132 case QUIRK_ZXR: 9133 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9134 data = ca0113_mmio_init_data_zxr; 9135 break; 9136 default: 9137 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9138 data = ca0113_mmio_init_data_sbz; 9139 break; 9140 } 9141 9142 for (i = 0; i < count; i++) 9143 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9144} 9145 9146static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9147{ 9148 struct ca0132_spec *spec = codec->spec; 9149 const unsigned int *addr, *data; 9150 unsigned int i, count; 9151 9152 addr = ca0113_mmio_init_address_ae5; 9153 data = ca0113_mmio_init_data_ae5; 9154 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9155 9156 if (ca0132_quirk(spec) == QUIRK_AE7) { 9157 writel(0x00000680, spec->mem_base + 0x1c); 9158 writel(0x00880680, spec->mem_base + 0x1c); 9159 } 9160 9161 for (i = 0; i < count; i++) { 9162 /* 9163 * AE-7 shares all writes with the AE-5, except that it writes 9164 * a different value to 0x20c. 9165 */ 9166 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9167 writel(0x00800001, spec->mem_base + addr[i]); 9168 continue; 9169 } 9170 9171 writel(data[i], spec->mem_base + addr[i]); 9172 } 9173 9174 if (ca0132_quirk(spec) == QUIRK_AE5) 9175 writel(0x00880680, spec->mem_base + 0x1c); 9176} 9177 9178static void ca0132_mmio_init(struct hda_codec *codec) 9179{ 9180 struct ca0132_spec *spec = codec->spec; 9181 9182 switch (ca0132_quirk(spec)) { 9183 case QUIRK_R3D: 9184 case QUIRK_SBZ: 9185 case QUIRK_ZXR: 9186 ca0132_mmio_init_sbz(codec); 9187 break; 9188 case QUIRK_AE5: 9189 ca0132_mmio_init_ae5(codec); 9190 break; 9191 default: 9192 break; 9193 } 9194} 9195 9196static const unsigned int ca0132_ae5_register_set_addresses[] = { 9197 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9198 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9199}; 9200 9201static const unsigned char ca0132_ae5_register_set_data[] = { 9202 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9203 0x01, 0x6b, 0x57 9204}; 9205 9206/* 9207 * This function writes to some SFR's, does some region2 writes, and then 9208 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9209 * what it does. 9210 */ 9211static void ae5_register_set(struct hda_codec *codec) 9212{ 9213 struct ca0132_spec *spec = codec->spec; 9214 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9215 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9216 const unsigned char *data = ca0132_ae5_register_set_data; 9217 unsigned int i, cur_addr; 9218 unsigned char tmp[3]; 9219 9220 if (ca0132_quirk(spec) == QUIRK_AE7) { 9221 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9222 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 9223 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9224 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 9225 } 9226 9227 chipio_8051_write_direct(codec, 0x93, 0x10); 9228 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9229 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 9230 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9231 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 9232 9233 if (ca0132_quirk(spec) == QUIRK_AE7) { 9234 tmp[0] = 0x03; 9235 tmp[1] = 0x03; 9236 tmp[2] = 0x07; 9237 } else { 9238 tmp[0] = 0x0f; 9239 tmp[1] = 0x0f; 9240 tmp[2] = 0x0f; 9241 } 9242 9243 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9244 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9245 9246 /* 9247 * First writes are in single bytes, final are in 4 bytes. So, we use 9248 * writeb, then writel. 9249 */ 9250 for (i = 0; cur_addr < 12; i++, cur_addr++) 9251 writeb(data[i], spec->mem_base + addr[cur_addr]); 9252 9253 for (; cur_addr < count; i++, cur_addr++) 9254 writel(data[i], spec->mem_base + addr[cur_addr]); 9255 9256 writel(0x00800001, spec->mem_base + 0x20c); 9257 9258 if (ca0132_quirk(spec) == QUIRK_AE7) { 9259 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9260 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9261 } else { 9262 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9263 } 9264 9265 chipio_8051_write_direct(codec, 0x90, 0x00); 9266 chipio_8051_write_direct(codec, 0x90, 0x10); 9267 9268 if (ca0132_quirk(spec) == QUIRK_AE5) 9269 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9270 9271 chipio_write(codec, 0x18b0a4, 0x000000c2); 9272 9273 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 9274 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 9275} 9276 9277/* 9278 * Extra init functions for alternative ca0132 codecs. Done 9279 * here so they don't clutter up the main ca0132_init function 9280 * anymore than they have to. 9281 */ 9282static void ca0132_alt_init(struct hda_codec *codec) 9283{ 9284 struct ca0132_spec *spec = codec->spec; 9285 9286 ca0132_alt_vol_setup(codec); 9287 9288 switch (ca0132_quirk(spec)) { 9289 case QUIRK_SBZ: 9290 codec_dbg(codec, "SBZ alt_init"); 9291 ca0132_gpio_init(codec); 9292 sbz_pre_dsp_setup(codec); 9293 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9294 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9295 break; 9296 case QUIRK_R3DI: 9297 codec_dbg(codec, "R3DI alt_init"); 9298 ca0132_gpio_init(codec); 9299 ca0132_gpio_setup(codec); 9300 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9301 r3di_pre_dsp_setup(codec); 9302 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9303 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9304 break; 9305 case QUIRK_R3D: 9306 r3d_pre_dsp_setup(codec); 9307 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9308 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9309 break; 9310 case QUIRK_AE5: 9311 ca0132_gpio_init(codec); 9312 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9313 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 9314 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9315 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 9316 chipio_write(codec, 0x18b030, 0x00000020); 9317 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9318 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9319 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9320 break; 9321 case QUIRK_AE7: 9322 ca0132_gpio_init(codec); 9323 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9324 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 9325 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9326 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 9327 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9328 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9329 chipio_write(codec, 0x18b008, 0x000000f8); 9330 chipio_write(codec, 0x18b008, 0x000000f0); 9331 chipio_write(codec, 0x18b030, 0x00000020); 9332 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9333 break; 9334 case QUIRK_ZXR: 9335 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9336 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9337 break; 9338 default: 9339 break; 9340 } 9341} 9342 9343static int ca0132_init(struct hda_codec *codec) 9344{ 9345 struct ca0132_spec *spec = codec->spec; 9346 struct auto_pin_cfg *cfg = &spec->autocfg; 9347 int i; 9348 bool dsp_loaded; 9349 9350 /* 9351 * If the DSP is already downloaded, and init has been entered again, 9352 * there's only two reasons for it. One, the codec has awaken from a 9353 * suspended state, and in that case dspload_is_loaded will return 9354 * false, and the init will be ran again. The other reason it gets 9355 * re entered is on startup for some reason it triggers a suspend and 9356 * resume state. In this case, it will check if the DSP is downloaded, 9357 * and not run the init function again. For codecs using alt_functions, 9358 * it will check if the DSP is loaded properly. 9359 */ 9360 if (spec->dsp_state == DSP_DOWNLOADED) { 9361 dsp_loaded = dspload_is_loaded(codec); 9362 if (!dsp_loaded) { 9363 spec->dsp_reload = true; 9364 spec->dsp_state = DSP_DOWNLOAD_INIT; 9365 } else { 9366 if (ca0132_quirk(spec) == QUIRK_SBZ) 9367 sbz_dsp_startup_check(codec); 9368 return 0; 9369 } 9370 } 9371 9372 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9373 spec->dsp_state = DSP_DOWNLOAD_INIT; 9374 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9375 9376 if (ca0132_use_pci_mmio(spec)) 9377 ca0132_mmio_init(codec); 9378 9379 snd_hda_power_up_pm(codec); 9380 9381 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9382 ae5_register_set(codec); 9383 9384 ca0132_init_unsol(codec); 9385 ca0132_init_params(codec); 9386 ca0132_init_flags(codec); 9387 9388 snd_hda_sequence_write(codec, spec->base_init_verbs); 9389 9390 if (ca0132_use_alt_functions(spec)) 9391 ca0132_alt_init(codec); 9392 9393 ca0132_download_dsp(codec); 9394 9395 ca0132_refresh_widget_caps(codec); 9396 9397 switch (ca0132_quirk(spec)) { 9398 case QUIRK_R3DI: 9399 case QUIRK_R3D: 9400 r3d_setup_defaults(codec); 9401 break; 9402 case QUIRK_SBZ: 9403 case QUIRK_ZXR: 9404 sbz_setup_defaults(codec); 9405 break; 9406 case QUIRK_AE5: 9407 ae5_setup_defaults(codec); 9408 break; 9409 case QUIRK_AE7: 9410 ae7_setup_defaults(codec); 9411 break; 9412 default: 9413 ca0132_setup_defaults(codec); 9414 ca0132_init_analog_mic2(codec); 9415 ca0132_init_dmic(codec); 9416 break; 9417 } 9418 9419 for (i = 0; i < spec->num_outputs; i++) 9420 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9421 9422 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9423 9424 for (i = 0; i < spec->num_inputs; i++) 9425 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9426 9427 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9428 9429 if (!ca0132_use_alt_functions(spec)) { 9430 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9431 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9432 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9433 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9434 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9435 } 9436 9437 if (ca0132_quirk(spec) == QUIRK_SBZ) 9438 ca0132_gpio_setup(codec); 9439 9440 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9441 if (ca0132_use_alt_functions(spec)) { 9442 ca0132_alt_select_out(codec); 9443 ca0132_alt_select_in(codec); 9444 } else { 9445 ca0132_select_out(codec); 9446 ca0132_select_mic(codec); 9447 } 9448 9449 snd_hda_jack_report_sync(codec); 9450 9451 /* 9452 * Re set the PlayEnhancement switch on a resume event, because the 9453 * controls will not be reloaded. 9454 */ 9455 if (spec->dsp_reload) { 9456 spec->dsp_reload = false; 9457 ca0132_pe_switch_set(codec); 9458 } 9459 9460 snd_hda_power_down_pm(codec); 9461 9462 return 0; 9463} 9464 9465static int dbpro_init(struct hda_codec *codec) 9466{ 9467 struct ca0132_spec *spec = codec->spec; 9468 struct auto_pin_cfg *cfg = &spec->autocfg; 9469 unsigned int i; 9470 9471 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9472 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9473 9474 for (i = 0; i < spec->num_inputs; i++) 9475 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9476 9477 return 0; 9478} 9479 9480static void ca0132_free(struct hda_codec *codec) 9481{ 9482 struct ca0132_spec *spec = codec->spec; 9483 9484 cancel_delayed_work_sync(&spec->unsol_hp_work); 9485 snd_hda_power_up(codec); 9486 switch (ca0132_quirk(spec)) { 9487 case QUIRK_SBZ: 9488 sbz_exit_chip(codec); 9489 break; 9490 case QUIRK_ZXR: 9491 zxr_exit_chip(codec); 9492 break; 9493 case QUIRK_R3D: 9494 r3d_exit_chip(codec); 9495 break; 9496 case QUIRK_AE5: 9497 ae5_exit_chip(codec); 9498 break; 9499 case QUIRK_AE7: 9500 ae7_exit_chip(codec); 9501 break; 9502 case QUIRK_R3DI: 9503 r3di_gpio_shutdown(codec); 9504 break; 9505 default: 9506 break; 9507 } 9508 9509 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9510 ca0132_exit_chip(codec); 9511 9512 snd_hda_power_down(codec); 9513#ifdef CONFIG_PCI 9514 if (spec->mem_base) 9515 pci_iounmap(codec->bus->pci, spec->mem_base); 9516#endif 9517 kfree(spec->spec_init_verbs); 9518 kfree(codec->spec); 9519} 9520 9521static void dbpro_free(struct hda_codec *codec) 9522{ 9523 struct ca0132_spec *spec = codec->spec; 9524 9525 zxr_dbpro_power_state_shutdown(codec); 9526 9527 kfree(spec->spec_init_verbs); 9528 kfree(codec->spec); 9529} 9530 9531static void ca0132_reboot_notify(struct hda_codec *codec) 9532{ 9533 codec->patch_ops.free(codec); 9534} 9535 9536#ifdef CONFIG_PM 9537static int ca0132_suspend(struct hda_codec *codec) 9538{ 9539 struct ca0132_spec *spec = codec->spec; 9540 9541 cancel_delayed_work_sync(&spec->unsol_hp_work); 9542 return 0; 9543} 9544#endif 9545 9546static const struct hda_codec_ops ca0132_patch_ops = { 9547 .build_controls = ca0132_build_controls, 9548 .build_pcms = ca0132_build_pcms, 9549 .init = ca0132_init, 9550 .free = ca0132_free, 9551 .unsol_event = snd_hda_jack_unsol_event, 9552#ifdef CONFIG_PM 9553 .suspend = ca0132_suspend, 9554#endif 9555 .reboot_notify = ca0132_reboot_notify, 9556}; 9557 9558static const struct hda_codec_ops dbpro_patch_ops = { 9559 .build_controls = dbpro_build_controls, 9560 .build_pcms = dbpro_build_pcms, 9561 .init = dbpro_init, 9562 .free = dbpro_free, 9563}; 9564 9565static void ca0132_config(struct hda_codec *codec) 9566{ 9567 struct ca0132_spec *spec = codec->spec; 9568 9569 spec->dacs[0] = 0x2; 9570 spec->dacs[1] = 0x3; 9571 spec->dacs[2] = 0x4; 9572 9573 spec->multiout.dac_nids = spec->dacs; 9574 spec->multiout.num_dacs = 3; 9575 9576 if (!ca0132_use_alt_functions(spec)) 9577 spec->multiout.max_channels = 2; 9578 else 9579 spec->multiout.max_channels = 6; 9580 9581 switch (ca0132_quirk(spec)) { 9582 case QUIRK_ALIENWARE: 9583 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9584 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9585 break; 9586 case QUIRK_SBZ: 9587 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9588 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9589 break; 9590 case QUIRK_ZXR: 9591 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9592 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9593 break; 9594 case QUIRK_R3D: 9595 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9596 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9597 break; 9598 case QUIRK_R3DI: 9599 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9600 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9601 break; 9602 case QUIRK_AE5: 9603 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9604 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9605 break; 9606 case QUIRK_AE7: 9607 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9608 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9609 break; 9610 default: 9611 break; 9612 } 9613 9614 switch (ca0132_quirk(spec)) { 9615 case QUIRK_ALIENWARE: 9616 spec->num_outputs = 2; 9617 spec->out_pins[0] = 0x0b; /* speaker out */ 9618 spec->out_pins[1] = 0x0f; 9619 spec->shared_out_nid = 0x2; 9620 spec->unsol_tag_hp = 0x0f; 9621 9622 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9623 spec->adcs[1] = 0x8; /* analog mic2 */ 9624 spec->adcs[2] = 0xa; /* what u hear */ 9625 9626 spec->num_inputs = 3; 9627 spec->input_pins[0] = 0x12; 9628 spec->input_pins[1] = 0x11; 9629 spec->input_pins[2] = 0x13; 9630 spec->shared_mic_nid = 0x7; 9631 spec->unsol_tag_amic1 = 0x11; 9632 break; 9633 case QUIRK_SBZ: 9634 case QUIRK_R3D: 9635 spec->num_outputs = 2; 9636 spec->out_pins[0] = 0x0B; /* Line out */ 9637 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9638 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9639 spec->out_pins[3] = 0x11; /* Rear surround */ 9640 spec->shared_out_nid = 0x2; 9641 spec->unsol_tag_hp = spec->out_pins[1]; 9642 spec->unsol_tag_front_hp = spec->out_pins[2]; 9643 9644 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9645 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9646 spec->adcs[2] = 0xa; /* what u hear */ 9647 9648 spec->num_inputs = 2; 9649 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9650 spec->input_pins[1] = 0x13; /* What U Hear */ 9651 spec->shared_mic_nid = 0x7; 9652 spec->unsol_tag_amic1 = spec->input_pins[0]; 9653 9654 /* SPDIF I/O */ 9655 spec->dig_out = 0x05; 9656 spec->multiout.dig_out_nid = spec->dig_out; 9657 spec->dig_in = 0x09; 9658 break; 9659 case QUIRK_ZXR: 9660 spec->num_outputs = 2; 9661 spec->out_pins[0] = 0x0B; /* Line out */ 9662 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9663 spec->out_pins[2] = 0x10; /* Center/LFE */ 9664 spec->out_pins[3] = 0x11; /* Rear surround */ 9665 spec->shared_out_nid = 0x2; 9666 spec->unsol_tag_hp = spec->out_pins[1]; 9667 spec->unsol_tag_front_hp = spec->out_pins[2]; 9668 9669 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9670 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9671 spec->adcs[2] = 0xa; /* what u hear */ 9672 9673 spec->num_inputs = 2; 9674 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9675 spec->input_pins[1] = 0x13; /* What U Hear */ 9676 spec->shared_mic_nid = 0x7; 9677 spec->unsol_tag_amic1 = spec->input_pins[0]; 9678 break; 9679 case QUIRK_ZXR_DBPRO: 9680 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9681 9682 spec->num_inputs = 1; 9683 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9684 9685 spec->dig_out = 0x05; 9686 spec->multiout.dig_out_nid = spec->dig_out; 9687 9688 spec->dig_in = 0x09; 9689 break; 9690 case QUIRK_AE5: 9691 case QUIRK_AE7: 9692 spec->num_outputs = 2; 9693 spec->out_pins[0] = 0x0B; /* Line out */ 9694 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9695 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9696 spec->out_pins[3] = 0x0F; /* Rear surround */ 9697 spec->shared_out_nid = 0x2; 9698 spec->unsol_tag_hp = spec->out_pins[1]; 9699 spec->unsol_tag_front_hp = spec->out_pins[2]; 9700 9701 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9702 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9703 spec->adcs[2] = 0xa; /* what u hear */ 9704 9705 spec->num_inputs = 2; 9706 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9707 spec->input_pins[1] = 0x13; /* What U Hear */ 9708 spec->shared_mic_nid = 0x7; 9709 spec->unsol_tag_amic1 = spec->input_pins[0]; 9710 9711 /* SPDIF I/O */ 9712 spec->dig_out = 0x05; 9713 spec->multiout.dig_out_nid = spec->dig_out; 9714 break; 9715 case QUIRK_R3DI: 9716 spec->num_outputs = 2; 9717 spec->out_pins[0] = 0x0B; /* Line out */ 9718 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9719 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9720 spec->out_pins[3] = 0x11; /* Rear surround */ 9721 spec->shared_out_nid = 0x2; 9722 spec->unsol_tag_hp = spec->out_pins[1]; 9723 spec->unsol_tag_front_hp = spec->out_pins[2]; 9724 9725 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9726 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9727 spec->adcs[2] = 0x0a; /* what u hear */ 9728 9729 spec->num_inputs = 2; 9730 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9731 spec->input_pins[1] = 0x13; /* What U Hear */ 9732 spec->shared_mic_nid = 0x7; 9733 spec->unsol_tag_amic1 = spec->input_pins[0]; 9734 9735 /* SPDIF I/O */ 9736 spec->dig_out = 0x05; 9737 spec->multiout.dig_out_nid = spec->dig_out; 9738 break; 9739 default: 9740 spec->num_outputs = 2; 9741 spec->out_pins[0] = 0x0b; /* speaker out */ 9742 spec->out_pins[1] = 0x10; /* headphone out */ 9743 spec->shared_out_nid = 0x2; 9744 spec->unsol_tag_hp = spec->out_pins[1]; 9745 9746 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9747 spec->adcs[1] = 0x8; /* analog mic2 */ 9748 spec->adcs[2] = 0xa; /* what u hear */ 9749 9750 spec->num_inputs = 3; 9751 spec->input_pins[0] = 0x12; 9752 spec->input_pins[1] = 0x11; 9753 spec->input_pins[2] = 0x13; 9754 spec->shared_mic_nid = 0x7; 9755 spec->unsol_tag_amic1 = spec->input_pins[0]; 9756 9757 /* SPDIF I/O */ 9758 spec->dig_out = 0x05; 9759 spec->multiout.dig_out_nid = spec->dig_out; 9760 spec->dig_in = 0x09; 9761 break; 9762 } 9763} 9764 9765static int ca0132_prepare_verbs(struct hda_codec *codec) 9766{ 9767/* Verbs + terminator (an empty element) */ 9768#define NUM_SPEC_VERBS 2 9769 struct ca0132_spec *spec = codec->spec; 9770 9771 spec->chip_init_verbs = ca0132_init_verbs0; 9772 /* 9773 * Since desktop cards use pci_mmio, this can be used to determine 9774 * whether or not to use these verbs instead of a separate bool. 9775 */ 9776 if (ca0132_use_pci_mmio(spec)) 9777 spec->desktop_init_verbs = ca0132_init_verbs1; 9778 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 9779 sizeof(struct hda_verb), 9780 GFP_KERNEL); 9781 if (!spec->spec_init_verbs) 9782 return -ENOMEM; 9783 9784 /* config EAPD */ 9785 spec->spec_init_verbs[0].nid = 0x0b; 9786 spec->spec_init_verbs[0].param = 0x78D; 9787 spec->spec_init_verbs[0].verb = 0x00; 9788 9789 /* Previously commented configuration */ 9790 /* 9791 spec->spec_init_verbs[2].nid = 0x0b; 9792 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9793 spec->spec_init_verbs[2].verb = 0x02; 9794 9795 spec->spec_init_verbs[3].nid = 0x10; 9796 spec->spec_init_verbs[3].param = 0x78D; 9797 spec->spec_init_verbs[3].verb = 0x02; 9798 9799 spec->spec_init_verbs[4].nid = 0x10; 9800 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9801 spec->spec_init_verbs[4].verb = 0x02; 9802 */ 9803 9804 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9805 return 0; 9806} 9807 9808/* 9809 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9810 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9811 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9812 * daughter boards ID. 9813 */ 9814static void sbz_detect_quirk(struct hda_codec *codec) 9815{ 9816 struct ca0132_spec *spec = codec->spec; 9817 9818 switch (codec->core.subsystem_id) { 9819 case 0x11020033: 9820 spec->quirk = QUIRK_ZXR; 9821 break; 9822 case 0x1102003f: 9823 spec->quirk = QUIRK_ZXR_DBPRO; 9824 break; 9825 default: 9826 spec->quirk = QUIRK_SBZ; 9827 break; 9828 } 9829} 9830 9831static int patch_ca0132(struct hda_codec *codec) 9832{ 9833 struct ca0132_spec *spec; 9834 int err; 9835 const struct snd_pci_quirk *quirk; 9836 9837 codec_dbg(codec, "patch_ca0132\n"); 9838 9839 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 9840 if (!spec) 9841 return -ENOMEM; 9842 codec->spec = spec; 9843 spec->codec = codec; 9844 9845 /* Detect codec quirk */ 9846 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 9847 if (quirk) 9848 spec->quirk = quirk->value; 9849 else 9850 spec->quirk = QUIRK_NONE; 9851 if (ca0132_quirk(spec) == QUIRK_SBZ) 9852 sbz_detect_quirk(codec); 9853 9854 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 9855 codec->patch_ops = dbpro_patch_ops; 9856 else 9857 codec->patch_ops = ca0132_patch_ops; 9858 9859 codec->pcm_format_first = 1; 9860 codec->no_sticky_stream = 1; 9861 9862 9863 spec->dsp_state = DSP_DOWNLOAD_INIT; 9864 spec->num_mixers = 1; 9865 9866 /* Set which mixers each quirk uses. */ 9867 switch (ca0132_quirk(spec)) { 9868 case QUIRK_SBZ: 9869 spec->mixers[0] = desktop_mixer; 9870 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 9871 break; 9872 case QUIRK_ZXR: 9873 spec->mixers[0] = desktop_mixer; 9874 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 9875 break; 9876 case QUIRK_ZXR_DBPRO: 9877 break; 9878 case QUIRK_R3D: 9879 spec->mixers[0] = desktop_mixer; 9880 snd_hda_codec_set_name(codec, "Recon3D"); 9881 break; 9882 case QUIRK_R3DI: 9883 spec->mixers[0] = r3di_mixer; 9884 snd_hda_codec_set_name(codec, "Recon3Di"); 9885 break; 9886 case QUIRK_AE5: 9887 spec->mixers[0] = desktop_mixer; 9888 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 9889 break; 9890 case QUIRK_AE7: 9891 spec->mixers[0] = desktop_mixer; 9892 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 9893 break; 9894 default: 9895 spec->mixers[0] = ca0132_mixer; 9896 break; 9897 } 9898 9899 /* Setup whether or not to use alt functions/controls/pci_mmio */ 9900 switch (ca0132_quirk(spec)) { 9901 case QUIRK_SBZ: 9902 case QUIRK_R3D: 9903 case QUIRK_AE5: 9904 case QUIRK_AE7: 9905 case QUIRK_ZXR: 9906 spec->use_alt_controls = true; 9907 spec->use_alt_functions = true; 9908 spec->use_pci_mmio = true; 9909 break; 9910 case QUIRK_R3DI: 9911 spec->use_alt_controls = true; 9912 spec->use_alt_functions = true; 9913 spec->use_pci_mmio = false; 9914 break; 9915 default: 9916 spec->use_alt_controls = false; 9917 spec->use_alt_functions = false; 9918 spec->use_pci_mmio = false; 9919 break; 9920 } 9921 9922#ifdef CONFIG_PCI 9923 if (spec->use_pci_mmio) { 9924 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 9925 if (spec->mem_base == NULL) { 9926 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 9927 spec->quirk = QUIRK_NONE; 9928 } 9929 } 9930#endif 9931 9932 spec->base_init_verbs = ca0132_base_init_verbs; 9933 spec->base_exit_verbs = ca0132_base_exit_verbs; 9934 9935 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 9936 9937 ca0132_init_chip(codec); 9938 9939 ca0132_config(codec); 9940 9941 err = ca0132_prepare_verbs(codec); 9942 if (err < 0) 9943 goto error; 9944 9945 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 9946 if (err < 0) 9947 goto error; 9948 9949 return 0; 9950 9951 error: 9952 ca0132_free(codec); 9953 return err; 9954} 9955 9956/* 9957 * patch entries 9958 */ 9959static const struct hda_device_id snd_hda_id_ca0132[] = { 9960 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 9961 {} /* terminator */ 9962}; 9963MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 9964 9965MODULE_LICENSE("GPL"); 9966MODULE_DESCRIPTION("Creative Sound Core3D codec"); 9967 9968static struct hda_codec_driver ca0132_driver = { 9969 .id = snd_hda_id_ca0132, 9970}; 9971 9972module_hda_codec_driver(ca0132_driver); 9973