1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * 4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 5 */ 6 7#include <linux/clk.h> 8#include <linux/clocksource.h> 9#include <linux/completion.h> 10#include <linux/delay.h> 11#include <linux/dma-mapping.h> 12#include <linux/init.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/moduleparam.h> 18#include <linux/mutex.h> 19#include <linux/of_device.h> 20#include <linux/reset.h> 21#include <linux/slab.h> 22#include <linux/time.h> 23#include <linux/string.h> 24#include <linux/pm_runtime.h> 25 26#include <sound/core.h> 27#include <sound/initval.h> 28 29#include <sound/hda_codec.h> 30#include "hda_controller.h" 31 32/* Defines for Nvidia Tegra HDA support */ 33#define HDA_BAR0 0x8000 34 35#define HDA_CFG_CMD 0x1004 36#define HDA_CFG_BAR0 0x1010 37 38#define HDA_ENABLE_IO_SPACE (1 << 0) 39#define HDA_ENABLE_MEM_SPACE (1 << 1) 40#define HDA_ENABLE_BUS_MASTER (1 << 2) 41#define HDA_ENABLE_SERR (1 << 8) 42#define HDA_DISABLE_INTR (1 << 10) 43#define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 44#define HDA_BAR0_FINAL_PROGRAM (1 << 14) 45 46/* IPFS */ 47#define HDA_IPFS_CONFIG 0x180 48#define HDA_IPFS_EN_FPCI 0x1 49 50#define HDA_IPFS_FPCI_BAR0 0x80 51#define HDA_FPCI_BAR0_START 0x40 52 53#define HDA_IPFS_INTR_MASK 0x188 54#define HDA_IPFS_EN_INTR (1 << 16) 55 56/* FPCI */ 57#define FPCI_DBG_CFG_2 0x10F4 58#define FPCI_GCAP_NSDO_SHIFT 18 59#define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT) 60 61/* max number of SDs */ 62#define NUM_CAPTURE_SD 1 63#define NUM_PLAYBACK_SD 1 64 65/* 66 * Tegra194 does not reflect correct number of SDO lines. Below macro 67 * is used to update the GCAP register to workaround the issue. 68 */ 69#define TEGRA194_NUM_SDO_LINES 4 70 71struct hda_tegra { 72 struct azx chip; 73 struct device *dev; 74 struct reset_control *reset; 75 struct clk_bulk_data clocks[3]; 76 unsigned int nclocks; 77 void __iomem *regs; 78 struct work_struct probe_work; 79}; 80 81#ifdef CONFIG_PM 82static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 83module_param(power_save, bint, 0644); 84MODULE_PARM_DESC(power_save, 85 "Automatic power-saving timeout (in seconds, 0 = disable)."); 86#else 87#define power_save 0 88#endif 89 90static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 91 92static void hda_tegra_init(struct hda_tegra *hda) 93{ 94 u32 v; 95 96 /* Enable PCI access */ 97 v = readl(hda->regs + HDA_IPFS_CONFIG); 98 v |= HDA_IPFS_EN_FPCI; 99 writel(v, hda->regs + HDA_IPFS_CONFIG); 100 101 /* Enable MEM/IO space and bus master */ 102 v = readl(hda->regs + HDA_CFG_CMD); 103 v &= ~HDA_DISABLE_INTR; 104 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 105 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 106 writel(v, hda->regs + HDA_CFG_CMD); 107 108 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 109 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 110 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 111 112 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 113 v |= HDA_IPFS_EN_INTR; 114 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 115} 116 117/* 118 * power management 119 */ 120static int __maybe_unused hda_tegra_suspend(struct device *dev) 121{ 122 struct snd_card *card = dev_get_drvdata(dev); 123 int rc; 124 125 rc = pm_runtime_force_suspend(dev); 126 if (rc < 0) 127 return rc; 128 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 129 130 return 0; 131} 132 133static int __maybe_unused hda_tegra_resume(struct device *dev) 134{ 135 struct snd_card *card = dev_get_drvdata(dev); 136 int rc; 137 138 rc = pm_runtime_force_resume(dev); 139 if (rc < 0) 140 return rc; 141 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 142 143 return 0; 144} 145 146static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) 147{ 148 struct snd_card *card = dev_get_drvdata(dev); 149 struct azx *chip = card->private_data; 150 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 151 152 if (chip && chip->running) { 153 /* enable controller wake up event */ 154 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 155 STATESTS_INT_MASK); 156 157 azx_stop_chip(chip); 158 azx_enter_link_reset(chip); 159 } 160 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks); 161 162 return 0; 163} 164 165static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) 166{ 167 struct snd_card *card = dev_get_drvdata(dev); 168 struct azx *chip = card->private_data; 169 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 170 int rc; 171 172 if (!chip->running) { 173 rc = reset_control_assert(hda->reset); 174 if (rc) 175 return rc; 176 } 177 178 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks); 179 if (rc != 0) 180 return rc; 181 if (chip && chip->running) { 182 hda_tegra_init(hda); 183 azx_init_chip(chip, 1); 184 /* disable controller wake up event*/ 185 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 186 ~STATESTS_INT_MASK); 187 } else { 188 usleep_range(10, 100); 189 190 rc = reset_control_deassert(hda->reset); 191 if (rc) 192 return rc; 193 } 194 195 return 0; 196} 197 198static const struct dev_pm_ops hda_tegra_pm = { 199 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 200 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, 201 hda_tegra_runtime_resume, 202 NULL) 203}; 204 205static int hda_tegra_dev_disconnect(struct snd_device *device) 206{ 207 struct azx *chip = device->device_data; 208 209 chip->bus.shutdown = 1; 210 return 0; 211} 212 213/* 214 * destructor 215 */ 216static int hda_tegra_dev_free(struct snd_device *device) 217{ 218 struct azx *chip = device->device_data; 219 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 220 221 cancel_work_sync(&hda->probe_work); 222 if (azx_bus(chip)->chip_init) { 223 azx_stop_all_streams(chip); 224 azx_stop_chip(chip); 225 } 226 227 azx_free_stream_pages(chip); 228 azx_free_streams(chip); 229 snd_hdac_bus_exit(azx_bus(chip)); 230 231 return 0; 232} 233 234static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 235{ 236 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 237 struct hdac_bus *bus = azx_bus(chip); 238 struct device *dev = hda->dev; 239 struct resource *res; 240 241 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 242 hda->regs = devm_ioremap_resource(dev, res); 243 if (IS_ERR(hda->regs)) 244 return PTR_ERR(hda->regs); 245 246 bus->remap_addr = hda->regs + HDA_BAR0; 247 bus->addr = res->start + HDA_BAR0; 248 249 hda_tegra_init(hda); 250 251 return 0; 252} 253 254static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 255{ 256 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 257 struct hdac_bus *bus = azx_bus(chip); 258 struct snd_card *card = chip->card; 259 int err; 260 unsigned short gcap; 261 int irq_id = platform_get_irq(pdev, 0); 262 const char *sname, *drv_name = "tegra-hda"; 263 struct device_node *np = pdev->dev.of_node; 264 265 if (irq_id < 0) 266 return irq_id; 267 268 err = hda_tegra_init_chip(chip, pdev); 269 if (err) 270 return err; 271 272 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 273 IRQF_SHARED, KBUILD_MODNAME, chip); 274 if (err) { 275 dev_err(chip->card->dev, 276 "unable to request IRQ %d, disabling device\n", 277 irq_id); 278 return err; 279 } 280 bus->irq = irq_id; 281 bus->dma_stop_delay = 100; 282 card->sync_irq = bus->irq; 283 284 /* 285 * Tegra194 has 4 SDO lines and the STRIPE can be used to 286 * indicate how many of the SDO lines the stream should be 287 * striped. But GCAP register does not reflect the true 288 * capability of HW. Below workaround helps to fix this. 289 * 290 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2, 291 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines. 292 */ 293 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) { 294 u32 val; 295 296 dev_info(card->dev, "Override SDO lines to %u\n", 297 TEGRA194_NUM_SDO_LINES); 298 299 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK; 300 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT; 301 writel(val, hda->regs + FPCI_DBG_CFG_2); 302 } 303 304 gcap = azx_readw(chip, GCAP); 305 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 306 307 chip->align_buffer_size = 1; 308 309 /* read number of streams from GCAP register instead of using 310 * hardcoded value 311 */ 312 chip->capture_streams = (gcap >> 8) & 0x0f; 313 chip->playback_streams = (gcap >> 12) & 0x0f; 314 if (!chip->playback_streams && !chip->capture_streams) { 315 /* gcap didn't give any info, switching to old method */ 316 chip->playback_streams = NUM_PLAYBACK_SD; 317 chip->capture_streams = NUM_CAPTURE_SD; 318 } 319 chip->capture_index_offset = 0; 320 chip->playback_index_offset = chip->capture_streams; 321 chip->num_streams = chip->playback_streams + chip->capture_streams; 322 323 /* initialize streams */ 324 err = azx_init_streams(chip); 325 if (err < 0) { 326 dev_err(card->dev, "failed to initialize streams: %d\n", err); 327 return err; 328 } 329 330 err = azx_alloc_stream_pages(chip); 331 if (err < 0) { 332 dev_err(card->dev, "failed to allocate stream pages: %d\n", 333 err); 334 return err; 335 } 336 337 /* initialize chip */ 338 azx_init_chip(chip, 1); 339 340 /* 341 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with 342 * 4 SDO lines due to legacy design limitation. Following 343 * is, from HD Audio Specification (Revision 1.0a), used to 344 * control striping of the stream across multiple SDO lines 345 * for sample rates <= 48K. 346 * 347 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } 348 * 349 * Due to legacy design issue it is recommended that above 350 * ratio must be greater than 8. Since number of SDO lines is 351 * in powers of 2, next available ratio is 16 which can be 352 * used as a limiting factor here. 353 */ 354 if (of_device_is_compatible(np, "nvidia,tegra30-hda")) 355 chip->bus.core.sdo_limit = 16; 356 357 /* codec detection */ 358 if (!bus->codec_mask) { 359 dev_err(card->dev, "no codecs found!\n"); 360 return -ENODEV; 361 } 362 363 /* driver name */ 364 strncpy(card->driver, drv_name, sizeof(card->driver)); 365 /* shortname for card */ 366 sname = of_get_property(np, "nvidia,model", NULL); 367 if (!sname) 368 sname = drv_name; 369 if (strlen(sname) > sizeof(card->shortname)) 370 dev_info(card->dev, "truncating shortname for card\n"); 371 strncpy(card->shortname, sname, sizeof(card->shortname)); 372 373 /* longname for card */ 374 snprintf(card->longname, sizeof(card->longname), 375 "%s at 0x%lx irq %i", 376 card->shortname, bus->addr, bus->irq); 377 378 return 0; 379} 380 381/* 382 * constructor 383 */ 384 385static void hda_tegra_probe_work(struct work_struct *work); 386 387static int hda_tegra_create(struct snd_card *card, 388 unsigned int driver_caps, 389 struct hda_tegra *hda) 390{ 391 static const struct snd_device_ops ops = { 392 .dev_disconnect = hda_tegra_dev_disconnect, 393 .dev_free = hda_tegra_dev_free, 394 }; 395 struct azx *chip; 396 int err; 397 398 chip = &hda->chip; 399 400 mutex_init(&chip->open_mutex); 401 chip->card = card; 402 chip->ops = &hda_tegra_ops; 403 chip->driver_caps = driver_caps; 404 chip->driver_type = driver_caps & 0xff; 405 chip->dev_index = 0; 406 INIT_LIST_HEAD(&chip->pcm_list); 407 408 chip->codec_probe_mask = -1; 409 410 chip->single_cmd = false; 411 chip->snoop = true; 412 413 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 414 415 err = azx_bus_init(chip, NULL); 416 if (err < 0) 417 return err; 418 419 chip->bus.core.sync_write = 0; 420 chip->bus.core.needs_damn_long_delay = 1; 421 chip->bus.core.aligned_mmio = 1; 422 423 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 424 if (err < 0) { 425 dev_err(card->dev, "Error creating device\n"); 426 return err; 427 } 428 429 return 0; 430} 431 432static const struct of_device_id hda_tegra_match[] = { 433 { .compatible = "nvidia,tegra30-hda" }, 434 { .compatible = "nvidia,tegra194-hda" }, 435 {}, 436}; 437MODULE_DEVICE_TABLE(of, hda_tegra_match); 438 439static int hda_tegra_probe(struct platform_device *pdev) 440{ 441 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 442 AZX_DCAPS_PM_RUNTIME | 443 AZX_DCAPS_4K_BDLE_BOUNDARY; 444 struct snd_card *card; 445 struct azx *chip; 446 struct hda_tegra *hda; 447 int err; 448 449 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 450 if (!hda) 451 return -ENOMEM; 452 hda->dev = &pdev->dev; 453 chip = &hda->chip; 454 455 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 456 THIS_MODULE, 0, &card); 457 if (err < 0) { 458 dev_err(&pdev->dev, "Error creating card!\n"); 459 return err; 460 } 461 462 hda->reset = devm_reset_control_array_get_exclusive(&pdev->dev); 463 if (IS_ERR(hda->reset)) { 464 err = PTR_ERR(hda->reset); 465 goto out_free; 466 } 467 468 hda->clocks[hda->nclocks++].id = "hda"; 469 hda->clocks[hda->nclocks++].id = "hda2hdmi"; 470 hda->clocks[hda->nclocks++].id = "hda2codec_2x"; 471 472 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks); 473 if (err < 0) 474 goto out_free; 475 476 err = hda_tegra_create(card, driver_flags, hda); 477 if (err < 0) 478 goto out_free; 479 card->private_data = chip; 480 481 dev_set_drvdata(&pdev->dev, card); 482 483 pm_runtime_enable(hda->dev); 484 if (!azx_has_pm_runtime(chip)) 485 pm_runtime_forbid(hda->dev); 486 487 schedule_work(&hda->probe_work); 488 489 return 0; 490 491out_free: 492 snd_card_free(card); 493 return err; 494} 495 496static void hda_tegra_probe_work(struct work_struct *work) 497{ 498 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 499 struct azx *chip = &hda->chip; 500 struct platform_device *pdev = to_platform_device(hda->dev); 501 int err; 502 503 pm_runtime_get_sync(hda->dev); 504 err = hda_tegra_first_init(chip, pdev); 505 if (err < 0) 506 goto out_free; 507 508 /* create codec instances */ 509 err = azx_probe_codecs(chip, 8); 510 if (err < 0) 511 goto out_free; 512 513 err = azx_codec_configure(chip); 514 if (err < 0) 515 goto out_free; 516 517 err = snd_card_register(chip->card); 518 if (err < 0) 519 goto out_free; 520 521 chip->running = 1; 522 snd_hda_set_power_save(&chip->bus, power_save * 1000); 523 524 out_free: 525 pm_runtime_put(hda->dev); 526 return; /* no error return from async probe */ 527} 528 529static int hda_tegra_remove(struct platform_device *pdev) 530{ 531 int ret; 532 533 ret = snd_card_free(dev_get_drvdata(&pdev->dev)); 534 pm_runtime_disable(&pdev->dev); 535 536 return ret; 537} 538 539static void hda_tegra_shutdown(struct platform_device *pdev) 540{ 541 struct snd_card *card = dev_get_drvdata(&pdev->dev); 542 struct azx *chip; 543 544 if (!card) 545 return; 546 chip = card->private_data; 547 if (chip && chip->running) 548 azx_stop_chip(chip); 549} 550 551static struct platform_driver tegra_platform_hda = { 552 .driver = { 553 .name = "tegra-hda", 554 .pm = &hda_tegra_pm, 555 .of_match_table = hda_tegra_match, 556 }, 557 .probe = hda_tegra_probe, 558 .remove = hda_tegra_remove, 559 .shutdown = hda_tegra_shutdown, 560}; 561module_platform_driver(tegra_platform_hda); 562 563MODULE_DESCRIPTION("Tegra HDA bus driver"); 564MODULE_LICENSE("GPL v2"); 565