1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23#include <linux/delay.h> 24#include <linux/interrupt.h> 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/dma-mapping.h> 28#include <linux/moduleparam.h> 29#include <linux/init.h> 30#include <linux/slab.h> 31#include <linux/pci.h> 32#include <linux/mutex.h> 33#include <linux/io.h> 34#include <linux/pm_runtime.h> 35#include <linux/clocksource.h> 36#include <linux/time.h> 37#include <linux/completion.h> 38#include <linux/acpi.h> 39#include <linux/pgtable.h> 40 41#ifdef CONFIG_X86 42/* for snoop control */ 43#include <asm/set_memory.h> 44#include <asm/cpufeature.h> 45#endif 46#include <sound/core.h> 47#include <sound/initval.h> 48#include <sound/hdaudio.h> 49#include <sound/hda_i915.h> 50#include <sound/intel-dsp-config.h> 51#include <linux/vgaarb.h> 52#include <linux/vga_switcheroo.h> 53#include <linux/firmware.h> 54#include <sound/hda_codec.h> 55#include "hda_controller.h" 56#include "hda_intel.h" 57 58#define CREATE_TRACE_POINTS 59#include "hda_intel_trace.h" 60 61/* position fix mode */ 62enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70}; 71 72/* Defines for ATI HD Audio support in SB450 south bridge */ 73#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76/* Defines for Nvidia HDA support */ 77#define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78#define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79#define NVIDIA_HDA_ISTRM_COH 0x4d 80#define NVIDIA_HDA_OSTRM_COH 0x4c 81#define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83/* Defines for Intel SCH HDA snoop control */ 84#define INTEL_HDA_CGCTL 0x48 85#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86#define INTEL_SCH_HDA_DEVC 0x78 87#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89/* Define VIA HD Audio Device ID*/ 90#define VIA_HDAC_DEVICE_ID 0x3288 91 92/* max number of SDs */ 93/* ICH, ATI and VIA have 4 playback and 4 capture */ 94#define ICH6_NUM_CAPTURE 4 95#define ICH6_NUM_PLAYBACK 4 96 97/* ULI has 6 playback and 5 capture */ 98#define ULI_NUM_CAPTURE 5 99#define ULI_NUM_PLAYBACK 6 100 101/* ATI HDMI may have up to 8 playbacks and 0 capture */ 102#define ATIHDMI_NUM_CAPTURE 0 103#define ATIHDMI_NUM_PLAYBACK 8 104 105/* TERA has 4 playback and 3 capture */ 106#define TERA_NUM_CAPTURE 3 107#define TERA_NUM_PLAYBACK 4 108 109 110static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113static char *model[SNDRV_CARDS]; 114static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117static int probe_only[SNDRV_CARDS]; 118static int jackpoll_ms[SNDRV_CARDS]; 119static int single_cmd = -1; 120static int enable_msi = -1; 121#ifdef CONFIG_SND_HDA_PATCH_LOADER 122static char *patch[SNDRV_CARDS]; 123#endif 124#ifdef CONFIG_SND_HDA_INPUT_BEEP 125static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127#endif 128static bool dmic_detect = 1; 129 130module_param_array(index, int, NULL, 0444); 131MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132module_param_array(id, charp, NULL, 0444); 133MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134module_param_array(enable, bool, NULL, 0444); 135MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136module_param_array(model, charp, NULL, 0444); 137MODULE_PARM_DESC(model, "Use the given board model."); 138module_param_array(position_fix, int, NULL, 0444); 139MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141module_param_array(bdl_pos_adj, int, NULL, 0644); 142MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143module_param_array(probe_mask, int, NULL, 0444); 144MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145module_param_array(probe_only, int, NULL, 0444); 146MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147module_param_array(jackpoll_ms, int, NULL, 0444); 148MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149module_param(single_cmd, bint, 0444); 150MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152module_param(enable_msi, bint, 0444); 153MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154#ifdef CONFIG_SND_HDA_PATCH_LOADER 155module_param_array(patch, charp, NULL, 0444); 156MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157#endif 158#ifdef CONFIG_SND_HDA_INPUT_BEEP 159module_param_array(beep_mode, bool, NULL, 0444); 160MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162#endif 163module_param(dmic_detect, bool, 0444); 164MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1); " 166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 167 168#ifdef CONFIG_PM 169static int param_set_xint(const char *val, const struct kernel_param *kp); 170static const struct kernel_param_ops param_ops_xint = { 171 .set = param_set_xint, 172 .get = param_get_int, 173}; 174#define param_check_xint param_check_int 175 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 177module_param(power_save, xint, 0644); 178MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 179 "(in second, 0 = disable)."); 180 181static bool pm_blacklist = true; 182module_param(pm_blacklist, bool, 0644); 183MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 184 185/* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189static bool power_save_controller = 1; 190module_param(power_save_controller, bool, 0644); 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192#else 193#define power_save 0 194#endif /* CONFIG_PM */ 195 196static int align_buffer_size = -1; 197module_param(align_buffer_size, bint, 0644); 198MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201#ifdef CONFIG_X86 202static int hda_snoop = -1; 203module_param_named(snoop, hda_snoop, bint, 0444); 204MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205#else 206#define hda_snoop true 207#endif 208 209 210MODULE_LICENSE("GPL"); 211MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 212 "{Intel, ICH6M}," 213 "{Intel, ICH7}," 214 "{Intel, ESB2}," 215 "{Intel, ICH8}," 216 "{Intel, ICH9}," 217 "{Intel, ICH10}," 218 "{Intel, PCH}," 219 "{Intel, CPT}," 220 "{Intel, PPT}," 221 "{Intel, LPT}," 222 "{Intel, LPT_LP}," 223 "{Intel, WPT_LP}," 224 "{Intel, SPT}," 225 "{Intel, SPT_LP}," 226 "{Intel, HPT}," 227 "{Intel, PBG}," 228 "{Intel, SCH}," 229 "{ATI, SB450}," 230 "{ATI, SB600}," 231 "{ATI, RS600}," 232 "{ATI, RS690}," 233 "{ATI, RS780}," 234 "{ATI, R600}," 235 "{ATI, RV630}," 236 "{ATI, RV610}," 237 "{ATI, RV670}," 238 "{ATI, RV635}," 239 "{ATI, RV620}," 240 "{ATI, RV770}," 241 "{VIA, VT8251}," 242 "{VIA, VT8237A}," 243 "{SiS, SIS966}," 244 "{ULI, M5461}}"); 245MODULE_DESCRIPTION("Intel HDA driver"); 246 247#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 248#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 249#define SUPPORT_VGA_SWITCHEROO 250#endif 251#endif 252 253 254/* 255 */ 256 257/* driver types */ 258enum { 259 AZX_DRIVER_ICH, 260 AZX_DRIVER_PCH, 261 AZX_DRIVER_SCH, 262 AZX_DRIVER_SKL, 263 AZX_DRIVER_HDMI, 264 AZX_DRIVER_ATI, 265 AZX_DRIVER_ATIHDMI, 266 AZX_DRIVER_ATIHDMI_NS, 267 AZX_DRIVER_GFHDMI, 268 AZX_DRIVER_VIA, 269 AZX_DRIVER_SIS, 270 AZX_DRIVER_ULI, 271 AZX_DRIVER_NVIDIA, 272 AZX_DRIVER_TERA, 273 AZX_DRIVER_CTX, 274 AZX_DRIVER_CTHDA, 275 AZX_DRIVER_CMEDIA, 276 AZX_DRIVER_ZHAOXIN, 277 AZX_DRIVER_GENERIC, 278 AZX_NUM_DRIVERS, /* keep this as last entry */ 279}; 280 281#define azx_get_snoop_type(chip) \ 282 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 283#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 284 285/* quirks for old Intel chipsets */ 286#define AZX_DCAPS_INTEL_ICH \ 287 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 288 289/* quirks for Intel PCH */ 290#define AZX_DCAPS_INTEL_PCH_BASE \ 291 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 292 AZX_DCAPS_SNOOP_TYPE(SCH)) 293 294/* PCH up to IVB; no runtime PM; bind with i915 gfx */ 295#define AZX_DCAPS_INTEL_PCH_NOPM \ 296 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 297 298/* PCH for HSW/BDW; with runtime PM */ 299/* no i915 binding for this as HSW/BDW has another controller for HDMI */ 300#define AZX_DCAPS_INTEL_PCH \ 301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 302 303/* HSW HDMI */ 304#define AZX_DCAPS_INTEL_HASWELL \ 305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 307 AZX_DCAPS_SNOOP_TYPE(SCH)) 308 309/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 310#define AZX_DCAPS_INTEL_BROADWELL \ 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 313 AZX_DCAPS_SNOOP_TYPE(SCH)) 314 315#define AZX_DCAPS_INTEL_BAYTRAIL \ 316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 317 318#define AZX_DCAPS_INTEL_BRASWELL \ 319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 320 AZX_DCAPS_I915_COMPONENT) 321 322#define AZX_DCAPS_INTEL_SKYLAKE \ 323 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 324 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 325 326#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 327 328/* quirks for ATI SB / AMD Hudson */ 329#define AZX_DCAPS_PRESET_ATI_SB \ 330 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 331 AZX_DCAPS_SNOOP_TYPE(ATI)) 332 333/* quirks for ATI/AMD HDMI */ 334#define AZX_DCAPS_PRESET_ATI_HDMI \ 335 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 336 AZX_DCAPS_NO_MSI64) 337 338/* quirks for ATI HDMI with snoop off */ 339#define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 340 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 341 342/* quirks for AMD SB */ 343#define AZX_DCAPS_PRESET_AMD_SB \ 344 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 345 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 346 AZX_DCAPS_RETRY_PROBE) 347 348/* quirks for Nvidia */ 349#define AZX_DCAPS_PRESET_NVIDIA \ 350 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 351 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 352 353#define AZX_DCAPS_PRESET_CTHDA \ 354 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 355 AZX_DCAPS_NO_64BIT |\ 356 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 357 358/* 359 * vga_switcheroo support 360 */ 361#ifdef SUPPORT_VGA_SWITCHEROO 362#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 363#define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 364#else 365#define use_vga_switcheroo(chip) 0 366#define needs_eld_notify_link(chip) false 367#endif 368 369#define CONTROLLER_IN_GPU(pci) (((pci)->vendor == 0x8086) && \ 370 (((pci)->device == 0x0a0c) || \ 371 ((pci)->device == 0x0c0c) || \ 372 ((pci)->device == 0x0d0c) || \ 373 ((pci)->device == 0x160c) || \ 374 ((pci)->device == 0x490d) || \ 375 ((pci)->device == 0x4f90) || \ 376 ((pci)->device == 0x4f91) || \ 377 ((pci)->device == 0x4f92))) 378 379#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 380 381static const char * const driver_short_names[] = { 382 [AZX_DRIVER_ICH] = "HDA Intel", 383 [AZX_DRIVER_PCH] = "HDA Intel PCH", 384 [AZX_DRIVER_SCH] = "HDA Intel MID", 385 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 386 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 387 [AZX_DRIVER_ATI] = "HDA ATI SB", 388 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 389 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 390 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 391 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 392 [AZX_DRIVER_SIS] = "HDA SIS966", 393 [AZX_DRIVER_ULI] = "HDA ULI M5461", 394 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 395 [AZX_DRIVER_TERA] = "HDA Teradici", 396 [AZX_DRIVER_CTX] = "HDA Creative", 397 [AZX_DRIVER_CTHDA] = "HDA Creative", 398 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 399 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 400 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 401}; 402 403static int azx_acquire_irq(struct azx *chip, int do_disconnect); 404static void set_default_power_save(struct azx *chip); 405 406/* 407 * initialize the PCI registers 408 */ 409/* update bits in a PCI register byte */ 410static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 411 unsigned char mask, unsigned char val) 412{ 413 unsigned char data; 414 415 pci_read_config_byte(pci, reg, &data); 416 data &= ~mask; 417 data |= (val & mask); 418 pci_write_config_byte(pci, reg, data); 419} 420 421static void azx_init_pci(struct azx *chip) 422{ 423 int snoop_type = azx_get_snoop_type(chip); 424 425 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 426 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 427 * Ensuring these bits are 0 clears playback static on some HD Audio 428 * codecs. 429 * The PCI register TCSEL is defined in the Intel manuals. 430 */ 431 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 432 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 433 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 434 } 435 436 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 437 * we need to enable snoop. 438 */ 439 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 440 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 441 azx_snoop(chip)); 442 update_pci_byte(chip->pci, 443 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 444 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 445 } 446 447 /* For NVIDIA HDA, enable snoop */ 448 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 449 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 450 azx_snoop(chip)); 451 update_pci_byte(chip->pci, 452 NVIDIA_HDA_TRANSREG_ADDR, 453 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 454 update_pci_byte(chip->pci, 455 NVIDIA_HDA_ISTRM_COH, 456 0x01, NVIDIA_HDA_ENABLE_COHBIT); 457 update_pci_byte(chip->pci, 458 NVIDIA_HDA_OSTRM_COH, 459 0x01, NVIDIA_HDA_ENABLE_COHBIT); 460 } 461 462 /* Enable SCH/PCH snoop if needed */ 463 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 464 unsigned short snoop; 465 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 466 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 467 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 468 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 469 if (!azx_snoop(chip)) 470 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 471 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 472 pci_read_config_word(chip->pci, 473 INTEL_SCH_HDA_DEVC, &snoop); 474 } 475 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 476 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 477 "Disabled" : "Enabled"); 478 } 479} 480 481/* 482 * In BXT-P A0, HD-Audio DMA requests is later than expected, 483 * and makes an audio stream sensitive to system latencies when 484 * 24/32 bits are playing. 485 * Adjusting threshold of DMA fifo to force the DMA request 486 * sooner to improve latency tolerance at the expense of power. 487 */ 488static void bxt_reduce_dma_latency(struct azx *chip) 489{ 490 u32 val; 491 492 val = azx_readl(chip, VS_EM4L); 493 val &= (0x3 << 20); 494 azx_writel(chip, VS_EM4L, val); 495} 496 497/* 498 * ML_LCAP bits: 499 * bit 0: 6 MHz Supported 500 * bit 1: 12 MHz Supported 501 * bit 2: 24 MHz Supported 502 * bit 3: 48 MHz Supported 503 * bit 4: 96 MHz Supported 504 * bit 5: 192 MHz Supported 505 */ 506static int intel_get_lctl_scf(struct azx *chip) 507{ 508 struct hdac_bus *bus = azx_bus(chip); 509 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 510 u32 val, t; 511 int i; 512 513 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 514 515 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 516 t = preferred_bits[i]; 517 if (val & (1 << t)) 518 return t; 519 } 520 521 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 522 return 0; 523} 524 525static int intel_ml_lctl_set_power(struct azx *chip, int state) 526{ 527 struct hdac_bus *bus = azx_bus(chip); 528 u32 val; 529 int timeout; 530 531 /* 532 * the codecs are sharing the first link setting by default 533 * If other links are enabled for stream, they need similar fix 534 */ 535 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 536 val &= ~AZX_MLCTL_SPA; 537 val |= state << AZX_MLCTL_SPA_SHIFT; 538 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 539 /* wait for CPA */ 540 timeout = 50; 541 while (timeout) { 542 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 543 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 544 return 0; 545 timeout--; 546 udelay(10); 547 } 548 549 return -1; 550} 551 552static void intel_init_lctl(struct azx *chip) 553{ 554 struct hdac_bus *bus = azx_bus(chip); 555 u32 val; 556 int ret; 557 558 /* 0. check lctl register value is correct or not */ 559 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 560 /* if SCF is already set, let's use it */ 561 if ((val & ML_LCTL_SCF_MASK) != 0) 562 return; 563 564 /* 565 * Before operating on SPA, CPA must match SPA. 566 * Any deviation may result in undefined behavior. 567 */ 568 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 569 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 570 return; 571 572 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 573 ret = intel_ml_lctl_set_power(chip, 0); 574 udelay(100); 575 if (ret) 576 goto set_spa; 577 578 /* 2. update SCF to select a properly audio clock*/ 579 val &= ~ML_LCTL_SCF_MASK; 580 val |= intel_get_lctl_scf(chip); 581 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 582 583set_spa: 584 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 585 intel_ml_lctl_set_power(chip, 1); 586 udelay(100); 587} 588 589static void hda_intel_init_chip(struct azx *chip, bool full_reset) 590{ 591 struct hdac_bus *bus = azx_bus(chip); 592 struct pci_dev *pci = chip->pci; 593 u32 val; 594 595 snd_hdac_set_codec_wakeup(bus, true); 596 if (chip->driver_type == AZX_DRIVER_SKL) { 597 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 598 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 599 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 600 } 601 azx_init_chip(chip, full_reset); 602 if (chip->driver_type == AZX_DRIVER_SKL) { 603 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 604 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 605 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 606 } 607 608 snd_hdac_set_codec_wakeup(bus, false); 609 610 /* reduce dma latency to avoid noise */ 611 if (IS_BXT(pci)) 612 bxt_reduce_dma_latency(chip); 613 614 if (bus->mlcap != NULL) 615 intel_init_lctl(chip); 616} 617 618/* calculate runtime delay from LPIB */ 619static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 620 unsigned int pos) 621{ 622 struct snd_pcm_substream *substream = azx_dev->core.substream; 623 int stream = substream->stream; 624 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 625 int delay; 626 627 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 628 delay = pos - lpib_pos; 629 else 630 delay = lpib_pos - pos; 631 if (delay < 0) { 632 if (delay >= azx_dev->core.delay_negative_threshold) 633 delay = 0; 634 else 635 delay += azx_dev->core.bufsize; 636 } 637 638 if (delay >= azx_dev->core.period_bytes) { 639 dev_info(chip->card->dev, 640 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 641 delay, azx_dev->core.period_bytes); 642 delay = 0; 643 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 644 chip->get_delay[stream] = NULL; 645 } 646 647 return bytes_to_frames(substream->runtime, delay); 648} 649 650static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 651 652/* called from IRQ */ 653static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 654{ 655 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 656 int ok; 657 658 ok = azx_position_ok(chip, azx_dev); 659 if (ok == 1) { 660 azx_dev->irq_pending = 0; 661 return ok; 662 } else if (ok == 0) { 663 /* bogus IRQ, process it later */ 664 azx_dev->irq_pending = 1; 665 schedule_work(&hda->irq_pending_work); 666 } 667 return 0; 668} 669 670#define display_power(chip, enable) \ 671 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 672 673/* 674 * Check whether the current DMA position is acceptable for updating 675 * periods. Returns non-zero if it's OK. 676 * 677 * Many HD-audio controllers appear pretty inaccurate about 678 * the update-IRQ timing. The IRQ is issued before actually the 679 * data is processed. So, we need to process it afterwords in a 680 * workqueue. 681 * 682 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 683 */ 684static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 685{ 686 struct snd_pcm_substream *substream = azx_dev->core.substream; 687 struct snd_pcm_runtime *runtime = substream->runtime; 688 int stream = substream->stream; 689 u32 wallclk; 690 unsigned int pos; 691 snd_pcm_uframes_t hwptr, target; 692 693 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 694 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 695 return -1; /* bogus (too early) interrupt */ 696 697 if (chip->get_position[stream]) 698 pos = chip->get_position[stream](chip, azx_dev); 699 else { /* use the position buffer as default */ 700 pos = azx_get_pos_posbuf(chip, azx_dev); 701 if (!pos || pos == (u32)-1) { 702 dev_info(chip->card->dev, 703 "Invalid position buffer, using LPIB read method instead.\n"); 704 chip->get_position[stream] = azx_get_pos_lpib; 705 if (chip->get_position[0] == azx_get_pos_lpib && 706 chip->get_position[1] == azx_get_pos_lpib) 707 azx_bus(chip)->use_posbuf = false; 708 pos = azx_get_pos_lpib(chip, azx_dev); 709 chip->get_delay[stream] = NULL; 710 } else { 711 chip->get_position[stream] = azx_get_pos_posbuf; 712 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 713 chip->get_delay[stream] = azx_get_delay_from_lpib; 714 } 715 } 716 717 if (pos >= azx_dev->core.bufsize) 718 pos = 0; 719 720 if (WARN_ONCE(!azx_dev->core.period_bytes, 721 "hda-intel: zero azx_dev->period_bytes")) 722 return -1; /* this shouldn't happen! */ 723 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 724 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 725 /* NG - it's below the first next period boundary */ 726 return chip->bdl_pos_adj ? 0 : -1; 727 azx_dev->core.start_wallclk += wallclk; 728 729 if (azx_dev->core.no_period_wakeup) 730 return 1; /* OK, no need to check period boundary */ 731 732 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 733 return 1; /* OK, already in hwptr updating process */ 734 735 /* check whether the period gets really elapsed */ 736 pos = bytes_to_frames(runtime, pos); 737 hwptr = runtime->hw_ptr_base + pos; 738 if (hwptr < runtime->status->hw_ptr) 739 hwptr += runtime->buffer_size; 740 target = runtime->hw_ptr_interrupt + runtime->period_size; 741 if (hwptr < target) { 742 /* too early wakeup, process it later */ 743 return chip->bdl_pos_adj ? 0 : -1; 744 } 745 746 return 1; /* OK, it's fine */ 747} 748 749/* 750 * The work for pending PCM period updates. 751 */ 752static void azx_irq_pending_work(struct work_struct *work) 753{ 754 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 755 struct azx *chip = &hda->chip; 756 struct hdac_bus *bus = azx_bus(chip); 757 struct hdac_stream *s; 758 int pending, ok; 759 760 if (!hda->irq_pending_warned) { 761 dev_info(chip->card->dev, 762 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 763 chip->card->number); 764 hda->irq_pending_warned = 1; 765 } 766 767 for (;;) { 768 pending = 0; 769 spin_lock_irq(&bus->reg_lock); 770 list_for_each_entry(s, &bus->stream_list, list) { 771 struct azx_dev *azx_dev = stream_to_azx_dev(s); 772 if (!azx_dev->irq_pending || 773 !s->substream || 774 !s->running) 775 continue; 776 ok = azx_position_ok(chip, azx_dev); 777 if (ok > 0) { 778 azx_dev->irq_pending = 0; 779 spin_unlock(&bus->reg_lock); 780 snd_pcm_period_elapsed(s->substream); 781 spin_lock(&bus->reg_lock); 782 } else if (ok < 0) { 783 pending = 0; /* too early */ 784 } else 785 pending++; 786 } 787 spin_unlock_irq(&bus->reg_lock); 788 if (!pending) 789 return; 790 msleep(1); 791 } 792} 793 794/* clear irq_pending flags and assure no on-going workq */ 795static void azx_clear_irq_pending(struct azx *chip) 796{ 797 struct hdac_bus *bus = azx_bus(chip); 798 struct hdac_stream *s; 799 800 spin_lock_irq(&bus->reg_lock); 801 list_for_each_entry(s, &bus->stream_list, list) { 802 struct azx_dev *azx_dev = stream_to_azx_dev(s); 803 azx_dev->irq_pending = 0; 804 } 805 spin_unlock_irq(&bus->reg_lock); 806} 807 808static int azx_acquire_irq(struct azx *chip, int do_disconnect) 809{ 810 struct hdac_bus *bus = azx_bus(chip); 811 812 if (request_irq(chip->pci->irq, azx_interrupt, 813 chip->msi ? 0 : IRQF_SHARED, 814 chip->card->irq_descr, chip)) { 815 dev_err(chip->card->dev, 816 "unable to grab IRQ %d, disabling device\n", 817 chip->pci->irq); 818 if (do_disconnect) 819 snd_card_disconnect(chip->card); 820 return -1; 821 } 822 bus->irq = chip->pci->irq; 823 chip->card->sync_irq = bus->irq; 824 pci_intx(chip->pci, !chip->msi); 825 return 0; 826} 827 828/* get the current DMA position with correction on VIA chips */ 829static unsigned int azx_via_get_position(struct azx *chip, 830 struct azx_dev *azx_dev) 831{ 832 unsigned int link_pos, mini_pos, bound_pos; 833 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 834 unsigned int fifo_size; 835 836 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 837 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 838 /* Playback, no problem using link position */ 839 return link_pos; 840 } 841 842 /* Capture */ 843 /* For new chipset, 844 * use mod to get the DMA position just like old chipset 845 */ 846 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 847 mod_dma_pos %= azx_dev->core.period_bytes; 848 849 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 850 851 if (azx_dev->insufficient) { 852 /* Link position never gather than FIFO size */ 853 if (link_pos <= fifo_size) 854 return 0; 855 856 azx_dev->insufficient = 0; 857 } 858 859 if (link_pos <= fifo_size) 860 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 861 else 862 mini_pos = link_pos - fifo_size; 863 864 /* Find nearest previous boudary */ 865 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 866 mod_link_pos = link_pos % azx_dev->core.period_bytes; 867 if (mod_link_pos >= fifo_size) 868 bound_pos = link_pos - mod_link_pos; 869 else if (mod_dma_pos >= mod_mini_pos) 870 bound_pos = mini_pos - mod_mini_pos; 871 else { 872 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 873 if (bound_pos >= azx_dev->core.bufsize) 874 bound_pos = 0; 875 } 876 877 /* Calculate real DMA position we want */ 878 return bound_pos + mod_dma_pos; 879} 880 881#define AMD_FIFO_SIZE 32 882 883/* get the current DMA position with FIFO size correction */ 884static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 885{ 886 struct snd_pcm_substream *substream = azx_dev->core.substream; 887 struct snd_pcm_runtime *runtime = substream->runtime; 888 unsigned int pos, delay; 889 890 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 891 if (!runtime) 892 return pos; 893 894 runtime->delay = AMD_FIFO_SIZE; 895 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 896 if (azx_dev->insufficient) { 897 if (pos < delay) { 898 delay = pos; 899 runtime->delay = bytes_to_frames(runtime, pos); 900 } else { 901 azx_dev->insufficient = 0; 902 } 903 } 904 905 /* correct the DMA position for capture stream */ 906 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 907 if (pos < delay) 908 pos += azx_dev->core.bufsize; 909 pos -= delay; 910 } 911 912 return pos; 913} 914 915static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 916 unsigned int pos) 917{ 918 struct snd_pcm_substream *substream = azx_dev->core.substream; 919 920 /* just read back the calculated value in the above */ 921 return substream->runtime->delay; 922} 923 924static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 925{ 926 azx_stop_chip(chip); 927 if (!skip_link_reset) 928 azx_enter_link_reset(chip); 929 azx_clear_irq_pending(chip); 930 display_power(chip, false); 931} 932 933#ifdef CONFIG_PM 934static DEFINE_MUTEX(card_list_lock); 935static LIST_HEAD(card_list); 936 937static void azx_shutdown_chip(struct azx *chip) 938{ 939 __azx_shutdown_chip(chip, false); 940} 941 942static void azx_add_card_list(struct azx *chip) 943{ 944 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 945 mutex_lock(&card_list_lock); 946 list_add(&hda->list, &card_list); 947 mutex_unlock(&card_list_lock); 948} 949 950static void azx_del_card_list(struct azx *chip) 951{ 952 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 953 mutex_lock(&card_list_lock); 954 list_del_init(&hda->list); 955 mutex_unlock(&card_list_lock); 956} 957 958/* trigger power-save check at writing parameter */ 959static int param_set_xint(const char *val, const struct kernel_param *kp) 960{ 961 struct hda_intel *hda; 962 struct azx *chip; 963 int prev = power_save; 964 int ret = param_set_int(val, kp); 965 966 if (ret || prev == power_save) 967 return ret; 968 969 mutex_lock(&card_list_lock); 970 list_for_each_entry(hda, &card_list, list) { 971 chip = &hda->chip; 972 if (!hda->probe_continued || chip->disabled) 973 continue; 974 snd_hda_set_power_save(&chip->bus, power_save * 1000); 975 } 976 mutex_unlock(&card_list_lock); 977 return 0; 978} 979 980/* 981 * power management 982 */ 983static bool azx_is_pm_ready(struct snd_card *card) 984{ 985 struct azx *chip; 986 struct hda_intel *hda; 987 988 if (!card) 989 return false; 990 chip = card->private_data; 991 hda = container_of(chip, struct hda_intel, chip); 992 if (chip->disabled || hda->init_failed || !chip->running) 993 return false; 994 return true; 995} 996 997static void __azx_runtime_resume(struct azx *chip) 998{ 999 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1000 struct hdac_bus *bus = azx_bus(chip); 1001 struct hda_codec *codec; 1002 int status; 1003 1004 display_power(chip, true); 1005 if (hda->need_i915_power) 1006 snd_hdac_i915_set_bclk(bus); 1007 1008 /* Read STATESTS before controller reset */ 1009 status = azx_readw(chip, STATESTS); 1010 1011 azx_init_pci(chip); 1012 hda_intel_init_chip(chip, true); 1013 1014 /* Avoid codec resume if runtime resume is for system suspend */ 1015 if (!chip->pm_prepared) { 1016 list_for_each_codec(codec, &chip->bus) { 1017 if (codec->relaxed_resume) 1018 continue; 1019 1020 if (codec->forced_resume || (status & (1 << codec->addr))) 1021 pm_request_resume(hda_codec_dev(codec)); 1022 } 1023 } 1024 1025 /* power down again for link-controlled chips */ 1026 if (!hda->need_i915_power) 1027 display_power(chip, false); 1028} 1029 1030#ifdef CONFIG_PM_SLEEP 1031static int azx_prepare(struct device *dev) 1032{ 1033 struct snd_card *card = dev_get_drvdata(dev); 1034 struct azx *chip; 1035 1036 if (!azx_is_pm_ready(card)) 1037 return 0; 1038 1039 chip = card->private_data; 1040 chip->pm_prepared = 1; 1041 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1042 1043 flush_work(&azx_bus(chip)->unsol_work); 1044 1045 /* HDA controller always requires different WAKEEN for runtime suspend 1046 * and system suspend, so don't use direct-complete here. 1047 */ 1048 return 0; 1049} 1050 1051static void azx_complete(struct device *dev) 1052{ 1053 struct snd_card *card = dev_get_drvdata(dev); 1054 struct azx *chip; 1055 1056 if (!azx_is_pm_ready(card)) 1057 return; 1058 1059 chip = card->private_data; 1060 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1061 chip->pm_prepared = 0; 1062} 1063 1064static int azx_suspend(struct device *dev) 1065{ 1066 struct snd_card *card = dev_get_drvdata(dev); 1067 struct azx *chip; 1068 struct hdac_bus *bus; 1069 1070 if (!azx_is_pm_ready(card)) 1071 return 0; 1072 1073 chip = card->private_data; 1074 bus = azx_bus(chip); 1075 azx_shutdown_chip(chip); 1076 if (bus->irq >= 0) { 1077 free_irq(bus->irq, chip); 1078 bus->irq = -1; 1079 chip->card->sync_irq = -1; 1080 } 1081 1082 if (chip->msi) 1083 pci_disable_msi(chip->pci); 1084 1085 trace_azx_suspend(chip); 1086 return 0; 1087} 1088 1089static int azx_resume(struct device *dev) 1090{ 1091 struct snd_card *card = dev_get_drvdata(dev); 1092 struct azx *chip; 1093 1094 if (!azx_is_pm_ready(card)) 1095 return 0; 1096 1097 chip = card->private_data; 1098 if (chip->msi) 1099 if (pci_enable_msi(chip->pci) < 0) 1100 chip->msi = 0; 1101 if (azx_acquire_irq(chip, 1) < 0) 1102 return -EIO; 1103 1104 __azx_runtime_resume(chip); 1105 1106 trace_azx_resume(chip); 1107 return 0; 1108} 1109 1110/* put codec down to D3 at hibernation for Intel SKL+; 1111 * otherwise BIOS may still access the codec and screw up the driver 1112 */ 1113static int azx_freeze_noirq(struct device *dev) 1114{ 1115 struct snd_card *card = dev_get_drvdata(dev); 1116 struct azx *chip = card->private_data; 1117 struct pci_dev *pci = to_pci_dev(dev); 1118 1119 if (!azx_is_pm_ready(card)) 1120 return 0; 1121 if (chip->driver_type == AZX_DRIVER_SKL) 1122 pci_set_power_state(pci, PCI_D3hot); 1123 1124 return 0; 1125} 1126 1127static int azx_thaw_noirq(struct device *dev) 1128{ 1129 struct snd_card *card = dev_get_drvdata(dev); 1130 struct azx *chip = card->private_data; 1131 struct pci_dev *pci = to_pci_dev(dev); 1132 1133 if (!azx_is_pm_ready(card)) 1134 return 0; 1135 if (chip->driver_type == AZX_DRIVER_SKL) 1136 pci_set_power_state(pci, PCI_D0); 1137 1138 return 0; 1139} 1140#endif /* CONFIG_PM_SLEEP */ 1141 1142static int azx_runtime_suspend(struct device *dev) 1143{ 1144 struct snd_card *card = dev_get_drvdata(dev); 1145 struct azx *chip; 1146 1147 if (!azx_is_pm_ready(card)) 1148 return 0; 1149 chip = card->private_data; 1150 1151 /* enable controller wake up event */ 1152 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1153 1154 azx_shutdown_chip(chip); 1155 trace_azx_runtime_suspend(chip); 1156 return 0; 1157} 1158 1159static int azx_runtime_resume(struct device *dev) 1160{ 1161 struct snd_card *card = dev_get_drvdata(dev); 1162 struct azx *chip; 1163 1164 if (!azx_is_pm_ready(card)) 1165 return 0; 1166 chip = card->private_data; 1167 __azx_runtime_resume(chip); 1168 1169 /* disable controller Wake Up event*/ 1170 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1171 1172 trace_azx_runtime_resume(chip); 1173 return 0; 1174} 1175 1176static int azx_runtime_idle(struct device *dev) 1177{ 1178 struct snd_card *card = dev_get_drvdata(dev); 1179 struct azx *chip; 1180 struct hda_intel *hda; 1181 1182 if (!card) 1183 return 0; 1184 1185 chip = card->private_data; 1186 hda = container_of(chip, struct hda_intel, chip); 1187 if (chip->disabled || hda->init_failed) 1188 return 0; 1189 1190 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1191 azx_bus(chip)->codec_powered || !chip->running) 1192 return -EBUSY; 1193 1194 /* ELD notification gets broken when HD-audio bus is off */ 1195 if (needs_eld_notify_link(chip)) 1196 return -EBUSY; 1197 1198 return 0; 1199} 1200 1201static const struct dev_pm_ops azx_pm = { 1202 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1203#ifdef CONFIG_PM_SLEEP 1204 .prepare = azx_prepare, 1205 .complete = azx_complete, 1206 .freeze_noirq = azx_freeze_noirq, 1207 .thaw_noirq = azx_thaw_noirq, 1208#endif 1209 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1210}; 1211 1212#define AZX_PM_OPS &azx_pm 1213#else 1214#define azx_add_card_list(chip) /* NOP */ 1215#define azx_del_card_list(chip) /* NOP */ 1216#define AZX_PM_OPS NULL 1217#endif /* CONFIG_PM */ 1218 1219 1220static int azx_probe_continue(struct azx *chip); 1221 1222#ifdef SUPPORT_VGA_SWITCHEROO 1223static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1224 1225static void azx_vs_set_state(struct pci_dev *pci, 1226 enum vga_switcheroo_state state) 1227{ 1228 struct snd_card *card = pci_get_drvdata(pci); 1229 struct azx *chip = card->private_data; 1230 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1231 struct hda_codec *codec; 1232 bool disabled; 1233 1234 wait_for_completion(&hda->probe_wait); 1235 if (hda->init_failed) 1236 return; 1237 1238 disabled = (state == VGA_SWITCHEROO_OFF); 1239 if (chip->disabled == disabled) 1240 return; 1241 1242 if (!hda->probe_continued) { 1243 chip->disabled = disabled; 1244 if (!disabled) { 1245 dev_info(chip->card->dev, 1246 "Start delayed initialization\n"); 1247 if (azx_probe_continue(chip) < 0) 1248 dev_err(chip->card->dev, "initialization error\n"); 1249 } 1250 } else { 1251 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1252 disabled ? "Disabling" : "Enabling"); 1253 if (disabled) { 1254 list_for_each_codec(codec, &chip->bus) { 1255 pm_runtime_suspend(hda_codec_dev(codec)); 1256 pm_runtime_disable(hda_codec_dev(codec)); 1257 } 1258 pm_runtime_suspend(card->dev); 1259 pm_runtime_disable(card->dev); 1260 /* when we get suspended by vga_switcheroo we end up in D3cold, 1261 * however we have no ACPI handle, so pci/acpi can't put us there, 1262 * put ourselves there */ 1263 pci->current_state = PCI_D3cold; 1264 chip->disabled = true; 1265 if (snd_hda_lock_devices(&chip->bus)) 1266 dev_warn(chip->card->dev, 1267 "Cannot lock devices!\n"); 1268 } else { 1269 snd_hda_unlock_devices(&chip->bus); 1270 chip->disabled = false; 1271 pm_runtime_enable(card->dev); 1272 list_for_each_codec(codec, &chip->bus) { 1273 pm_runtime_enable(hda_codec_dev(codec)); 1274 pm_runtime_resume(hda_codec_dev(codec)); 1275 } 1276 } 1277 } 1278} 1279 1280static bool azx_vs_can_switch(struct pci_dev *pci) 1281{ 1282 struct snd_card *card = pci_get_drvdata(pci); 1283 struct azx *chip = card->private_data; 1284 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1285 1286 wait_for_completion(&hda->probe_wait); 1287 if (hda->init_failed) 1288 return false; 1289 if (chip->disabled || !hda->probe_continued) 1290 return true; 1291 if (snd_hda_lock_devices(&chip->bus)) 1292 return false; 1293 snd_hda_unlock_devices(&chip->bus); 1294 return true; 1295} 1296 1297/* 1298 * The discrete GPU cannot power down unless the HDA controller runtime 1299 * suspends, so activate runtime PM on codecs even if power_save == 0. 1300 */ 1301static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1302{ 1303 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1304 struct hda_codec *codec; 1305 1306 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1307 list_for_each_codec(codec, &chip->bus) 1308 codec->auto_runtime_pm = 1; 1309 /* reset the power save setup */ 1310 if (chip->running) 1311 set_default_power_save(chip); 1312 } 1313} 1314 1315static void azx_vs_gpu_bound(struct pci_dev *pci, 1316 enum vga_switcheroo_client_id client_id) 1317{ 1318 struct snd_card *card = pci_get_drvdata(pci); 1319 struct azx *chip = card->private_data; 1320 1321 if (client_id == VGA_SWITCHEROO_DIS) 1322 chip->bus.keep_power = 0; 1323 setup_vga_switcheroo_runtime_pm(chip); 1324} 1325 1326static void init_vga_switcheroo(struct azx *chip) 1327{ 1328 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1329 struct pci_dev *p = get_bound_vga(chip->pci); 1330 struct pci_dev *parent; 1331 if (p) { 1332 dev_info(chip->card->dev, 1333 "Handle vga_switcheroo audio client\n"); 1334 hda->use_vga_switcheroo = 1; 1335 1336 /* cleared in either gpu_bound op or codec probe, or when its 1337 * upstream port has _PR3 (i.e. dGPU). 1338 */ 1339 parent = pci_upstream_bridge(p); 1340 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1341 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1342 pci_dev_put(p); 1343 } 1344} 1345 1346static const struct vga_switcheroo_client_ops azx_vs_ops = { 1347 .set_gpu_state = azx_vs_set_state, 1348 .can_switch = azx_vs_can_switch, 1349 .gpu_bound = azx_vs_gpu_bound, 1350}; 1351 1352static int register_vga_switcheroo(struct azx *chip) 1353{ 1354 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1355 struct pci_dev *p; 1356 int err; 1357 1358 if (!hda->use_vga_switcheroo) 1359 return 0; 1360 1361 p = get_bound_vga(chip->pci); 1362 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1363 pci_dev_put(p); 1364 1365 if (err < 0) 1366 return err; 1367 hda->vga_switcheroo_registered = 1; 1368 1369 return 0; 1370} 1371#else 1372#define init_vga_switcheroo(chip) /* NOP */ 1373#define register_vga_switcheroo(chip) 0 1374#define check_hdmi_disabled(pci) false 1375#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1376#endif /* SUPPORT_VGA_SWITCHER */ 1377 1378/* 1379 * destructor 1380 */ 1381static void azx_free(struct azx *chip) 1382{ 1383 struct pci_dev *pci = chip->pci; 1384 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1385 struct hdac_bus *bus = azx_bus(chip); 1386 1387 if (hda->freed) 1388 return; 1389 1390 if (azx_has_pm_runtime(chip) && chip->running) 1391 pm_runtime_get_noresume(&pci->dev); 1392 chip->running = 0; 1393 1394 azx_del_card_list(chip); 1395 1396 hda->init_failed = 1; /* to be sure */ 1397 complete_all(&hda->probe_wait); 1398 1399 if (use_vga_switcheroo(hda)) { 1400 if (chip->disabled && hda->probe_continued) 1401 snd_hda_unlock_devices(&chip->bus); 1402 if (hda->vga_switcheroo_registered) 1403 vga_switcheroo_unregister_client(chip->pci); 1404 } 1405 1406 if (bus->chip_init) { 1407 azx_clear_irq_pending(chip); 1408 azx_stop_all_streams(chip); 1409 azx_stop_chip(chip); 1410 } 1411 1412 if (bus->irq >= 0) 1413 free_irq(bus->irq, (void*)chip); 1414 if (chip->msi) 1415 pci_disable_msi(chip->pci); 1416 iounmap(bus->remap_addr); 1417 1418 azx_free_stream_pages(chip); 1419 azx_free_streams(chip); 1420 snd_hdac_bus_exit(bus); 1421 1422 if (chip->region_requested) 1423 pci_release_regions(chip->pci); 1424 1425 pci_disable_device(chip->pci); 1426#ifdef CONFIG_SND_HDA_PATCH_LOADER 1427 release_firmware(chip->fw); 1428#endif 1429 display_power(chip, false); 1430 1431 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1432 snd_hdac_i915_exit(bus); 1433 1434 hda->freed = 1; 1435} 1436 1437static int azx_dev_disconnect(struct snd_device *device) 1438{ 1439 struct azx *chip = device->device_data; 1440 struct hdac_bus *bus = azx_bus(chip); 1441 1442 chip->bus.shutdown = 1; 1443 cancel_work_sync(&bus->unsol_work); 1444 1445 return 0; 1446} 1447 1448static int azx_dev_free(struct snd_device *device) 1449{ 1450 azx_free(device->device_data); 1451 return 0; 1452} 1453 1454#ifdef SUPPORT_VGA_SWITCHEROO 1455#ifdef CONFIG_ACPI 1456/* ATPX is in the integrated GPU's namespace */ 1457static bool atpx_present(void) 1458{ 1459 struct pci_dev *pdev = NULL; 1460 acpi_handle dhandle, atpx_handle; 1461 acpi_status status; 1462 1463 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1464 dhandle = ACPI_HANDLE(&pdev->dev); 1465 if (dhandle) { 1466 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1467 if (!ACPI_FAILURE(status)) { 1468 pci_dev_put(pdev); 1469 return true; 1470 } 1471 } 1472 } 1473 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1474 dhandle = ACPI_HANDLE(&pdev->dev); 1475 if (dhandle) { 1476 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1477 if (!ACPI_FAILURE(status)) { 1478 pci_dev_put(pdev); 1479 return true; 1480 } 1481 } 1482 } 1483 return false; 1484} 1485#else 1486static bool atpx_present(void) 1487{ 1488 return false; 1489} 1490#endif 1491 1492/* 1493 * Check of disabled HDMI controller by vga_switcheroo 1494 */ 1495static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1496{ 1497 struct pci_dev *p; 1498 1499 /* check only discrete GPU */ 1500 switch (pci->vendor) { 1501 case PCI_VENDOR_ID_ATI: 1502 case PCI_VENDOR_ID_AMD: 1503 if (pci->devfn == 1) { 1504 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1505 pci->bus->number, 0); 1506 if (p) { 1507 /* ATPX is in the integrated GPU's ACPI namespace 1508 * rather than the dGPU's namespace. However, 1509 * the dGPU is the one who is involved in 1510 * vgaswitcheroo. 1511 */ 1512 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1513 atpx_present()) 1514 return p; 1515 pci_dev_put(p); 1516 } 1517 } 1518 break; 1519 case PCI_VENDOR_ID_NVIDIA: 1520 if (pci->devfn == 1) { 1521 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1522 pci->bus->number, 0); 1523 if (p) { 1524 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1525 return p; 1526 pci_dev_put(p); 1527 } 1528 } 1529 break; 1530 } 1531 return NULL; 1532} 1533 1534static bool check_hdmi_disabled(struct pci_dev *pci) 1535{ 1536 bool vga_inactive = false; 1537 struct pci_dev *p = get_bound_vga(pci); 1538 1539 if (p) { 1540 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1541 vga_inactive = true; 1542 pci_dev_put(p); 1543 } 1544 return vga_inactive; 1545} 1546#endif /* SUPPORT_VGA_SWITCHEROO */ 1547 1548/* 1549 * allow/deny-listing for position_fix 1550 */ 1551static const struct snd_pci_quirk position_fix_list[] = { 1552 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1553 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1554 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1555 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1556 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1557 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1558 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1559 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1560 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1561 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1562 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1563 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1564 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1565 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1566 {} 1567}; 1568 1569static int check_position_fix(struct azx *chip, int fix) 1570{ 1571 const struct snd_pci_quirk *q; 1572 1573 switch (fix) { 1574 case POS_FIX_AUTO: 1575 case POS_FIX_LPIB: 1576 case POS_FIX_POSBUF: 1577 case POS_FIX_VIACOMBO: 1578 case POS_FIX_COMBO: 1579 case POS_FIX_SKL: 1580 case POS_FIX_FIFO: 1581 return fix; 1582 } 1583 1584 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1585 if (q) { 1586 dev_info(chip->card->dev, 1587 "position_fix set to %d for device %04x:%04x\n", 1588 q->value, q->subvendor, q->subdevice); 1589 return q->value; 1590 } 1591 1592 /* Check VIA/ATI HD Audio Controller exist */ 1593 if (chip->driver_type == AZX_DRIVER_VIA) { 1594 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1595 return POS_FIX_VIACOMBO; 1596 } 1597 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1598 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1599 return POS_FIX_FIFO; 1600 } 1601 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1602 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1603 return POS_FIX_LPIB; 1604 } 1605 if (chip->driver_type == AZX_DRIVER_SKL) { 1606 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1607 return POS_FIX_SKL; 1608 } 1609 return POS_FIX_AUTO; 1610} 1611 1612static void assign_position_fix(struct azx *chip, int fix) 1613{ 1614 static const azx_get_pos_callback_t callbacks[] = { 1615 [POS_FIX_AUTO] = NULL, 1616 [POS_FIX_LPIB] = azx_get_pos_lpib, 1617 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1618 [POS_FIX_VIACOMBO] = azx_via_get_position, 1619 [POS_FIX_COMBO] = azx_get_pos_lpib, 1620 [POS_FIX_SKL] = azx_get_pos_posbuf, 1621 [POS_FIX_FIFO] = azx_get_pos_fifo, 1622 }; 1623 1624 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1625 1626 /* combo mode uses LPIB only for playback */ 1627 if (fix == POS_FIX_COMBO) 1628 chip->get_position[1] = NULL; 1629 1630 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1631 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1632 chip->get_delay[0] = chip->get_delay[1] = 1633 azx_get_delay_from_lpib; 1634 } 1635 1636 if (fix == POS_FIX_FIFO) 1637 chip->get_delay[0] = chip->get_delay[1] = 1638 azx_get_delay_from_fifo; 1639} 1640 1641/* 1642 * deny-lists for probe_mask 1643 */ 1644static const struct snd_pci_quirk probe_mask_list[] = { 1645 /* Thinkpad often breaks the controller communication when accessing 1646 * to the non-working (or non-existing) modem codec slot. 1647 */ 1648 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1649 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1650 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1651 /* broken BIOS */ 1652 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1653 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1654 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1655 /* forced codec slots */ 1656 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1657 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1658 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1659 /* WinFast VP200 H (Teradici) user reported broken communication */ 1660 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1661 {} 1662}; 1663 1664#define AZX_FORCE_CODEC_MASK 0x100 1665 1666static void check_probe_mask(struct azx *chip, int dev) 1667{ 1668 const struct snd_pci_quirk *q; 1669 1670 chip->codec_probe_mask = probe_mask[dev]; 1671 if (chip->codec_probe_mask == -1) { 1672 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1673 if (q) { 1674 dev_info(chip->card->dev, 1675 "probe_mask set to 0x%x for device %04x:%04x\n", 1676 q->value, q->subvendor, q->subdevice); 1677 chip->codec_probe_mask = q->value; 1678 } 1679 } 1680 1681 /* check forced option */ 1682 if (chip->codec_probe_mask != -1 && 1683 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1684 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1685 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1686 (int)azx_bus(chip)->codec_mask); 1687 } 1688} 1689 1690/* 1691 * allow/deny-list for enable_msi 1692 */ 1693static const struct snd_pci_quirk msi_deny_list[] = { 1694 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1695 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1696 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1697 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1698 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1699 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1700 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1701 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1702 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1703 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1704 {} 1705}; 1706 1707static void check_msi(struct azx *chip) 1708{ 1709 const struct snd_pci_quirk *q; 1710 1711 if (enable_msi >= 0) { 1712 chip->msi = !!enable_msi; 1713 return; 1714 } 1715 chip->msi = 1; /* enable MSI as default */ 1716 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1717 if (q) { 1718 dev_info(chip->card->dev, 1719 "msi for device %04x:%04x set to %d\n", 1720 q->subvendor, q->subdevice, q->value); 1721 chip->msi = q->value; 1722 return; 1723 } 1724 1725 /* NVidia chipsets seem to cause troubles with MSI */ 1726 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1727 dev_info(chip->card->dev, "Disabling MSI\n"); 1728 chip->msi = 0; 1729 } 1730} 1731 1732/* check the snoop mode availability */ 1733static void azx_check_snoop_available(struct azx *chip) 1734{ 1735 int snoop = hda_snoop; 1736 1737 if (snoop >= 0) { 1738 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1739 snoop ? "snoop" : "non-snoop"); 1740 chip->snoop = snoop; 1741 chip->uc_buffer = !snoop; 1742 return; 1743 } 1744 1745 snoop = true; 1746 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1747 chip->driver_type == AZX_DRIVER_VIA) { 1748 /* force to non-snoop mode for a new VIA controller 1749 * when BIOS is set 1750 */ 1751 u8 val; 1752 pci_read_config_byte(chip->pci, 0x42, &val); 1753 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1754 chip->pci->revision == 0x20)) 1755 snoop = false; 1756 } 1757 1758 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1759 snoop = false; 1760 1761 chip->snoop = snoop; 1762 if (!snoop) { 1763 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1764 /* C-Media requires non-cached pages only for CORB/RIRB */ 1765 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1766 chip->uc_buffer = true; 1767 } 1768} 1769 1770static void azx_probe_work(struct work_struct *work) 1771{ 1772 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1773 azx_probe_continue(&hda->chip); 1774} 1775 1776static int default_bdl_pos_adj(struct azx *chip) 1777{ 1778 /* some exceptions: Atoms seem problematic with value 1 */ 1779 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1780 switch (chip->pci->device) { 1781 case 0x0f04: /* Baytrail */ 1782 case 0x2284: /* Braswell */ 1783 return 32; 1784 } 1785 } 1786 1787 switch (chip->driver_type) { 1788 /* 1789 * increase the bdl size for Glenfly Gpus for hardware 1790 * limitation on hdac interrupt interval 1791 */ 1792 case AZX_DRIVER_GFHDMI: 1793 return 128; 1794 case AZX_DRIVER_ICH: 1795 case AZX_DRIVER_PCH: 1796 return 1; 1797 default: 1798 return 32; 1799 } 1800} 1801 1802/* 1803 * constructor 1804 */ 1805static const struct hda_controller_ops pci_hda_ops; 1806 1807static int azx_create(struct snd_card *card, struct pci_dev *pci, 1808 int dev, unsigned int driver_caps, 1809 struct azx **rchip) 1810{ 1811 static const struct snd_device_ops ops = { 1812 .dev_disconnect = azx_dev_disconnect, 1813 .dev_free = azx_dev_free, 1814 }; 1815 struct hda_intel *hda; 1816 struct azx *chip; 1817 int err; 1818 1819 *rchip = NULL; 1820 1821 err = pci_enable_device(pci); 1822 if (err < 0) 1823 return err; 1824 1825 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1826 if (!hda) { 1827 pci_disable_device(pci); 1828 return -ENOMEM; 1829 } 1830 1831 chip = &hda->chip; 1832 mutex_init(&chip->open_mutex); 1833 chip->card = card; 1834 chip->pci = pci; 1835 chip->ops = &pci_hda_ops; 1836 chip->driver_caps = driver_caps; 1837 chip->driver_type = driver_caps & 0xff; 1838 check_msi(chip); 1839 chip->dev_index = dev; 1840 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1841 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1842 INIT_LIST_HEAD(&chip->pcm_list); 1843 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1844 INIT_LIST_HEAD(&hda->list); 1845 init_vga_switcheroo(chip); 1846 init_completion(&hda->probe_wait); 1847 1848 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1849 1850 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1851 chip->fallback_to_single_cmd = 1; 1852 else /* explicitly set to single_cmd or not */ 1853 chip->single_cmd = single_cmd; 1854 1855 azx_check_snoop_available(chip); 1856 1857 if (bdl_pos_adj[dev] < 0) 1858 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1859 else 1860 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1861 1862 err = azx_bus_init(chip, model[dev]); 1863 if (err < 0) { 1864 pci_disable_device(pci); 1865 return err; 1866 } 1867 1868 /* use the non-cached pages in non-snoop mode */ 1869 if (!azx_snoop(chip)) 1870 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1871 1872 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1873 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1874 chip->bus.core.needs_damn_long_delay = 1; 1875 } 1876 1877 check_probe_mask(chip, dev); 1878 1879 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1880 if (err < 0) { 1881 dev_err(card->dev, "Error creating device [card]!\n"); 1882 azx_free(chip); 1883 return err; 1884 } 1885 1886 /* continue probing in work context as may trigger request module */ 1887 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1888 1889 *rchip = chip; 1890 1891 return 0; 1892} 1893 1894static int azx_first_init(struct azx *chip) 1895{ 1896 int dev = chip->dev_index; 1897 struct pci_dev *pci = chip->pci; 1898 struct snd_card *card = chip->card; 1899 struct hdac_bus *bus = azx_bus(chip); 1900 int err; 1901 unsigned short gcap; 1902 unsigned int dma_bits = 64; 1903 1904#if BITS_PER_LONG != 64 1905 /* Fix up base address on ULI M5461 */ 1906 if (chip->driver_type == AZX_DRIVER_ULI) { 1907 u16 tmp3; 1908 pci_read_config_word(pci, 0x40, &tmp3); 1909 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1910 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1911 } 1912#endif 1913 /* 1914 * Fix response write request not synced to memory when handle 1915 * hdac interrupt on Glenfly Gpus 1916 */ 1917 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1918 bus->polling_mode = 1; 1919 1920 err = pci_request_regions(pci, "ICH HD audio"); 1921 if (err < 0) 1922 return err; 1923 chip->region_requested = 1; 1924 1925 bus->addr = pci_resource_start(pci, 0); 1926 bus->remap_addr = pci_ioremap_bar(pci, 0); 1927 if (bus->remap_addr == NULL) { 1928 dev_err(card->dev, "ioremap error\n"); 1929 return -ENXIO; 1930 } 1931 1932 if (chip->driver_type == AZX_DRIVER_SKL) 1933 snd_hdac_bus_parse_capabilities(bus); 1934 1935 /* 1936 * Some Intel CPUs has always running timer (ART) feature and 1937 * controller may have Global time sync reporting capability, so 1938 * check both of these before declaring synchronized time reporting 1939 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1940 */ 1941 chip->gts_present = false; 1942 1943#ifdef CONFIG_X86 1944 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1945 chip->gts_present = true; 1946#endif 1947 1948 if (chip->msi) { 1949 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1950 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1951 pci->no_64bit_msi = true; 1952 } 1953 if (pci_enable_msi(pci) < 0) 1954 chip->msi = 0; 1955 } 1956 1957 pci_set_master(pci); 1958 1959 gcap = azx_readw(chip, GCAP); 1960 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1961 1962 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1963 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1964 dma_bits = 40; 1965 1966 /* disable SB600 64bit support for safety */ 1967 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1968 struct pci_dev *p_smbus; 1969 dma_bits = 40; 1970 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1971 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1972 NULL); 1973 if (p_smbus) { 1974 if (p_smbus->revision < 0x30) 1975 gcap &= ~AZX_GCAP_64OK; 1976 pci_dev_put(p_smbus); 1977 } 1978 } 1979 1980 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1981 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1982 dma_bits = 40; 1983 1984 /* disable 64bit DMA address on some devices */ 1985 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1986 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1987 gcap &= ~AZX_GCAP_64OK; 1988 } 1989 1990 /* disable buffer size rounding to 128-byte multiples if supported */ 1991 if (align_buffer_size >= 0) 1992 chip->align_buffer_size = !!align_buffer_size; 1993 else { 1994 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1995 chip->align_buffer_size = 0; 1996 else 1997 chip->align_buffer_size = 1; 1998 } 1999 2000 /* allow 64bit DMA address if supported by H/W */ 2001 if (!(gcap & AZX_GCAP_64OK)) 2002 dma_bits = 32; 2003 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 2004 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 2005 } else { 2006 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 2007 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 2008 } 2009 2010 /* read number of streams from GCAP register instead of using 2011 * hardcoded value 2012 */ 2013 chip->capture_streams = (gcap >> 8) & 0x0f; 2014 chip->playback_streams = (gcap >> 12) & 0x0f; 2015 if (!chip->playback_streams && !chip->capture_streams) { 2016 /* gcap didn't give any info, switching to old method */ 2017 2018 switch (chip->driver_type) { 2019 case AZX_DRIVER_ULI: 2020 chip->playback_streams = ULI_NUM_PLAYBACK; 2021 chip->capture_streams = ULI_NUM_CAPTURE; 2022 break; 2023 case AZX_DRIVER_ATIHDMI: 2024 case AZX_DRIVER_ATIHDMI_NS: 2025 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 2026 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 2027 break; 2028 case AZX_DRIVER_GFHDMI: 2029 case AZX_DRIVER_GENERIC: 2030 default: 2031 chip->playback_streams = ICH6_NUM_PLAYBACK; 2032 chip->capture_streams = ICH6_NUM_CAPTURE; 2033 break; 2034 } 2035 } 2036 chip->capture_index_offset = 0; 2037 chip->playback_index_offset = chip->capture_streams; 2038 chip->num_streams = chip->playback_streams + chip->capture_streams; 2039 2040 /* sanity check for the SDxCTL.STRM field overflow */ 2041 if (chip->num_streams > 15 && 2042 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 2043 dev_warn(chip->card->dev, "number of I/O streams is %d, " 2044 "forcing separate stream tags", chip->num_streams); 2045 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 2046 } 2047 2048 /* initialize streams */ 2049 err = azx_init_streams(chip); 2050 if (err < 0) 2051 return err; 2052 2053 err = azx_alloc_stream_pages(chip); 2054 if (err < 0) 2055 return err; 2056 2057 /* initialize chip */ 2058 azx_init_pci(chip); 2059 2060 snd_hdac_i915_set_bclk(bus); 2061 2062 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2063 2064 /* codec detection */ 2065 if (!azx_bus(chip)->codec_mask) { 2066 dev_err(card->dev, "no codecs found!\n"); 2067 /* keep running the rest for the runtime PM */ 2068 } 2069 2070 if (azx_acquire_irq(chip, 0) < 0) 2071 return -EBUSY; 2072 2073 strcpy(card->driver, "HDA-Intel"); 2074 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2075 sizeof(card->shortname)); 2076 snprintf(card->longname, sizeof(card->longname), 2077 "%s at 0x%lx irq %i", 2078 card->shortname, bus->addr, bus->irq); 2079 2080 return 0; 2081} 2082 2083#ifdef CONFIG_SND_HDA_PATCH_LOADER 2084/* callback from request_firmware_nowait() */ 2085static void azx_firmware_cb(const struct firmware *fw, void *context) 2086{ 2087 struct snd_card *card = context; 2088 struct azx *chip = card->private_data; 2089 2090 if (fw) 2091 chip->fw = fw; 2092 else 2093 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2094 if (!chip->disabled) { 2095 /* continue probing */ 2096 azx_probe_continue(chip); 2097 } 2098} 2099#endif 2100 2101static int disable_msi_reset_irq(struct azx *chip) 2102{ 2103 struct hdac_bus *bus = azx_bus(chip); 2104 int err; 2105 2106 free_irq(bus->irq, chip); 2107 bus->irq = -1; 2108 chip->card->sync_irq = -1; 2109 pci_disable_msi(chip->pci); 2110 chip->msi = 0; 2111 err = azx_acquire_irq(chip, 1); 2112 if (err < 0) 2113 return err; 2114 2115 return 0; 2116} 2117 2118static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2119 struct vm_area_struct *area) 2120{ 2121#ifdef CONFIG_X86 2122 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2123 struct azx *chip = apcm->chip; 2124 if (chip->uc_buffer) 2125 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2126#endif 2127} 2128 2129/* Denylist for skipping the whole probe: 2130 * some HD-audio PCI entries are exposed without any codecs, and such devices 2131 * should be ignored from the beginning. 2132 */ 2133static const struct pci_device_id driver_denylist[] = { 2134 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2135 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2136 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2137 {} 2138}; 2139 2140static const struct hda_controller_ops pci_hda_ops = { 2141 .disable_msi_reset_irq = disable_msi_reset_irq, 2142 .pcm_mmap_prepare = pcm_mmap_prepare, 2143 .position_check = azx_position_check, 2144}; 2145 2146static int azx_probe(struct pci_dev *pci, 2147 const struct pci_device_id *pci_id) 2148{ 2149 static int dev; 2150 struct snd_card *card; 2151 struct hda_intel *hda; 2152 struct azx *chip; 2153 bool schedule_probe; 2154 int err; 2155 2156 if (pci_match_id(driver_denylist, pci)) { 2157 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2158 return -ENODEV; 2159 } 2160 2161 if (dev >= SNDRV_CARDS) 2162 return -ENODEV; 2163 if (!enable[dev]) { 2164 dev++; 2165 return -ENOENT; 2166 } 2167 2168 /* 2169 * stop probe if another Intel's DSP driver should be activated 2170 */ 2171 if (dmic_detect) { 2172 err = snd_intel_dsp_driver_probe(pci); 2173 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2174 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2175 return -ENODEV; 2176 } 2177 } else { 2178 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2179 } 2180 2181 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2182 0, &card); 2183 if (err < 0) { 2184 dev_err(&pci->dev, "Error creating card!\n"); 2185 return err; 2186 } 2187 2188 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2189 if (err < 0) 2190 goto out_free; 2191 card->private_data = chip; 2192 hda = container_of(chip, struct hda_intel, chip); 2193 2194 pci_set_drvdata(pci, card); 2195 2196 err = register_vga_switcheroo(chip); 2197 if (err < 0) { 2198 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2199 goto out_free; 2200 } 2201 2202 if (check_hdmi_disabled(pci)) { 2203 dev_info(card->dev, "VGA controller is disabled\n"); 2204 dev_info(card->dev, "Delaying initialization\n"); 2205 chip->disabled = true; 2206 } 2207 2208 schedule_probe = !chip->disabled; 2209 2210#ifdef CONFIG_SND_HDA_PATCH_LOADER 2211 if (patch[dev] && *patch[dev]) { 2212 dev_info(card->dev, "Applying patch firmware '%s'\n", 2213 patch[dev]); 2214 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2215 &pci->dev, GFP_KERNEL, card, 2216 azx_firmware_cb); 2217 if (err < 0) 2218 goto out_free; 2219 schedule_probe = false; /* continued in azx_firmware_cb() */ 2220 } 2221#endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2222 2223#ifndef CONFIG_SND_HDA_I915 2224 if (CONTROLLER_IN_GPU(pci)) 2225 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2226#endif 2227 2228 if (schedule_probe) 2229 schedule_delayed_work(&hda->probe_work, 0); 2230 2231 dev++; 2232 if (chip->disabled) 2233 complete_all(&hda->probe_wait); 2234 return 0; 2235 2236out_free: 2237 snd_card_free(card); 2238 return err; 2239} 2240 2241#ifdef CONFIG_PM 2242/* On some boards setting power_save to a non 0 value leads to clicking / 2243 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2244 * figure out how to avoid these sounds, but that is not always feasible. 2245 * So we keep a list of devices where we disable powersaving as its known 2246 * to causes problems on these devices. 2247 */ 2248static const struct snd_pci_quirk power_save_denylist[] = { 2249 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2250 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2251 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2252 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2253 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2254 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2255 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2256 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2257 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2258 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0), 2259 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2260 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2261 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2262 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2263 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2264 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2265 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2266 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2267 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2268 /* https://bugs.launchpad.net/bugs/1821663 */ 2269 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2270 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2271 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2272 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2273 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2274 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), 2275 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2276 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2277 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2278 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2279 /* https://bugs.launchpad.net/bugs/1821663 */ 2280 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2281 /* KONTRON SinglePC may cause a stall at runtime resume */ 2282 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0), 2283 {} 2284}; 2285#endif /* CONFIG_PM */ 2286 2287static void set_default_power_save(struct azx *chip) 2288{ 2289 int val = power_save; 2290 2291#ifdef CONFIG_PM 2292 if (pm_blacklist) { 2293 const struct snd_pci_quirk *q; 2294 2295 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2296 if (q && val) { 2297 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2298 q->subvendor, q->subdevice); 2299 val = 0; 2300 } 2301 } 2302#endif /* CONFIG_PM */ 2303 snd_hda_set_power_save(&chip->bus, val * 1000); 2304} 2305 2306/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2307static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2308 [AZX_DRIVER_NVIDIA] = 8, 2309 [AZX_DRIVER_TERA] = 1, 2310}; 2311 2312static int azx_probe_continue(struct azx *chip) 2313{ 2314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2315 struct hdac_bus *bus = azx_bus(chip); 2316 struct pci_dev *pci = chip->pci; 2317 int dev = chip->dev_index; 2318 int err; 2319 2320 if (chip->disabled || hda->init_failed) 2321 return -EIO; 2322 if (hda->probe_retry) 2323 goto probe_retry; 2324 2325 to_hda_bus(bus)->bus_probing = 1; 2326 hda->probe_continued = 1; 2327 2328 /* bind with i915 if needed */ 2329 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2330 err = snd_hdac_i915_init(bus); 2331 if (err < 0) { 2332 /* if the controller is bound only with HDMI/DP 2333 * (for HSW and BDW), we need to abort the probe; 2334 * for other chips, still continue probing as other 2335 * codecs can be on the same link. 2336 */ 2337 if (CONTROLLER_IN_GPU(pci)) { 2338 dev_err(chip->card->dev, 2339 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2340 goto out_free; 2341 } else { 2342 /* don't bother any longer */ 2343 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2344 } 2345 } 2346 2347 /* HSW/BDW controllers need this power */ 2348 if (CONTROLLER_IN_GPU(pci)) 2349 hda->need_i915_power = 1; 2350 } 2351 2352 /* Request display power well for the HDA controller or codec. For 2353 * Haswell/Broadwell, both the display HDA controller and codec need 2354 * this power. For other platforms, like Baytrail/Braswell, only the 2355 * display codec needs the power and it can be released after probe. 2356 */ 2357 display_power(chip, true); 2358 2359 err = azx_first_init(chip); 2360 if (err < 0) 2361 goto out_free; 2362 2363#ifdef CONFIG_SND_HDA_INPUT_BEEP 2364 chip->beep_mode = beep_mode[dev]; 2365#endif 2366 2367 /* create codec instances */ 2368 if (bus->codec_mask) { 2369 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2370 if (err < 0) 2371 goto out_free; 2372 } 2373 2374#ifdef CONFIG_SND_HDA_PATCH_LOADER 2375 if (chip->fw) { 2376 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2377 chip->fw->data); 2378 if (err < 0) 2379 goto out_free; 2380#ifndef CONFIG_PM 2381 release_firmware(chip->fw); /* no longer needed */ 2382 chip->fw = NULL; 2383#endif 2384 } 2385#endif 2386 2387 probe_retry: 2388 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2389 err = azx_codec_configure(chip); 2390 if (err) { 2391 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2392 ++hda->probe_retry < 60) { 2393 schedule_delayed_work(&hda->probe_work, 2394 msecs_to_jiffies(1000)); 2395 return 0; /* keep things up */ 2396 } 2397 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2398 goto out_free; 2399 } 2400 } 2401 2402 err = snd_card_register(chip->card); 2403 if (err < 0) 2404 goto out_free; 2405 2406 setup_vga_switcheroo_runtime_pm(chip); 2407 2408 chip->running = 1; 2409 azx_add_card_list(chip); 2410 2411 set_default_power_save(chip); 2412 2413 if (azx_has_pm_runtime(chip)) { 2414 pm_runtime_use_autosuspend(&pci->dev); 2415 pm_runtime_allow(&pci->dev); 2416 pm_runtime_put_autosuspend(&pci->dev); 2417 } 2418 2419out_free: 2420 if (err < 0) { 2421 pci_set_drvdata(pci, NULL); 2422 snd_card_free(chip->card); 2423 return err; 2424 } 2425 2426 if (!hda->need_i915_power) 2427 display_power(chip, false); 2428 complete_all(&hda->probe_wait); 2429 to_hda_bus(bus)->bus_probing = 0; 2430 hda->probe_retry = 0; 2431 return 0; 2432} 2433 2434static void azx_remove(struct pci_dev *pci) 2435{ 2436 struct snd_card *card = pci_get_drvdata(pci); 2437 struct azx *chip; 2438 struct hda_intel *hda; 2439 2440 if (card) { 2441 /* cancel the pending probing work */ 2442 chip = card->private_data; 2443 hda = container_of(chip, struct hda_intel, chip); 2444 /* FIXME: below is an ugly workaround. 2445 * Both device_release_driver() and driver_probe_device() 2446 * take *both* the device's and its parent's lock before 2447 * calling the remove() and probe() callbacks. The codec 2448 * probe takes the locks of both the codec itself and its 2449 * parent, i.e. the PCI controller dev. Meanwhile, when 2450 * the PCI controller is unbound, it takes its lock, too 2451 * ==> ouch, a deadlock! 2452 * As a workaround, we unlock temporarily here the controller 2453 * device during cancel_work_sync() call. 2454 */ 2455 device_unlock(&pci->dev); 2456 cancel_delayed_work_sync(&hda->probe_work); 2457 device_lock(&pci->dev); 2458 2459 snd_card_free(card); 2460 } 2461} 2462 2463static void azx_shutdown(struct pci_dev *pci) 2464{ 2465 struct snd_card *card = pci_get_drvdata(pci); 2466 struct azx *chip; 2467 2468 if (!card) 2469 return; 2470 chip = card->private_data; 2471 if (chip && chip->running) 2472 __azx_shutdown_chip(chip, true); 2473} 2474 2475/* PCI IDs */ 2476static const struct pci_device_id azx_ids[] = { 2477 /* CPT */ 2478 { PCI_DEVICE(0x8086, 0x1c20), 2479 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2480 /* PBG */ 2481 { PCI_DEVICE(0x8086, 0x1d20), 2482 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2483 /* Panther Point */ 2484 { PCI_DEVICE(0x8086, 0x1e20), 2485 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2486 /* Lynx Point */ 2487 { PCI_DEVICE(0x8086, 0x8c20), 2488 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2489 /* 9 Series */ 2490 { PCI_DEVICE(0x8086, 0x8ca0), 2491 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2492 /* Wellsburg */ 2493 { PCI_DEVICE(0x8086, 0x8d20), 2494 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2495 { PCI_DEVICE(0x8086, 0x8d21), 2496 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2497 /* Lewisburg */ 2498 { PCI_DEVICE(0x8086, 0xa1f0), 2499 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2500 { PCI_DEVICE(0x8086, 0xa270), 2501 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2502 /* Lynx Point-LP */ 2503 { PCI_DEVICE(0x8086, 0x9c20), 2504 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2505 /* Lynx Point-LP */ 2506 { PCI_DEVICE(0x8086, 0x9c21), 2507 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2508 /* Wildcat Point-LP */ 2509 { PCI_DEVICE(0x8086, 0x9ca0), 2510 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2511 /* Sunrise Point */ 2512 { PCI_DEVICE(0x8086, 0xa170), 2513 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2514 /* Sunrise Point-LP */ 2515 { PCI_DEVICE(0x8086, 0x9d70), 2516 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2517 /* Kabylake */ 2518 { PCI_DEVICE(0x8086, 0xa171), 2519 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2520 /* Kabylake-LP */ 2521 { PCI_DEVICE(0x8086, 0x9d71), 2522 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2523 /* Kabylake-H */ 2524 { PCI_DEVICE(0x8086, 0xa2f0), 2525 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2526 /* Coffelake */ 2527 { PCI_DEVICE(0x8086, 0xa348), 2528 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2529 /* Cannonlake */ 2530 { PCI_DEVICE(0x8086, 0x9dc8), 2531 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2532 /* CometLake-LP */ 2533 { PCI_DEVICE(0x8086, 0x02C8), 2534 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2535 /* CometLake-H */ 2536 { PCI_DEVICE(0x8086, 0x06C8), 2537 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2538 { PCI_DEVICE(0x8086, 0xf1c8), 2539 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2540 /* CometLake-S */ 2541 { PCI_DEVICE(0x8086, 0xa3f0), 2542 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2543 /* CometLake-R */ 2544 { PCI_DEVICE(0x8086, 0xf0c8), 2545 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2546 /* Icelake */ 2547 { PCI_DEVICE(0x8086, 0x34c8), 2548 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2549 /* Icelake-H */ 2550 { PCI_DEVICE(0x8086, 0x3dc8), 2551 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2552 /* Jasperlake */ 2553 { PCI_DEVICE(0x8086, 0x38c8), 2554 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2555 { PCI_DEVICE(0x8086, 0x4dc8), 2556 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2557 /* Tigerlake */ 2558 { PCI_DEVICE(0x8086, 0xa0c8), 2559 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2560 /* Tigerlake-H */ 2561 { PCI_DEVICE(0x8086, 0x43c8), 2562 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2563 /* DG1 */ 2564 { PCI_DEVICE(0x8086, 0x490d), 2565 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2566 /* DG2 */ 2567 { PCI_DEVICE(0x8086, 0x4f90), 2568 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2569 { PCI_DEVICE(0x8086, 0x4f91), 2570 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2571 { PCI_DEVICE(0x8086, 0x4f92), 2572 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2573 /* Alderlake-S */ 2574 { PCI_DEVICE(0x8086, 0x7ad0), 2575 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2576 /* Alderlake-P */ 2577 { PCI_DEVICE(0x8086, 0x51c8), 2578 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2579 /* Elkhart Lake */ 2580 { PCI_DEVICE(0x8086, 0x4b55), 2581 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2582 { PCI_DEVICE(0x8086, 0x4b58), 2583 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2584 /* Arrow Lake */ 2585 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2586 /* Broxton-P(Apollolake) */ 2587 { PCI_DEVICE(0x8086, 0x5a98), 2588 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2589 /* Broxton-T */ 2590 { PCI_DEVICE(0x8086, 0x1a98), 2591 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2592 /* Gemini-Lake */ 2593 { PCI_DEVICE(0x8086, 0x3198), 2594 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2595 /* Haswell */ 2596 { PCI_DEVICE(0x8086, 0x0a0c), 2597 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2598 { PCI_DEVICE(0x8086, 0x0c0c), 2599 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2600 { PCI_DEVICE(0x8086, 0x0d0c), 2601 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2602 /* Broadwell */ 2603 { PCI_DEVICE(0x8086, 0x160c), 2604 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2605 /* 5 Series/3400 */ 2606 { PCI_DEVICE(0x8086, 0x3b56), 2607 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2608 { PCI_DEVICE(0x8086, 0x3b57), 2609 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2610 /* Poulsbo */ 2611 { PCI_DEVICE(0x8086, 0x811b), 2612 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2613 AZX_DCAPS_POSFIX_LPIB }, 2614 /* Oaktrail */ 2615 { PCI_DEVICE(0x8086, 0x080a), 2616 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2617 /* BayTrail */ 2618 { PCI_DEVICE(0x8086, 0x0f04), 2619 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2620 /* Braswell */ 2621 { PCI_DEVICE(0x8086, 0x2284), 2622 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2623 /* ICH6 */ 2624 { PCI_DEVICE(0x8086, 0x2668), 2625 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2626 /* ICH7 */ 2627 { PCI_DEVICE(0x8086, 0x27d8), 2628 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2629 /* ESB2 */ 2630 { PCI_DEVICE(0x8086, 0x269a), 2631 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2632 /* ICH8 */ 2633 { PCI_DEVICE(0x8086, 0x284b), 2634 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2635 /* ICH9 */ 2636 { PCI_DEVICE(0x8086, 0x293e), 2637 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2638 /* ICH9 */ 2639 { PCI_DEVICE(0x8086, 0x293f), 2640 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2641 /* ICH10 */ 2642 { PCI_DEVICE(0x8086, 0x3a3e), 2643 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2644 /* ICH10 */ 2645 { PCI_DEVICE(0x8086, 0x3a6e), 2646 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2647 /* Generic Intel */ 2648 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2649 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2650 .class_mask = 0xffffff, 2651 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2652 /* ATI SB 450/600/700/800/900 */ 2653 { PCI_DEVICE(0x1002, 0x437b), 2654 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2655 { PCI_DEVICE(0x1002, 0x4383), 2656 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2657 /* AMD Hudson */ 2658 { PCI_DEVICE(0x1022, 0x780d), 2659 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2660 /* AMD, X370 & co */ 2661 { PCI_DEVICE(0x1022, 0x1457), 2662 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2663 /* AMD, X570 & co */ 2664 { PCI_DEVICE(0x1022, 0x1487), 2665 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2666 /* AMD Stoney */ 2667 { PCI_DEVICE(0x1022, 0x157a), 2668 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2669 AZX_DCAPS_PM_RUNTIME }, 2670 /* AMD Raven */ 2671 { PCI_DEVICE(0x1022, 0x15e3), 2672 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2673 /* ATI HDMI */ 2674 { PCI_DEVICE(0x1002, 0x0002), 2675 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2676 { PCI_DEVICE(0x1002, 0x1308), 2677 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2678 { PCI_DEVICE(0x1002, 0x157a), 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2680 { PCI_DEVICE(0x1002, 0x15b3), 2681 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2682 { PCI_DEVICE(0x1002, 0x793b), 2683 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2684 { PCI_DEVICE(0x1002, 0x7919), 2685 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2686 { PCI_DEVICE(0x1002, 0x960f), 2687 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2688 { PCI_DEVICE(0x1002, 0x970f), 2689 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2690 { PCI_DEVICE(0x1002, 0x9840), 2691 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2692 { PCI_DEVICE(0x1002, 0xaa00), 2693 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2694 { PCI_DEVICE(0x1002, 0xaa08), 2695 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2696 { PCI_DEVICE(0x1002, 0xaa10), 2697 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2698 { PCI_DEVICE(0x1002, 0xaa18), 2699 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2700 { PCI_DEVICE(0x1002, 0xaa20), 2701 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2702 { PCI_DEVICE(0x1002, 0xaa28), 2703 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2704 { PCI_DEVICE(0x1002, 0xaa30), 2705 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2706 { PCI_DEVICE(0x1002, 0xaa38), 2707 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2708 { PCI_DEVICE(0x1002, 0xaa40), 2709 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2710 { PCI_DEVICE(0x1002, 0xaa48), 2711 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2712 { PCI_DEVICE(0x1002, 0xaa50), 2713 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2714 { PCI_DEVICE(0x1002, 0xaa58), 2715 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2716 { PCI_DEVICE(0x1002, 0xaa60), 2717 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2718 { PCI_DEVICE(0x1002, 0xaa68), 2719 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2720 { PCI_DEVICE(0x1002, 0xaa80), 2721 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2722 { PCI_DEVICE(0x1002, 0xaa88), 2723 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2724 { PCI_DEVICE(0x1002, 0xaa90), 2725 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2726 { PCI_DEVICE(0x1002, 0xaa98), 2727 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2728 { PCI_DEVICE(0x1002, 0x9902), 2729 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2730 { PCI_DEVICE(0x1002, 0xaaa0), 2731 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2732 { PCI_DEVICE(0x1002, 0xaaa8), 2733 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2734 { PCI_DEVICE(0x1002, 0xaab0), 2735 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2736 { PCI_DEVICE(0x1002, 0xaac0), 2737 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2738 { PCI_DEVICE(0x1002, 0xaac8), 2739 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2740 { PCI_DEVICE(0x1002, 0xaad8), 2741 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2742 AZX_DCAPS_PM_RUNTIME }, 2743 { PCI_DEVICE(0x1002, 0xaae0), 2744 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2745 AZX_DCAPS_PM_RUNTIME }, 2746 { PCI_DEVICE(0x1002, 0xaae8), 2747 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2748 AZX_DCAPS_PM_RUNTIME }, 2749 { PCI_DEVICE(0x1002, 0xaaf0), 2750 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2751 AZX_DCAPS_PM_RUNTIME }, 2752 { PCI_DEVICE(0x1002, 0xaaf8), 2753 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2754 AZX_DCAPS_PM_RUNTIME }, 2755 { PCI_DEVICE(0x1002, 0xab00), 2756 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2757 AZX_DCAPS_PM_RUNTIME }, 2758 { PCI_DEVICE(0x1002, 0xab08), 2759 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2760 AZX_DCAPS_PM_RUNTIME }, 2761 { PCI_DEVICE(0x1002, 0xab10), 2762 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2763 AZX_DCAPS_PM_RUNTIME }, 2764 { PCI_DEVICE(0x1002, 0xab18), 2765 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2766 AZX_DCAPS_PM_RUNTIME }, 2767 { PCI_DEVICE(0x1002, 0xab20), 2768 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2769 AZX_DCAPS_PM_RUNTIME }, 2770 { PCI_DEVICE(0x1002, 0xab28), 2771 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2772 AZX_DCAPS_PM_RUNTIME }, 2773 { PCI_DEVICE(0x1002, 0xab30), 2774 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2775 AZX_DCAPS_PM_RUNTIME }, 2776 { PCI_DEVICE(0x1002, 0xab38), 2777 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2778 AZX_DCAPS_PM_RUNTIME }, 2779 /* GLENFLY */ 2780 { PCI_DEVICE(0x6766, PCI_ANY_ID), 2781 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2782 .class_mask = 0xffffff, 2783 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2784 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2785 /* VIA VT8251/VT8237A */ 2786 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2787 /* VIA GFX VT7122/VX900 */ 2788 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2789 /* VIA GFX VT6122/VX11 */ 2790 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2791 /* SIS966 */ 2792 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2793 /* ULI M5461 */ 2794 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2795 /* NVIDIA MCP */ 2796 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2797 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2798 .class_mask = 0xffffff, 2799 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2800 /* Teradici */ 2801 { PCI_DEVICE(0x6549, 0x1200), 2802 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2803 { PCI_DEVICE(0x6549, 0x2200), 2804 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2805 /* Creative X-Fi (CA0110-IBG) */ 2806 /* CTHDA chips */ 2807 { PCI_DEVICE(0x1102, 0x0010), 2808 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2809 { PCI_DEVICE(0x1102, 0x0012), 2810 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2811#if !IS_ENABLED(CONFIG_SND_CTXFI) 2812 /* the following entry conflicts with snd-ctxfi driver, 2813 * as ctxfi driver mutates from HD-audio to native mode with 2814 * a special command sequence. 2815 */ 2816 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2817 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2818 .class_mask = 0xffffff, 2819 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2820 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2821#else 2822 /* this entry seems still valid -- i.e. without emu20kx chip */ 2823 { PCI_DEVICE(0x1102, 0x0009), 2824 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2825 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2826#endif 2827 /* CM8888 */ 2828 { PCI_DEVICE(0x13f6, 0x5011), 2829 .driver_data = AZX_DRIVER_CMEDIA | 2830 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2831 /* Vortex86MX */ 2832 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2833 /* VMware HDAudio */ 2834 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2835 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2836 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2837 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2838 .class_mask = 0xffffff, 2839 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2840 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2841 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2842 .class_mask = 0xffffff, 2843 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2844 /* Zhaoxin */ 2845 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2846 { 0, } 2847}; 2848MODULE_DEVICE_TABLE(pci, azx_ids); 2849 2850/* pci_driver definition */ 2851static struct pci_driver azx_driver = { 2852 .name = KBUILD_MODNAME, 2853 .id_table = azx_ids, 2854 .probe = azx_probe, 2855 .remove = azx_remove, 2856 .shutdown = azx_shutdown, 2857 .driver = { 2858 .pm = AZX_PM_OPS, 2859 }, 2860}; 2861 2862module_pci_driver(azx_driver); 2863