1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * 4 * Implementation of primary alsa driver code base for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 */ 11 12#include <linux/clocksource.h> 13#include <linux/delay.h> 14#include <linux/interrupt.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/pm_runtime.h> 18#include <linux/slab.h> 19 20#ifdef CONFIG_X86 21/* for art-tsc conversion */ 22#include <asm/tsc.h> 23#endif 24 25#include <sound/core.h> 26#include <sound/initval.h> 27#include "hda_controller.h" 28#include "hda_local.h" 29 30#define CREATE_TRACE_POINTS 31#include "hda_controller_trace.h" 32 33/* DSP lock helpers */ 34#define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev)) 35#define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev)) 36#define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev)) 37 38/* assign a stream for the PCM */ 39static inline struct azx_dev * 40azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) 41{ 42 struct hdac_stream *s; 43 44 s = snd_hdac_stream_assign(azx_bus(chip), substream); 45 if (!s) 46 return NULL; 47 return stream_to_azx_dev(s); 48} 49 50/* release the assigned stream */ 51static inline void azx_release_device(struct azx_dev *azx_dev) 52{ 53 snd_hdac_stream_release(azx_stream(azx_dev)); 54} 55 56static inline struct hda_pcm_stream * 57to_hda_pcm_stream(struct snd_pcm_substream *substream) 58{ 59 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 60 return &apcm->info->stream[substream->stream]; 61} 62 63static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, 64 u64 nsec) 65{ 66 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 67 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); 68 u64 codec_frames, codec_nsecs; 69 70 if (!hinfo->ops.get_delay) 71 return nsec; 72 73 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); 74 codec_nsecs = div_u64(codec_frames * 1000000000LL, 75 substream->runtime->rate); 76 77 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 78 return nsec + codec_nsecs; 79 80 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 81} 82 83/* 84 * PCM ops 85 */ 86 87static int azx_pcm_close(struct snd_pcm_substream *substream) 88{ 89 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 90 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); 91 struct azx *chip = apcm->chip; 92 struct azx_dev *azx_dev = get_azx_dev(substream); 93 94 trace_azx_pcm_close(chip, azx_dev); 95 mutex_lock(&chip->open_mutex); 96 azx_release_device(azx_dev); 97 if (hinfo->ops.close) 98 hinfo->ops.close(hinfo, apcm->codec, substream); 99 snd_hda_power_down(apcm->codec); 100 mutex_unlock(&chip->open_mutex); 101 snd_hda_codec_pcm_put(apcm->info); 102 return 0; 103} 104 105static int azx_pcm_hw_params(struct snd_pcm_substream *substream, 106 struct snd_pcm_hw_params *hw_params) 107{ 108 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 109 struct azx *chip = apcm->chip; 110 struct azx_dev *azx_dev = get_azx_dev(substream); 111 int ret = 0; 112 113 trace_azx_pcm_hw_params(chip, azx_dev); 114 dsp_lock(azx_dev); 115 if (dsp_is_locked(azx_dev)) { 116 ret = -EBUSY; 117 goto unlock; 118 } 119 120 azx_dev->core.bufsize = 0; 121 azx_dev->core.period_bytes = 0; 122 azx_dev->core.format_val = 0; 123 124unlock: 125 dsp_unlock(azx_dev); 126 return ret; 127} 128 129static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 130{ 131 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 132 struct azx_dev *azx_dev = get_azx_dev(substream); 133 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); 134 135 /* reset BDL address */ 136 dsp_lock(azx_dev); 137 if (!dsp_is_locked(azx_dev)) 138 snd_hdac_stream_cleanup(azx_stream(azx_dev)); 139 140 snd_hda_codec_cleanup(apcm->codec, hinfo, substream); 141 142 azx_stream(azx_dev)->prepared = 0; 143 dsp_unlock(azx_dev); 144 return 0; 145} 146 147static int azx_pcm_prepare(struct snd_pcm_substream *substream) 148{ 149 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 150 struct azx *chip = apcm->chip; 151 struct azx_dev *azx_dev = get_azx_dev(substream); 152 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); 153 struct snd_pcm_runtime *runtime = substream->runtime; 154 unsigned int format_val, stream_tag; 155 int err; 156 struct hda_spdif_out *spdif = 157 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); 158 unsigned short ctls = spdif ? spdif->ctls : 0; 159 160 trace_azx_pcm_prepare(chip, azx_dev); 161 dsp_lock(azx_dev); 162 if (dsp_is_locked(azx_dev)) { 163 err = -EBUSY; 164 goto unlock; 165 } 166 167 snd_hdac_stream_reset(azx_stream(azx_dev)); 168 format_val = snd_hdac_calc_stream_format(runtime->rate, 169 runtime->channels, 170 runtime->format, 171 hinfo->maxbps, 172 ctls); 173 if (!format_val) { 174 dev_err(chip->card->dev, 175 "invalid format_val, rate=%d, ch=%d, format=%d\n", 176 runtime->rate, runtime->channels, runtime->format); 177 err = -EINVAL; 178 goto unlock; 179 } 180 181 err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val); 182 if (err < 0) 183 goto unlock; 184 185 snd_hdac_stream_setup(azx_stream(azx_dev)); 186 187 stream_tag = azx_dev->core.stream_tag; 188 /* CA-IBG chips need the playback stream starting from 1 */ 189 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && 190 stream_tag > chip->capture_streams) 191 stream_tag -= chip->capture_streams; 192 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, 193 azx_dev->core.format_val, substream); 194 195 unlock: 196 if (!err) 197 azx_stream(azx_dev)->prepared = 1; 198 dsp_unlock(azx_dev); 199 return err; 200} 201 202static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 203{ 204 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 205 struct azx *chip = apcm->chip; 206 struct hdac_bus *bus = azx_bus(chip); 207 struct azx_dev *azx_dev; 208 struct snd_pcm_substream *s; 209 struct hdac_stream *hstr; 210 bool start; 211 int sbits = 0; 212 int sync_reg; 213 214 azx_dev = get_azx_dev(substream); 215 trace_azx_pcm_trigger(chip, azx_dev, cmd); 216 217 hstr = azx_stream(azx_dev); 218 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) 219 sync_reg = AZX_REG_OLD_SSYNC; 220 else 221 sync_reg = AZX_REG_SSYNC; 222 223 if (dsp_is_locked(azx_dev) || !hstr->prepared) 224 return -EPIPE; 225 226 switch (cmd) { 227 case SNDRV_PCM_TRIGGER_START: 228 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 229 case SNDRV_PCM_TRIGGER_RESUME: 230 start = true; 231 break; 232 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 233 case SNDRV_PCM_TRIGGER_SUSPEND: 234 case SNDRV_PCM_TRIGGER_STOP: 235 start = false; 236 break; 237 default: 238 return -EINVAL; 239 } 240 241 snd_pcm_group_for_each_entry(s, substream) { 242 if (s->pcm->card != substream->pcm->card) 243 continue; 244 azx_dev = get_azx_dev(s); 245 sbits |= 1 << azx_dev->core.index; 246 snd_pcm_trigger_done(s, substream); 247 } 248 249 spin_lock(&bus->reg_lock); 250 251 /* first, set SYNC bits of corresponding streams */ 252 snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg); 253 254 snd_pcm_group_for_each_entry(s, substream) { 255 if (s->pcm->card != substream->pcm->card) 256 continue; 257 azx_dev = get_azx_dev(s); 258 if (start) { 259 azx_dev->insufficient = 1; 260 snd_hdac_stream_start(azx_stream(azx_dev), true); 261 } else { 262 snd_hdac_stream_stop(azx_stream(azx_dev)); 263 } 264 } 265 spin_unlock(&bus->reg_lock); 266 267 snd_hdac_stream_sync(hstr, start, sbits); 268 269 spin_lock(&bus->reg_lock); 270 /* reset SYNC bits */ 271 snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg); 272 if (start) 273 snd_hdac_stream_timecounter_init(hstr, sbits); 274 spin_unlock(&bus->reg_lock); 275 return 0; 276} 277 278unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev) 279{ 280 return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 281} 282EXPORT_SYMBOL_GPL(azx_get_pos_lpib); 283 284unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev) 285{ 286 return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev)); 287} 288EXPORT_SYMBOL_GPL(azx_get_pos_posbuf); 289 290unsigned int azx_get_position(struct azx *chip, 291 struct azx_dev *azx_dev) 292{ 293 struct snd_pcm_substream *substream = azx_dev->core.substream; 294 unsigned int pos; 295 int stream = substream->stream; 296 int delay = 0; 297 298 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) { 299 pos = chip->get_position[stream](chip, azx_dev); 300 301 if (pos >= azx_dev->fix_prvpos) { 302 pos = pos - azx_dev->fix_prvpos; 303 pos %= azx_dev->core.bufsize; 304 } else { 305 if (azx_dev->fix_prvpos > azx_dev->core.bufsize) 306 pos = (0x100000000ULL + pos-azx_dev->fix_prvpos) 307 % azx_dev->core.bufsize; 308 else 309 pos = pos + azx_dev->core.bufsize - azx_dev->fix_prvpos; 310 } 311 312 return pos; 313 } 314 315 if (chip->get_position[stream]) 316 pos = chip->get_position[stream](chip, azx_dev); 317 else /* use the position buffer as default */ 318 pos = azx_get_pos_posbuf(chip, azx_dev); 319 320 if (pos >= azx_dev->core.bufsize) 321 pos = 0; 322 323 if (substream->runtime) { 324 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 325 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); 326 327 if (chip->get_delay[stream]) 328 delay += chip->get_delay[stream](chip, azx_dev, pos); 329 if (hinfo->ops.get_delay) 330 delay += hinfo->ops.get_delay(hinfo, apcm->codec, 331 substream); 332 substream->runtime->delay = delay; 333 } 334 335 trace_azx_get_position(chip, azx_dev, pos, delay); 336 return pos; 337} 338EXPORT_SYMBOL_GPL(azx_get_position); 339 340static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 341{ 342 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 343 struct azx *chip = apcm->chip; 344 struct azx_dev *azx_dev = get_azx_dev(substream); 345 return bytes_to_frames(substream->runtime, 346 azx_get_position(chip, azx_dev)); 347} 348 349/* 350 * azx_scale64: Scale base by mult/div while not overflowing sanely 351 * 352 * Derived from scale64_check_overflow in kernel/time/timekeeping.c 353 * 354 * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which 355 * is about 384307 ie ~4.5 days. 356 * 357 * This scales the calculation so that overflow will happen but after 2^64 / 358 * 48000 secs, which is pretty large! 359 * 360 * In caln below: 361 * base may overflow, but since there isn’t any additional division 362 * performed on base it’s OK 363 * rem can’t overflow because both are 32-bit values 364 */ 365 366#ifdef CONFIG_X86 367static u64 azx_scale64(u64 base, u32 num, u32 den) 368{ 369 u64 rem; 370 371 rem = do_div(base, den); 372 373 base *= num; 374 rem *= num; 375 376 do_div(rem, den); 377 378 return base + rem; 379} 380 381static int azx_get_sync_time(ktime_t *device, 382 struct system_counterval_t *system, void *ctx) 383{ 384 struct snd_pcm_substream *substream = ctx; 385 struct azx_dev *azx_dev = get_azx_dev(substream); 386 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 387 struct azx *chip = apcm->chip; 388 struct snd_pcm_runtime *runtime; 389 u64 ll_counter, ll_counter_l, ll_counter_h; 390 u64 tsc_counter, tsc_counter_l, tsc_counter_h; 391 u32 wallclk_ctr, wallclk_cycles; 392 bool direction; 393 u32 dma_select; 394 u32 timeout; 395 u32 retry_count = 0; 396 397 runtime = substream->runtime; 398 399 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 400 direction = 1; 401 else 402 direction = 0; 403 404 /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */ 405 do { 406 timeout = 100; 407 dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) | 408 (azx_dev->core.stream_tag - 1); 409 snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select); 410 411 /* Enable the capture */ 412 snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK); 413 414 while (timeout) { 415 if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) & 416 GTSCC_TSCCD_MASK) 417 break; 418 419 timeout--; 420 } 421 422 if (!timeout) { 423 dev_err(chip->card->dev, "GTSCC capture Timedout!\n"); 424 return -EIO; 425 } 426 427 /* Read wall clock counter */ 428 wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC); 429 430 /* Read TSC counter */ 431 tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL); 432 tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU); 433 434 /* Read Link counter */ 435 ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL); 436 ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU); 437 438 /* Ack: registers read done */ 439 snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT); 440 441 tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) | 442 tsc_counter_l; 443 444 ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l; 445 wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK; 446 447 /* 448 * An error occurs near frame "rollover". The clocks in 449 * frame value indicates whether this error may have 450 * occurred. Here we use the value of 10 i.e., 451 * HDA_MAX_CYCLE_OFFSET 452 */ 453 if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET 454 && wallclk_cycles > HDA_MAX_CYCLE_OFFSET) 455 break; 456 457 /* 458 * Sleep before we read again, else we may again get 459 * value near to MAX_CYCLE. Try to sleep for different 460 * amount of time so we dont hit the same number again 461 */ 462 udelay(retry_count++); 463 464 } while (retry_count != HDA_MAX_CYCLE_READ_RETRY); 465 466 if (retry_count == HDA_MAX_CYCLE_READ_RETRY) { 467 dev_err_ratelimited(chip->card->dev, 468 "Error in WALFCC cycle count\n"); 469 return -EIO; 470 } 471 472 *device = ns_to_ktime(azx_scale64(ll_counter, 473 NSEC_PER_SEC, runtime->rate)); 474 *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) / 475 ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate)); 476 477 *system = convert_art_to_tsc(tsc_counter); 478 479 return 0; 480} 481 482#else 483static int azx_get_sync_time(ktime_t *device, 484 struct system_counterval_t *system, void *ctx) 485{ 486 return -ENXIO; 487} 488#endif 489 490static int azx_get_crosststamp(struct snd_pcm_substream *substream, 491 struct system_device_crosststamp *xtstamp) 492{ 493 return get_device_system_crosststamp(azx_get_sync_time, 494 substream, NULL, xtstamp); 495} 496 497static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime, 498 struct snd_pcm_audio_tstamp_config *ts) 499{ 500 if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME) 501 if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED) 502 return true; 503 504 return false; 505} 506 507static int azx_get_time_info(struct snd_pcm_substream *substream, 508 struct timespec64 *system_ts, struct timespec64 *audio_ts, 509 struct snd_pcm_audio_tstamp_config *audio_tstamp_config, 510 struct snd_pcm_audio_tstamp_report *audio_tstamp_report) 511{ 512 struct azx_dev *azx_dev = get_azx_dev(substream); 513 struct snd_pcm_runtime *runtime = substream->runtime; 514 struct system_device_crosststamp xtstamp; 515 int ret; 516 u64 nsec; 517 518 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && 519 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { 520 521 snd_pcm_gettime(substream->runtime, system_ts); 522 523 nsec = timecounter_read(&azx_dev->core.tc); 524 nsec = div_u64(nsec, 3); /* can be optimized */ 525 if (audio_tstamp_config->report_delay) 526 nsec = azx_adjust_codec_delay(substream, nsec); 527 528 *audio_ts = ns_to_timespec64(nsec); 529 530 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; 531 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */ 532 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */ 533 534 } else if (is_link_time_supported(runtime, audio_tstamp_config)) { 535 536 ret = azx_get_crosststamp(substream, &xtstamp); 537 if (ret) 538 return ret; 539 540 switch (runtime->tstamp_type) { 541 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC: 542 return -EINVAL; 543 544 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW: 545 *system_ts = ktime_to_timespec64(xtstamp.sys_monoraw); 546 break; 547 548 default: 549 *system_ts = ktime_to_timespec64(xtstamp.sys_realtime); 550 break; 551 552 } 553 554 *audio_ts = ktime_to_timespec64(xtstamp.device); 555 556 audio_tstamp_report->actual_type = 557 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED; 558 audio_tstamp_report->accuracy_report = 1; 559 /* 24 MHz WallClock == 42ns resolution */ 560 audio_tstamp_report->accuracy = 42; 561 562 } else { 563 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; 564 } 565 566 return 0; 567} 568 569static const struct snd_pcm_hardware azx_pcm_hw = { 570 .info = (SNDRV_PCM_INFO_MMAP | 571 SNDRV_PCM_INFO_INTERLEAVED | 572 SNDRV_PCM_INFO_BLOCK_TRANSFER | 573 SNDRV_PCM_INFO_MMAP_VALID | 574 /* No full-resume yet implemented */ 575 /* SNDRV_PCM_INFO_RESUME |*/ 576 SNDRV_PCM_INFO_PAUSE | 577 SNDRV_PCM_INFO_SYNC_START | 578 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ 579 SNDRV_PCM_INFO_HAS_LINK_ATIME | 580 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 581 .formats = SNDRV_PCM_FMTBIT_S16_LE, 582 .rates = SNDRV_PCM_RATE_48000, 583 .rate_min = 48000, 584 .rate_max = 48000, 585 .channels_min = 2, 586 .channels_max = 2, 587 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 588 .period_bytes_min = 128, 589 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 590 .periods_min = 2, 591 .periods_max = AZX_MAX_FRAG, 592 .fifo_size = 0, 593}; 594 595static int azx_pcm_open(struct snd_pcm_substream *substream) 596{ 597 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 598 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); 599 struct azx *chip = apcm->chip; 600 struct azx_dev *azx_dev; 601 struct snd_pcm_runtime *runtime = substream->runtime; 602 int err; 603 int buff_step; 604 605 snd_hda_codec_pcm_get(apcm->info); 606 mutex_lock(&chip->open_mutex); 607 azx_dev = azx_assign_device(chip, substream); 608 trace_azx_pcm_open(chip, azx_dev); 609 if (azx_dev == NULL) { 610 err = -EBUSY; 611 goto unlock; 612 } 613 runtime->private_data = azx_dev; 614 615 runtime->hw = azx_pcm_hw; 616 if (chip->gts_present) 617 runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME; 618 runtime->hw.channels_min = hinfo->channels_min; 619 runtime->hw.channels_max = hinfo->channels_max; 620 runtime->hw.formats = hinfo->formats; 621 runtime->hw.rates = hinfo->rates; 622 snd_pcm_limit_hw_rates(runtime); 623 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 624 625 /* avoid wrap-around with wall-clock */ 626 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 627 20, 628 178000000); 629 630 if (chip->align_buffer_size) 631 /* constrain buffer sizes to be multiple of 128 632 bytes. This is more efficient in terms of memory 633 access but isn't required by the HDA spec and 634 prevents users from specifying exact period/buffer 635 sizes. For example for 44.1kHz, a period size set 636 to 20ms will be rounded to 19.59ms. */ 637 buff_step = 128; 638 else 639 /* Don't enforce steps on buffer sizes, still need to 640 be multiple of 4 bytes (HDA spec). Tested on Intel 641 HDA controllers, may not work on all devices where 642 option needs to be disabled */ 643 buff_step = 4; 644 645 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 646 buff_step); 647 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 648 buff_step); 649 snd_hda_power_up(apcm->codec); 650 if (hinfo->ops.open) 651 err = hinfo->ops.open(hinfo, apcm->codec, substream); 652 else 653 err = -ENODEV; 654 if (err < 0) { 655 azx_release_device(azx_dev); 656 goto powerdown; 657 } 658 snd_pcm_limit_hw_rates(runtime); 659 /* sanity check */ 660 if (snd_BUG_ON(!runtime->hw.channels_min) || 661 snd_BUG_ON(!runtime->hw.channels_max) || 662 snd_BUG_ON(!runtime->hw.formats) || 663 snd_BUG_ON(!runtime->hw.rates)) { 664 azx_release_device(azx_dev); 665 if (hinfo->ops.close) 666 hinfo->ops.close(hinfo, apcm->codec, substream); 667 err = -EINVAL; 668 goto powerdown; 669 } 670 671 /* disable LINK_ATIME timestamps for capture streams 672 until we figure out how to handle digital inputs */ 673 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 674 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ 675 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; 676 } 677 678 snd_pcm_set_sync(substream); 679 mutex_unlock(&chip->open_mutex); 680 return 0; 681 682 powerdown: 683 snd_hda_power_down(apcm->codec); 684 unlock: 685 mutex_unlock(&chip->open_mutex); 686 snd_hda_codec_pcm_put(apcm->info); 687 return err; 688} 689 690static int azx_pcm_mmap(struct snd_pcm_substream *substream, 691 struct vm_area_struct *area) 692{ 693 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 694 struct azx *chip = apcm->chip; 695 if (chip->ops->pcm_mmap_prepare) 696 chip->ops->pcm_mmap_prepare(substream, area); 697 return snd_pcm_lib_default_mmap(substream, area); 698} 699 700static const struct snd_pcm_ops azx_pcm_ops = { 701 .open = azx_pcm_open, 702 .close = azx_pcm_close, 703 .hw_params = azx_pcm_hw_params, 704 .hw_free = azx_pcm_hw_free, 705 .prepare = azx_pcm_prepare, 706 .trigger = azx_pcm_trigger, 707 .pointer = azx_pcm_pointer, 708 .get_time_info = azx_get_time_info, 709 .mmap = azx_pcm_mmap, 710}; 711 712static void azx_pcm_free(struct snd_pcm *pcm) 713{ 714 struct azx_pcm *apcm = pcm->private_data; 715 if (apcm) { 716 list_del(&apcm->list); 717 apcm->info->pcm = NULL; 718 kfree(apcm); 719 } 720} 721 722#define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 723 724int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec, 725 struct hda_pcm *cpcm) 726{ 727 struct hdac_bus *bus = &_bus->core; 728 struct azx *chip = bus_to_azx(bus); 729 struct snd_pcm *pcm; 730 struct azx_pcm *apcm; 731 int pcm_dev = cpcm->device; 732 unsigned int size; 733 int s, err; 734 int type = SNDRV_DMA_TYPE_DEV_SG; 735 736 list_for_each_entry(apcm, &chip->pcm_list, list) { 737 if (apcm->pcm->device == pcm_dev) { 738 dev_err(chip->card->dev, "PCM %d already exists\n", 739 pcm_dev); 740 return -EBUSY; 741 } 742 } 743 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, 744 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, 745 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, 746 &pcm); 747 if (err < 0) 748 return err; 749 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); 750 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); 751 if (apcm == NULL) { 752 snd_device_free(chip->card, pcm); 753 return -ENOMEM; 754 } 755 apcm->chip = chip; 756 apcm->pcm = pcm; 757 apcm->codec = codec; 758 apcm->info = cpcm; 759 pcm->private_data = apcm; 760 pcm->private_free = azx_pcm_free; 761 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) 762 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 763 list_add_tail(&apcm->list, &chip->pcm_list); 764 cpcm->pcm = pcm; 765 for (s = 0; s < 2; s++) { 766 if (cpcm->stream[s].substreams) 767 snd_pcm_set_ops(pcm, s, &azx_pcm_ops); 768 } 769 /* buffer pre-allocation */ 770 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 771 if (size > MAX_PREALLOC_SIZE) 772 size = MAX_PREALLOC_SIZE; 773 if (chip->uc_buffer) 774 type = SNDRV_DMA_TYPE_DEV_UC_SG; 775 snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev, 776 size, MAX_PREALLOC_SIZE); 777 return 0; 778} 779 780static unsigned int azx_command_addr(u32 cmd) 781{ 782 unsigned int addr = cmd >> 28; 783 784 if (addr >= AZX_MAX_CODECS) { 785 snd_BUG(); 786 addr = 0; 787 } 788 789 return addr; 790} 791 792/* receive a response */ 793static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr, 794 unsigned int *res) 795{ 796 struct azx *chip = bus_to_azx(bus); 797 struct hda_bus *hbus = &chip->bus; 798 int err; 799 800 again: 801 err = snd_hdac_bus_get_response(bus, addr, res); 802 if (!err) 803 return 0; 804 805 if (hbus->no_response_fallback) 806 return -EIO; 807 808 if (!bus->polling_mode) { 809 dev_warn(chip->card->dev, 810 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n", 811 bus->last_cmd[addr]); 812 bus->polling_mode = 1; 813 goto again; 814 } 815 816 if (chip->msi) { 817 dev_warn(chip->card->dev, 818 "No response from codec, disabling MSI: last cmd=0x%08x\n", 819 bus->last_cmd[addr]); 820 if (chip->ops->disable_msi_reset_irq && 821 chip->ops->disable_msi_reset_irq(chip) < 0) 822 return -EIO; 823 goto again; 824 } 825 826 if (chip->probing) { 827 /* If this critical timeout happens during the codec probing 828 * phase, this is likely an access to a non-existing codec 829 * slot. Better to return an error and reset the system. 830 */ 831 return -EIO; 832 } 833 834 /* no fallback mechanism? */ 835 if (!chip->fallback_to_single_cmd) 836 return -EIO; 837 838 /* a fatal communication error; need either to reset or to fallback 839 * to the single_cmd mode 840 */ 841 if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) { 842 hbus->response_reset = 1; 843 dev_err(chip->card->dev, 844 "No response from codec, resetting bus: last cmd=0x%08x\n", 845 bus->last_cmd[addr]); 846 return -EAGAIN; /* give a chance to retry */ 847 } 848 849 dev_err(chip->card->dev, 850 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n", 851 bus->last_cmd[addr]); 852 chip->single_cmd = 1; 853 hbus->response_reset = 0; 854 snd_hdac_bus_stop_cmd_io(bus); 855 return -EIO; 856} 857 858/* 859 * Use the single immediate command instead of CORB/RIRB for simplicity 860 * 861 * Note: according to Intel, this is not preferred use. The command was 862 * intended for the BIOS only, and may get confused with unsolicited 863 * responses. So, we shouldn't use it for normal operation from the 864 * driver. 865 * I left the codes, however, for debugging/testing purposes. 866 */ 867 868/* receive a response */ 869static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) 870{ 871 int timeout = 50; 872 873 while (timeout--) { 874 /* check IRV busy bit */ 875 if (azx_readw(chip, IRS) & AZX_IRS_VALID) { 876 /* reuse rirb.res as the response return value */ 877 azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR); 878 return 0; 879 } 880 udelay(1); 881 } 882 if (printk_ratelimit()) 883 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", 884 azx_readw(chip, IRS)); 885 azx_bus(chip)->rirb.res[addr] = -1; 886 return -EIO; 887} 888 889/* send a command */ 890static int azx_single_send_cmd(struct hdac_bus *bus, u32 val) 891{ 892 struct azx *chip = bus_to_azx(bus); 893 unsigned int addr = azx_command_addr(val); 894 int timeout = 50; 895 896 bus->last_cmd[azx_command_addr(val)] = val; 897 while (timeout--) { 898 /* check ICB busy bit */ 899 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) { 900 /* Clear IRV valid bit */ 901 azx_writew(chip, IRS, azx_readw(chip, IRS) | 902 AZX_IRS_VALID); 903 azx_writel(chip, IC, val); 904 azx_writew(chip, IRS, azx_readw(chip, IRS) | 905 AZX_IRS_BUSY); 906 return azx_single_wait_for_response(chip, addr); 907 } 908 udelay(1); 909 } 910 if (printk_ratelimit()) 911 dev_dbg(chip->card->dev, 912 "send_cmd timeout: IRS=0x%x, val=0x%x\n", 913 azx_readw(chip, IRS), val); 914 return -EIO; 915} 916 917/* receive a response */ 918static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr, 919 unsigned int *res) 920{ 921 if (res) 922 *res = bus->rirb.res[addr]; 923 return 0; 924} 925 926/* 927 * The below are the main callbacks from hda_codec. 928 * 929 * They are just the skeleton to call sub-callbacks according to the 930 * current setting of chip->single_cmd. 931 */ 932 933/* send a command */ 934static int azx_send_cmd(struct hdac_bus *bus, unsigned int val) 935{ 936 struct azx *chip = bus_to_azx(bus); 937 938 if (chip->disabled) 939 return 0; 940 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 941 udelay(500); 942 if (chip->single_cmd) 943 return azx_single_send_cmd(bus, val); 944 else 945 return snd_hdac_bus_send_cmd(bus, val); 946} 947 948/* get a response */ 949static int azx_get_response(struct hdac_bus *bus, unsigned int addr, 950 unsigned int *res) 951{ 952 struct azx *chip = bus_to_azx(bus); 953 954 if (chip->disabled) 955 return 0; 956 if (chip->single_cmd) 957 return azx_single_get_response(bus, addr, res); 958 else 959 return azx_rirb_get_response(bus, addr, res); 960} 961 962static const struct hdac_bus_ops bus_core_ops = { 963 .command = azx_send_cmd, 964 .get_response = azx_get_response, 965}; 966 967#ifdef CONFIG_SND_HDA_DSP_LOADER 968/* 969 * DSP loading code (e.g. for CA0132) 970 */ 971 972/* use the first stream for loading DSP */ 973static struct azx_dev * 974azx_get_dsp_loader_dev(struct azx *chip) 975{ 976 struct hdac_bus *bus = azx_bus(chip); 977 struct hdac_stream *s; 978 979 list_for_each_entry(s, &bus->stream_list, list) 980 if (s->index == chip->playback_index_offset) 981 return stream_to_azx_dev(s); 982 983 return NULL; 984} 985 986int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, 987 unsigned int byte_size, 988 struct snd_dma_buffer *bufp) 989{ 990 struct hdac_bus *bus = &codec->bus->core; 991 struct azx *chip = bus_to_azx(bus); 992 struct azx_dev *azx_dev; 993 struct hdac_stream *hstr; 994 bool saved = false; 995 int err; 996 997 azx_dev = azx_get_dsp_loader_dev(chip); 998 hstr = azx_stream(azx_dev); 999 spin_lock_irq(&bus->reg_lock); 1000 if (hstr->opened) { 1001 chip->saved_azx_dev = *azx_dev; 1002 saved = true; 1003 } 1004 spin_unlock_irq(&bus->reg_lock); 1005 1006 err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp); 1007 if (err < 0) { 1008 spin_lock_irq(&bus->reg_lock); 1009 if (saved) 1010 *azx_dev = chip->saved_azx_dev; 1011 spin_unlock_irq(&bus->reg_lock); 1012 return err; 1013 } 1014 1015 hstr->prepared = 0; 1016 return err; 1017} 1018EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare); 1019 1020void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) 1021{ 1022 struct hdac_bus *bus = &codec->bus->core; 1023 struct azx *chip = bus_to_azx(bus); 1024 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); 1025 1026 snd_hdac_dsp_trigger(azx_stream(azx_dev), start); 1027} 1028EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger); 1029 1030void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, 1031 struct snd_dma_buffer *dmab) 1032{ 1033 struct hdac_bus *bus = &codec->bus->core; 1034 struct azx *chip = bus_to_azx(bus); 1035 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); 1036 struct hdac_stream *hstr = azx_stream(azx_dev); 1037 1038 if (!dmab->area || !hstr->locked) 1039 return; 1040 1041 snd_hdac_dsp_cleanup(hstr, dmab); 1042 spin_lock_irq(&bus->reg_lock); 1043 if (hstr->opened) 1044 *azx_dev = chip->saved_azx_dev; 1045 hstr->locked = false; 1046 spin_unlock_irq(&bus->reg_lock); 1047} 1048EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup); 1049#endif /* CONFIG_SND_HDA_DSP_LOADER */ 1050 1051/* 1052 * reset and start the controller registers 1053 */ 1054void azx_init_chip(struct azx *chip, bool full_reset) 1055{ 1056 if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) { 1057 /* correct RINTCNT for CXT */ 1058 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) 1059 azx_writew(chip, RINTCNT, 0xc0); 1060 } 1061} 1062EXPORT_SYMBOL_GPL(azx_init_chip); 1063 1064void azx_stop_all_streams(struct azx *chip) 1065{ 1066 struct hdac_bus *bus = azx_bus(chip); 1067 1068 snd_hdac_stop_streams(bus); 1069} 1070EXPORT_SYMBOL_GPL(azx_stop_all_streams); 1071 1072void azx_stop_chip(struct azx *chip) 1073{ 1074 snd_hdac_bus_stop_chip(azx_bus(chip)); 1075} 1076EXPORT_SYMBOL_GPL(azx_stop_chip); 1077 1078/* 1079 * interrupt handler 1080 */ 1081static void stream_update(struct hdac_bus *bus, struct hdac_stream *s) 1082{ 1083 struct azx *chip = bus_to_azx(bus); 1084 struct azx_dev *azx_dev = stream_to_azx_dev(s); 1085 1086 /* check whether this IRQ is really acceptable */ 1087 if (!chip->ops->position_check || 1088 chip->ops->position_check(chip, azx_dev)) { 1089 spin_unlock(&bus->reg_lock); 1090 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream); 1091 spin_lock(&bus->reg_lock); 1092 } 1093} 1094 1095irqreturn_t azx_interrupt(int irq, void *dev_id) 1096{ 1097 struct azx *chip = dev_id; 1098 struct hdac_stream *azx_dev; 1099 struct hdac_bus *bus = azx_bus(chip); 1100 u32 i = 0, status = 0; 1101 bool active, handled = false; 1102 int repeat = 0; /* count for avoiding endless loop */ 1103 1104#ifdef CONFIG_PM 1105 if (azx_has_pm_runtime(chip)) 1106 if (!pm_runtime_active(chip->card->dev)) 1107 return IRQ_NONE; 1108#endif 1109 1110 spin_lock(&bus->reg_lock); 1111 1112 if (chip->disabled) 1113 goto unlock; 1114 1115 do { 1116 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) { 1117 i = 0; 1118 status = 0; 1119 list_for_each_entry(azx_dev, &bus->stream_list, list) { 1120 status |= (snd_hdac_stream_readb(azx_dev, SD_STS) & SD_INT_MASK) ? 1121 (1 << i) : 0; 1122 i++; 1123 } 1124 status |= (status & ~0) ? (1 << 31) : 0; 1125 } 1126 else 1127 status = azx_readl(chip, INTSTS); 1128 1129 if (status == 0 || 1130 (status == 0xffffffff && !(chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND))) 1131 break; 1132 1133 handled = true; 1134 active = false; 1135 if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update)) 1136 active = true; 1137 1138 status = azx_readb(chip, RIRBSTS); 1139 if (status & RIRB_INT_MASK) { 1140 /* 1141 * Clearing the interrupt status here ensures that no 1142 * interrupt gets masked after the RIRB wp is read in 1143 * snd_hdac_bus_update_rirb. This avoids a possible 1144 * race condition where codec response in RIRB may 1145 * remain unserviced by IRQ, eventually falling back 1146 * to polling mode in azx_rirb_get_response. 1147 */ 1148 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 1149 azx_writeb(chip, RIRBSTS, status & RIRB_INT_MASK); 1150 else 1151 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1152 active = true; 1153 if (status & RIRB_INT_RESPONSE) { 1154 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) 1155 udelay(80); 1156 snd_hdac_bus_update_rirb(bus); 1157 } 1158 } 1159 } while (active && ++repeat < 10); 1160 1161 unlock: 1162 spin_unlock(&bus->reg_lock); 1163 1164 return IRQ_RETVAL(handled); 1165} 1166EXPORT_SYMBOL_GPL(azx_interrupt); 1167 1168/* 1169 * Codec initerface 1170 */ 1171 1172/* 1173 * Probe the given codec address 1174 */ 1175static int probe_codec(struct azx *chip, int addr) 1176{ 1177 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 1178 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 1179 struct hdac_bus *bus = azx_bus(chip); 1180 int err; 1181 unsigned int res = -1; 1182 1183 mutex_lock(&bus->cmd_mutex); 1184 chip->probing = 1; 1185 azx_send_cmd(bus, cmd); 1186 err = azx_get_response(bus, addr, &res); 1187 chip->probing = 0; 1188 mutex_unlock(&bus->cmd_mutex); 1189 if (err < 0 || res == -1) 1190 return -EIO; 1191 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); 1192 return 0; 1193} 1194 1195void snd_hda_bus_reset(struct hda_bus *bus) 1196{ 1197 struct azx *chip = bus_to_azx(&bus->core); 1198 1199 bus->in_reset = 1; 1200 azx_stop_chip(chip); 1201 azx_init_chip(chip, true); 1202 if (bus->core.chip_init) 1203 snd_hda_bus_reset_codecs(bus); 1204 bus->in_reset = 0; 1205} 1206 1207/* HD-audio bus initialization */ 1208int azx_bus_init(struct azx *chip, const char *model) 1209{ 1210 struct hda_bus *bus = &chip->bus; 1211 int err; 1212 1213 err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops); 1214 if (err < 0) 1215 return err; 1216 1217 bus->card = chip->card; 1218 mutex_init(&bus->prepare_mutex); 1219 bus->pci = chip->pci; 1220 bus->modelname = model; 1221 bus->mixer_assigned = -1; 1222 bus->core.snoop = azx_snoop(chip); 1223 if (chip->get_position[0] != azx_get_pos_lpib || 1224 chip->get_position[1] != azx_get_pos_lpib) 1225 bus->core.use_posbuf = true; 1226 bus->core.bdl_pos_adj = chip->bdl_pos_adj; 1227 if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR) 1228 bus->core.corbrp_self_clear = true; 1229 1230 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) 1231 bus->core.align_bdle_4k = true; 1232 1233 /* enable sync_write flag for stable communication as default */ 1234 bus->core.sync_write = 1; 1235 1236 return 0; 1237} 1238EXPORT_SYMBOL_GPL(azx_bus_init); 1239 1240/* Probe codecs */ 1241int azx_probe_codecs(struct azx *chip, unsigned int max_slots) 1242{ 1243 struct hdac_bus *bus = azx_bus(chip); 1244 int c, codecs, err; 1245 1246 codecs = 0; 1247 if (!max_slots) 1248 max_slots = AZX_DEFAULT_CODECS; 1249 1250 /* First try to probe all given codec slots */ 1251 for (c = 0; c < max_slots; c++) { 1252 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1253 if (probe_codec(chip, c) < 0) { 1254 /* Some BIOSen give you wrong codec addresses 1255 * that don't exist 1256 */ 1257 dev_warn(chip->card->dev, 1258 "Codec #%d probe error; disabling it...\n", c); 1259 bus->codec_mask &= ~(1 << c); 1260 /* More badly, accessing to a non-existing 1261 * codec often screws up the controller chip, 1262 * and disturbs the further communications. 1263 * Thus if an error occurs during probing, 1264 * better to reset the controller chip to 1265 * get back to the sanity state. 1266 */ 1267 azx_stop_chip(chip); 1268 azx_init_chip(chip, true); 1269 } 1270 } 1271 } 1272 1273 /* Then create codec instances */ 1274 for (c = 0; c < max_slots; c++) { 1275 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1276 struct hda_codec *codec; 1277 err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec); 1278 if (err < 0) 1279 continue; 1280 codec->jackpoll_interval = chip->jackpoll_interval; 1281 codec->beep_mode = chip->beep_mode; 1282 codecs++; 1283 } 1284 } 1285 if (!codecs) { 1286 dev_err(chip->card->dev, "no codecs initialized\n"); 1287 return -ENXIO; 1288 } 1289 return 0; 1290} 1291EXPORT_SYMBOL_GPL(azx_probe_codecs); 1292 1293/* configure each codec instance */ 1294int azx_codec_configure(struct azx *chip) 1295{ 1296 struct hda_codec *codec, *next; 1297 int success = 0; 1298 1299 list_for_each_codec(codec, &chip->bus) { 1300 if (!snd_hda_codec_configure(codec)) 1301 success++; 1302 } 1303 1304 if (success) { 1305 /* unregister failed codecs if any codec has been probed */ 1306 list_for_each_codec_safe(codec, next, &chip->bus) { 1307 if (!codec->configured) { 1308 codec_err(codec, "Unable to configure, disabling\n"); 1309 snd_hdac_device_unregister(&codec->core); 1310 } 1311 } 1312 } 1313 1314 return success ? 0 : -ENODEV; 1315} 1316EXPORT_SYMBOL_GPL(azx_codec_configure); 1317 1318static int stream_direction(struct azx *chip, unsigned char index) 1319{ 1320 if (index >= chip->capture_index_offset && 1321 index < chip->capture_index_offset + chip->capture_streams) 1322 return SNDRV_PCM_STREAM_CAPTURE; 1323 return SNDRV_PCM_STREAM_PLAYBACK; 1324} 1325 1326/* initialize SD streams */ 1327int azx_init_streams(struct azx *chip) 1328{ 1329 int i; 1330 int stream_tags[2] = { 0, 0 }; 1331 1332 /* initialize each stream (aka device) 1333 * assign the starting bdl address to each stream (device) 1334 * and initialize 1335 */ 1336 for (i = 0; i < chip->num_streams; i++) { 1337 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL); 1338 int dir, tag; 1339 1340 if (!azx_dev) 1341 return -ENOMEM; 1342 1343 dir = stream_direction(chip, i); 1344 /* stream tag must be unique throughout 1345 * the stream direction group, 1346 * valid values 1...15 1347 * use separate stream tag if the flag 1348 * AZX_DCAPS_SEPARATE_STREAM_TAG is used 1349 */ 1350 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) 1351 tag = ++stream_tags[dir]; 1352 else 1353 tag = i + 1; 1354 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev), 1355 i, dir, tag); 1356 } 1357 1358 return 0; 1359} 1360EXPORT_SYMBOL_GPL(azx_init_streams); 1361 1362void azx_free_streams(struct azx *chip) 1363{ 1364 struct hdac_bus *bus = azx_bus(chip); 1365 struct hdac_stream *s; 1366 1367 while (!list_empty(&bus->stream_list)) { 1368 s = list_first_entry(&bus->stream_list, struct hdac_stream, list); 1369 list_del(&s->list); 1370 kfree(stream_to_azx_dev(s)); 1371 } 1372} 1373EXPORT_SYMBOL_GPL(azx_free_streams); 1374