1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * HD-audio stream operations 4 */ 5 6#include <linux/kernel.h> 7#include <linux/delay.h> 8#include <linux/export.h> 9#include <linux/clocksource.h> 10#include <sound/core.h> 11#include <sound/pcm.h> 12#include <sound/hdaudio.h> 13#include <sound/hda_register.h> 14#include "trace.h" 15#include "../pci/hda/hda_controller.h" 16 17/** 18 * snd_hdac_get_stream_stripe_ctl - get stripe control value 19 * @bus: HD-audio core bus 20 * @substream: PCM substream 21 */ 22int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, 23 struct snd_pcm_substream *substream) 24{ 25 struct snd_pcm_runtime *runtime = substream->runtime; 26 unsigned int channels = runtime->channels, 27 rate = runtime->rate, 28 bits_per_sample = runtime->sample_bits, 29 max_sdo_lines, value, sdo_line; 30 31 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */ 32 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO; 33 34 /* following is from HD audio spec */ 35 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) { 36 if (rate > 48000) 37 value = (channels * bits_per_sample * 38 (rate / 48000)) / sdo_line; 39 else 40 value = (channels * bits_per_sample) / sdo_line; 41 42 if (value >= bus->sdo_limit) 43 break; 44 } 45 46 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */ 47 return sdo_line >> 1; 48} 49EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl); 50 51/** 52 * snd_hdac_stream_init - initialize each stream (aka device) 53 * @bus: HD-audio core bus 54 * @azx_dev: HD-audio core stream object to initialize 55 * @idx: stream index number 56 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) 57 * @tag: the tag id to assign 58 * 59 * Assign the starting bdl address to each stream (device) and initialize. 60 */ 61void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, 62 int idx, int direction, int tag) 63{ 64 azx_dev->bus = bus; 65 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 66 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); 67 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 68 azx_dev->sd_int_sta_mask = 1 << idx; 69 azx_dev->index = idx; 70 azx_dev->direction = direction; 71 azx_dev->stream_tag = tag; 72 snd_hdac_dsp_lock_init(azx_dev); 73 list_add_tail(&azx_dev->list, &bus->stream_list); 74} 75EXPORT_SYMBOL_GPL(snd_hdac_stream_init); 76 77/** 78 * snd_hdac_stream_start - start a stream 79 * @azx_dev: HD-audio core stream to start 80 * @fresh_start: false = wallclock timestamp relative to period wallclock 81 * 82 * Start a stream, set start_wallclk and set the running flag. 83 */ 84void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start) 85{ 86 struct hdac_bus *bus = azx_dev->bus; 87 struct azx *chip = bus_to_azx(bus); 88 int stripe_ctl; 89 90 trace_snd_hdac_stream_start(bus, azx_dev); 91 92 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); 93 if (!fresh_start && !(chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND)) 94 azx_dev->start_wallclk -= azx_dev->period_wallclk; 95 96 /* enable SIE */ 97 snd_hdac_chip_updatel(bus, INTCTL, 98 1 << azx_dev->index, 99 1 << azx_dev->index); 100 /* set stripe control */ 101 if (azx_dev->stripe) { 102 if (azx_dev->substream) 103 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream); 104 else 105 stripe_ctl = 0; 106 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 107 snd_hdac_stream_updatel(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 108 stripe_ctl); 109 else 110 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 111 stripe_ctl); 112 } 113 /* set DMA start and interrupt mask */ 114 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 115 snd_hdac_stream_updatel(azx_dev, SD_CTL, 116 0, SD_CTL_DMA_START | SD_INT_MASK); 117 else 118 snd_hdac_stream_updateb(azx_dev, SD_CTL, 119 0, SD_CTL_DMA_START | SD_INT_MASK); 120 azx_dev->running = true; 121} 122EXPORT_SYMBOL_GPL(snd_hdac_stream_start); 123 124/** 125 * snd_hdac_stream_clear - stop a stream DMA 126 * @azx_dev: HD-audio core stream to stop 127 */ 128void snd_hdac_stream_clear(struct hdac_stream *azx_dev) 129{ 130 int stream; 131 struct azx *chip = bus_to_azx(azx_dev->bus); 132 struct snd_pcm_substream *substream = azx_dev->substream; 133 134 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) { 135 snd_hdac_stream_updatel(azx_dev, SD_CTL, 136 SD_CTL_DMA_START | SD_INT_MASK, 0); 137 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 138 if (azx_dev->stripe) 139 snd_hdac_stream_updatel(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); 140 141 if (!substream) 142 stream_to_azx_dev(azx_dev)->fix_prvpos = 0; 143 else { 144 stream = substream->stream; 145 stream_to_azx_dev(azx_dev)->fix_prvpos = 146 chip->get_position[stream](chip, stream_to_azx_dev(azx_dev)); 147 } 148 } else { 149 snd_hdac_stream_updateb(azx_dev, SD_CTL, 150 SD_CTL_DMA_START | SD_INT_MASK, 0); 151 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 152 if (azx_dev->stripe) 153 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); 154 } 155 azx_dev->running = false; 156} 157EXPORT_SYMBOL_GPL(snd_hdac_stream_clear); 158 159/** 160 * snd_hdac_stream_stop - stop a stream 161 * @azx_dev: HD-audio core stream to stop 162 * 163 * Stop a stream DMA and disable stream interrupt 164 */ 165void snd_hdac_stream_stop(struct hdac_stream *azx_dev) 166{ 167 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev); 168 169 snd_hdac_stream_clear(azx_dev); 170 /* disable SIE */ 171 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); 172} 173EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); 174 175/** 176 * snd_hdac_stop_streams - stop all streams 177 * @bus: HD-audio core bus 178 */ 179void snd_hdac_stop_streams(struct hdac_bus *bus) 180{ 181 struct hdac_stream *stream; 182 183 list_for_each_entry(stream, &bus->stream_list, list) 184 snd_hdac_stream_stop(stream); 185} 186EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); 187 188/** 189 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running 190 * @bus: HD-audio core bus 191 */ 192void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus) 193{ 194 195 if (bus->chip_init) { 196 snd_hdac_stop_streams(bus); 197 snd_hdac_bus_stop_chip(bus); 198 } 199} 200EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip); 201 202/** 203 * snd_hdac_stream_reset - reset a stream 204 * @azx_dev: HD-audio core stream to reset 205 */ 206void snd_hdac_stream_reset(struct hdac_stream *azx_dev) 207{ 208 unsigned char val; 209 int timeout; 210 int dma_run_state; 211 struct azx *chip = bus_to_azx(azx_dev->bus); 212 213 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 214 goto out; 215 216 snd_hdac_stream_clear(azx_dev); 217 218 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; 219 220 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); 221 udelay(3); 222 timeout = 300; 223 do { 224 val = snd_hdac_stream_readb(azx_dev, SD_CTL) & 225 SD_CTL_STREAM_RESET; 226 if (val) 227 break; 228 } while (--timeout); 229 230 if (azx_dev->bus->dma_stop_delay && dma_run_state) 231 udelay(azx_dev->bus->dma_stop_delay); 232 233 val &= ~SD_CTL_STREAM_RESET; 234 snd_hdac_stream_writeb(azx_dev, SD_CTL, val); 235 udelay(3); 236 237 timeout = 300; 238 /* waiting for hardware to report that the stream is out of reset */ 239 do { 240 val = snd_hdac_stream_readb(azx_dev, SD_CTL) & 241 SD_CTL_STREAM_RESET; 242 if (!val) 243 break; 244 } while (--timeout); 245 246out: 247 /* reset first position - may not be synced with hw at this time */ 248 if (azx_dev->posbuf) 249 *azx_dev->posbuf = 0; 250} 251EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); 252 253/** 254 * snd_hdac_stream_setup - set up the SD for streaming 255 * @azx_dev: HD-audio core stream to set up 256 */ 257int snd_hdac_stream_setup(struct hdac_stream *azx_dev) 258{ 259 struct hdac_bus *bus = azx_dev->bus; 260 struct snd_pcm_runtime *runtime; 261 unsigned int val; 262 struct azx *chip = bus_to_azx(bus); 263 264 if (azx_dev->substream) 265 runtime = azx_dev->substream->runtime; 266 else 267 runtime = NULL; 268 /* make sure the run bit is zero for SD */ 269 snd_hdac_stream_clear(azx_dev); 270 /* program the stream_tag */ 271 val = snd_hdac_stream_readl(azx_dev, SD_CTL); 272 val = (val & ~SD_CTL_STREAM_TAG_MASK) | 273 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); 274 if (!bus->snoop) 275 val |= SD_CTL_TRAFFIC_PRIO; 276 snd_hdac_stream_writel(azx_dev, SD_CTL, val); 277 278 /* program the length of samples in cyclic buffer */ 279 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) { 280 if(azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 281 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize - 64); 282 else 283 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize - 16); 284 } 285 else 286 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); 287 288 /* program the stream format */ 289 /* this value needs to be the same as the one programmed */ 290 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 291 292 /* program the stream LVI (last valid index) of the BDL */ 293 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 294 295 /* program the BDL address */ 296 /* lower BDL address */ 297 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 298 /* upper BDL address */ 299 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 300 upper_32_bits(azx_dev->bdl.addr)); 301 302 /* enable the position buffer */ 303 if (bus->use_posbuf && bus->posbuf.addr) { 304 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) 305 snd_hdac_chip_writel(bus, DPLBASE, 306 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); 307 } 308 309 /* set the interrupt enable bits in the descriptor control register */ 310 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); 311 312 azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1; 313 314 /* when LPIB delay correction gives a small negative value, 315 * we ignore it; currently set the threshold statically to 316 * 64 frames 317 */ 318 if (runtime && runtime->period_size > 64) 319 azx_dev->delay_negative_threshold = 320 -frames_to_bytes(runtime, 64); 321 else 322 azx_dev->delay_negative_threshold = 0; 323 324 /* wallclk has 24Mhz clock source */ 325 if (runtime) 326 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 327 runtime->rate) * 1000); 328 329 return 0; 330} 331EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); 332 333/** 334 * snd_hdac_stream_cleanup - cleanup a stream 335 * @azx_dev: HD-audio core stream to clean up 336 */ 337void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) 338{ 339 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 340 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 341 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 342 azx_dev->bufsize = 0; 343 azx_dev->period_bytes = 0; 344 azx_dev->format_val = 0; 345} 346EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); 347 348/** 349 * snd_hdac_stream_assign - assign a stream for the PCM 350 * @bus: HD-audio core bus 351 * @substream: PCM substream to assign 352 * 353 * Look for an unused stream for the given PCM substream, assign it 354 * and return the stream object. If no stream is free, returns NULL. 355 * The function tries to keep using the same stream object when it's used 356 * beforehand. Also, when bus->reverse_assign flag is set, the last free 357 * or matching entry is returned. This is needed for some strange codecs. 358 */ 359struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, 360 struct snd_pcm_substream *substream) 361{ 362 struct hdac_stream *azx_dev; 363 struct hdac_stream *res = NULL; 364 365 /* make a non-zero unique key for the substream */ 366 int key = (substream->number << 2) | (substream->stream + 1); 367 368 if (substream->pcm) 369 key |= (substream->pcm->device << 16); 370 371 spin_lock_irq(&bus->reg_lock); 372 list_for_each_entry(azx_dev, &bus->stream_list, list) { 373 if (azx_dev->direction != substream->stream) 374 continue; 375 if (azx_dev->opened) 376 continue; 377 if (azx_dev->assigned_key == key) { 378 res = azx_dev; 379 break; 380 } 381 if (!res || bus->reverse_assign) 382 res = azx_dev; 383 } 384 if (res) { 385 res->opened = 1; 386 res->running = 0; 387 res->assigned_key = key; 388 res->substream = substream; 389 } 390 spin_unlock_irq(&bus->reg_lock); 391 return res; 392} 393EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); 394 395/** 396 * snd_hdac_stream_release - release the assigned stream 397 * @azx_dev: HD-audio core stream to release 398 * 399 * Release the stream that has been assigned by snd_hdac_stream_assign(). 400 */ 401void snd_hdac_stream_release(struct hdac_stream *azx_dev) 402{ 403 struct hdac_bus *bus = azx_dev->bus; 404 405 spin_lock_irq(&bus->reg_lock); 406 azx_dev->opened = 0; 407 azx_dev->running = 0; 408 azx_dev->substream = NULL; 409 spin_unlock_irq(&bus->reg_lock); 410} 411EXPORT_SYMBOL_GPL(snd_hdac_stream_release); 412 413/** 414 * snd_hdac_get_stream - return hdac_stream based on stream_tag and 415 * direction 416 * 417 * @bus: HD-audio core bus 418 * @dir: direction for the stream to be found 419 * @stream_tag: stream tag for stream to be found 420 */ 421struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, 422 int dir, int stream_tag) 423{ 424 struct hdac_stream *s; 425 426 list_for_each_entry(s, &bus->stream_list, list) { 427 if (s->direction == dir && s->stream_tag == stream_tag) 428 return s; 429 } 430 431 return NULL; 432} 433EXPORT_SYMBOL_GPL(snd_hdac_get_stream); 434 435/* 436 * set up a BDL entry 437 */ 438static int setup_bdle(struct hdac_bus *bus, 439 struct snd_dma_buffer *dmab, 440 struct hdac_stream *azx_dev, __le32 **bdlp, 441 int ofs, int size, int with_ioc) 442{ 443 __le32 *bdl = *bdlp; 444 445 while (size > 0) { 446 dma_addr_t addr; 447 int chunk; 448 449 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 450 return -EINVAL; 451 452 addr = snd_sgbuf_get_addr(dmab, ofs); 453 /* program the address field of the BDL entry */ 454 bdl[0] = cpu_to_le32((u32)addr); 455 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 456 /* program the size field of the BDL entry */ 457 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); 458 /* one BDLE cannot cross 4K boundary on CTHDA chips */ 459 if (bus->align_bdle_4k) { 460 u32 remain = 0x1000 - (ofs & 0xfff); 461 462 if (chunk > remain) 463 chunk = remain; 464 } 465 bdl[2] = cpu_to_le32(chunk); 466 /* program the IOC to enable interrupt 467 * only when the whole fragment is processed 468 */ 469 size -= chunk; 470 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 471 bdl += 4; 472 azx_dev->frags++; 473 ofs += chunk; 474 } 475 *bdlp = bdl; 476 return ofs; 477} 478 479/** 480 * snd_hdac_stream_setup_periods - set up BDL entries 481 * @azx_dev: HD-audio core stream to set up 482 * 483 * Set up the buffer descriptor table of the given stream based on the 484 * period and buffer sizes of the assigned PCM substream. 485 */ 486int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) 487{ 488 struct hdac_bus *bus = azx_dev->bus; 489 struct snd_pcm_substream *substream = azx_dev->substream; 490 struct snd_pcm_runtime *runtime = substream->runtime; 491 __le32 *bdl; 492 int i, ofs, periods, period_bytes; 493 int pos_adj, pos_align; 494 struct azx *chip = bus_to_azx(bus); 495 496 /* reset BDL address */ 497 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 498 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 499 500 period_bytes = azx_dev->period_bytes; 501 periods = azx_dev->bufsize / period_bytes; 502 503 /* program the initial BDL entries */ 504 bdl = (__le32 *)azx_dev->bdl.area; 505 ofs = 0; 506 azx_dev->frags = 0; 507 508 pos_adj = bus->bdl_pos_adj; 509 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 510 pos_adj = 0; 511 if (!azx_dev->no_period_wakeup && pos_adj > 0) { 512 pos_align = pos_adj; 513 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 514 if (!pos_adj) 515 pos_adj = pos_align; 516 else 517 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 518 pos_align; 519 pos_adj = frames_to_bytes(runtime, pos_adj); 520 if (pos_adj >= period_bytes) { 521 dev_warn(bus->dev, "Too big adjustment %d\n", 522 pos_adj); 523 pos_adj = 0; 524 } else { 525 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), 526 azx_dev, 527 &bdl, ofs, pos_adj, true); 528 if (ofs < 0) 529 goto error; 530 } 531 } else 532 pos_adj = 0; 533 534 for (i = 0; i < periods; i++) { 535 if (i == periods - 1 && pos_adj) 536 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), 537 azx_dev, &bdl, ofs, 538 period_bytes - pos_adj, 0); 539 else 540 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), 541 azx_dev, &bdl, ofs, 542 period_bytes, 543 !azx_dev->no_period_wakeup); 544 if (ofs < 0) 545 goto error; 546 } 547 return 0; 548 549 error: 550 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", 551 azx_dev->bufsize, period_bytes); 552 return -EINVAL; 553} 554EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); 555 556/** 557 * snd_hdac_stream_set_params - set stream parameters 558 * @azx_dev: HD-audio core stream for which parameters are to be set 559 * @format_val: format value parameter 560 * 561 * Setup the HD-audio core stream parameters from substream of the stream 562 * and passed format value 563 */ 564int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, 565 unsigned int format_val) 566{ 567 568 unsigned int bufsize, period_bytes; 569 struct snd_pcm_substream *substream = azx_dev->substream; 570 struct snd_pcm_runtime *runtime; 571 int err; 572 573 if (!substream) 574 return -EINVAL; 575 runtime = substream->runtime; 576 bufsize = snd_pcm_lib_buffer_bytes(substream); 577 period_bytes = snd_pcm_lib_period_bytes(substream); 578 579 if (bufsize != azx_dev->bufsize || 580 period_bytes != azx_dev->period_bytes || 581 format_val != azx_dev->format_val || 582 runtime->no_period_wakeup != azx_dev->no_period_wakeup) { 583 azx_dev->bufsize = bufsize; 584 azx_dev->period_bytes = period_bytes; 585 azx_dev->format_val = format_val; 586 azx_dev->no_period_wakeup = runtime->no_period_wakeup; 587 err = snd_hdac_stream_setup_periods(azx_dev); 588 if (err < 0) 589 return err; 590 } 591 return 0; 592} 593EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); 594 595static u64 azx_cc_read(const struct cyclecounter *cc) 596{ 597 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); 598 599 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); 600} 601 602static void azx_timecounter_init(struct hdac_stream *azx_dev, 603 bool force, u64 last) 604{ 605 struct timecounter *tc = &azx_dev->tc; 606 struct cyclecounter *cc = &azx_dev->cc; 607 u64 nsec; 608 609 cc->read = azx_cc_read; 610 cc->mask = CLOCKSOURCE_MASK(32); 611 612 /* 613 * Converting from 24 MHz to ns means applying a 125/3 factor. 614 * To avoid any saturation issues in intermediate operations, 615 * the 125 factor is applied first. The division is applied 616 * last after reading the timecounter value. 617 * Applying the 1/3 factor as part of the multiplication 618 * requires at least 20 bits for a decent precision, however 619 * overflows occur after about 4 hours or less, not a option. 620 */ 621 622 cc->mult = 125; /* saturation after 195 years */ 623 cc->shift = 0; 624 625 nsec = 0; /* audio time is elapsed time since trigger */ 626 timecounter_init(tc, cc, nsec); 627 if (force) { 628 /* 629 * force timecounter to use predefined value, 630 * used for synchronized starts 631 */ 632 tc->cycle_last = last; 633 } 634} 635 636/** 637 * snd_hdac_stream_timecounter_init - initialize time counter 638 * @azx_dev: HD-audio core stream (master stream) 639 * @streams: bit flags of streams to set up 640 * 641 * Initializes the time counter of streams marked by the bit flags (each 642 * bit corresponds to the stream index). 643 * The trigger timestamp of PCM substream assigned to the given stream is 644 * updated accordingly, too. 645 */ 646void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, 647 unsigned int streams) 648{ 649 struct hdac_bus *bus = azx_dev->bus; 650 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; 651 struct hdac_stream *s; 652 bool inited = false; 653 u64 cycle_last = 0; 654 655 list_for_each_entry(s, &bus->stream_list, list) { 656 if ((streams & (1 << s->index))) { 657 azx_timecounter_init(s, inited, cycle_last); 658 if (!inited) { 659 inited = true; 660 cycle_last = s->tc.cycle_last; 661 } 662 } 663 } 664 665 snd_pcm_gettime(runtime, &runtime->trigger_tstamp); 666 runtime->trigger_tstamp_latched = true; 667} 668EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); 669 670/** 671 * snd_hdac_stream_sync_trigger - turn on/off stream sync register 672 * @azx_dev: HD-audio core stream (master stream) 673 * @set: true = set, false = clear 674 * @streams: bit flags of streams to sync 675 * @reg: the stream sync register address 676 */ 677void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, 678 unsigned int streams, unsigned int reg) 679{ 680 struct hdac_bus *bus = azx_dev->bus; 681 unsigned int val; 682 683 if (!reg) 684 reg = AZX_REG_SSYNC; 685 val = _snd_hdac_chip_readl(bus, reg); 686 if (set) 687 val |= streams; 688 else 689 val &= ~streams; 690 _snd_hdac_chip_writel(bus, reg, val); 691} 692EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); 693 694/** 695 * snd_hdac_stream_sync - sync with start/strop trigger operation 696 * @azx_dev: HD-audio core stream (master stream) 697 * @start: true = start, false = stop 698 * @streams: bit flags of streams to sync 699 * 700 * For @start = true, wait until all FIFOs get ready. 701 * For @start = false, wait until all RUN bits are cleared. 702 */ 703void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, 704 unsigned int streams) 705{ 706 struct hdac_bus *bus = azx_dev->bus; 707 int nwait, timeout; 708 struct hdac_stream *s; 709 710 for (timeout = 5000; timeout; timeout--) { 711 nwait = 0; 712 list_for_each_entry(s, &bus->stream_list, list) { 713 if (!(streams & (1 << s->index))) 714 continue; 715 716 if (start) { 717 /* check FIFO gets ready */ 718 if (!(snd_hdac_stream_readb(s, SD_STS) & 719 SD_STS_FIFO_READY)) 720 nwait++; 721 } else { 722 /* check RUN bit is cleared */ 723 if (snd_hdac_stream_readb(s, SD_CTL) & 724 SD_CTL_DMA_START) { 725 nwait++; 726 /* 727 * Perform stream reset if DMA RUN 728 * bit not cleared within given timeout 729 */ 730 if (timeout == 1) 731 snd_hdac_stream_reset(s); 732 } 733 } 734 } 735 if (!nwait) 736 break; 737 cpu_relax(); 738 } 739} 740EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); 741 742#ifdef CONFIG_SND_HDA_DSP_LOADER 743/** 744 * snd_hdac_dsp_prepare - prepare for DSP loading 745 * @azx_dev: HD-audio core stream used for DSP loading 746 * @format: HD-audio stream format 747 * @byte_size: data chunk byte size 748 * @bufp: allocated buffer 749 * 750 * Allocate the buffer for the given size and set up the given stream for 751 * DSP loading. Returns the stream tag (>= 0), or a negative error code. 752 */ 753int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 754 unsigned int byte_size, struct snd_dma_buffer *bufp) 755{ 756 struct hdac_bus *bus = azx_dev->bus; 757 __le32 *bdl; 758 int err; 759 760 snd_hdac_dsp_lock(azx_dev); 761 spin_lock_irq(&bus->reg_lock); 762 if (azx_dev->running || azx_dev->locked) { 763 spin_unlock_irq(&bus->reg_lock); 764 err = -EBUSY; 765 goto unlock; 766 } 767 azx_dev->locked = true; 768 spin_unlock_irq(&bus->reg_lock); 769 770 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev, 771 byte_size, bufp); 772 if (err < 0) 773 goto err_alloc; 774 775 azx_dev->substream = NULL; 776 azx_dev->bufsize = byte_size; 777 azx_dev->period_bytes = byte_size; 778 azx_dev->format_val = format; 779 780 snd_hdac_stream_reset(azx_dev); 781 782 /* reset BDL address */ 783 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 784 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 785 786 azx_dev->frags = 0; 787 bdl = (__le32 *)azx_dev->bdl.area; 788 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0); 789 if (err < 0) 790 goto error; 791 792 snd_hdac_stream_setup(azx_dev); 793 snd_hdac_dsp_unlock(azx_dev); 794 return azx_dev->stream_tag; 795 796 error: 797 snd_dma_free_pages(bufp); 798 err_alloc: 799 spin_lock_irq(&bus->reg_lock); 800 azx_dev->locked = false; 801 spin_unlock_irq(&bus->reg_lock); 802 unlock: 803 snd_hdac_dsp_unlock(azx_dev); 804 return err; 805} 806EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); 807 808/** 809 * snd_hdac_dsp_trigger - start / stop DSP loading 810 * @azx_dev: HD-audio core stream used for DSP loading 811 * @start: trigger start or stop 812 */ 813void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) 814{ 815 if (start) 816 snd_hdac_stream_start(azx_dev, true); 817 else 818 snd_hdac_stream_stop(azx_dev); 819} 820EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); 821 822/** 823 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal 824 * @azx_dev: HD-audio core stream used for DSP loading 825 * @dmab: buffer used by DSP loading 826 */ 827void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 828 struct snd_dma_buffer *dmab) 829{ 830 struct hdac_bus *bus = azx_dev->bus; 831 832 if (!dmab->area || !azx_dev->locked) 833 return; 834 835 snd_hdac_dsp_lock(azx_dev); 836 /* reset BDL address */ 837 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 838 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 839 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 840 azx_dev->bufsize = 0; 841 azx_dev->period_bytes = 0; 842 azx_dev->format_val = 0; 843 844 snd_dma_free_pages(dmab); 845 dmab->area = NULL; 846 847 spin_lock_irq(&bus->reg_lock); 848 azx_dev->locked = false; 849 spin_unlock_irq(&bus->reg_lock); 850 snd_hdac_dsp_unlock(azx_dev); 851} 852EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); 853#endif /* CONFIG_SND_HDA_DSP_LOADER */ 854