1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * HD-audio controller helpers 4 */ 5 6#include <linux/kernel.h> 7#include <linux/delay.h> 8#include <linux/export.h> 9#include <sound/core.h> 10#include <sound/hdaudio.h> 11#include <sound/hda_register.h> 12#include "local.h" 13#include "../pci/hda/hda_controller.h" 14 15/* clear CORB read pointer properly */ 16static void azx_clear_corbrp(struct hdac_bus *bus) 17{ 18 int timeout; 19 20 for (timeout = 1000; timeout > 0; timeout--) { 21 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST) 22 break; 23 udelay(1); 24 } 25 if (timeout <= 0) 26 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", 27 snd_hdac_chip_readw(bus, CORBRP)); 28 29 snd_hdac_chip_writew(bus, CORBRP, 0); 30 for (timeout = 1000; timeout > 0; timeout--) { 31 if (snd_hdac_chip_readw(bus, CORBRP) == 0) 32 break; 33 udelay(1); 34 } 35 if (timeout <= 0) 36 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", 37 snd_hdac_chip_readw(bus, CORBRP)); 38} 39 40/** 41 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers 42 * @bus: HD-audio core bus 43 */ 44void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus) 45{ 46 struct azx *chip = bus_to_azx(bus); 47 48 WARN_ON_ONCE(!bus->rb.area); 49 50 spin_lock_irq(&bus->reg_lock); 51 /* CORB set up */ 52 bus->corb.addr = bus->rb.addr; 53 bus->corb.buf = (__le32 *)bus->rb.area; 54 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr); 55 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr)); 56 57 /* set the corb size to 256 entries (ULI requires explicitly) */ 58 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02); 59 /* set the corb write pointer to 0 */ 60 snd_hdac_chip_writew(bus, CORBWP, 0); 61 62 /* reset the corb hw read pointer */ 63 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST); 64 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 65 snd_hdac_chip_writew(bus, CORBRP, 0); 66 else if (!bus->corbrp_self_clear) 67 azx_clear_corbrp(bus); 68 69 /* enable corb dma */ 70 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN); 71 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 72 snd_hdac_chip_readb(bus, CORBCTL); 73 74 /* RIRB set up */ 75 bus->rirb.addr = bus->rb.addr + 2048; 76 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048); 77 bus->rirb.wp = bus->rirb.rp = 0; 78 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds)); 79 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr); 80 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr)); 81 82 /* set the rirb size to 256 entries (ULI requires explicitly) */ 83 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02); 84 /* reset the rirb hw write pointer */ 85 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST); 86 /* set N=1, get RIRB response interrupt for new entry */ 87 snd_hdac_chip_writew(bus, RINTCNT, 1); 88 /* enable rirb dma and response irq */ 89 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) { 90 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN); 91 snd_hdac_chip_readb(bus, RIRBCTL); 92 } 93 else 94 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); 95 /* Accept unsolicited responses */ 96 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL); 97 spin_unlock_irq(&bus->reg_lock); 98} 99EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io); 100 101/* wait for cmd dmas till they are stopped */ 102static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus) 103{ 104 unsigned long timeout; 105 106 timeout = jiffies + msecs_to_jiffies(100); 107 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN) 108 && time_before(jiffies, timeout)) 109 udelay(10); 110 111 timeout = jiffies + msecs_to_jiffies(100); 112 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN) 113 && time_before(jiffies, timeout)) 114 udelay(10); 115} 116 117/** 118 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers 119 * @bus: HD-audio core bus 120 */ 121void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus) 122{ 123 spin_lock_irq(&bus->reg_lock); 124 /* disable ringbuffer DMAs */ 125 snd_hdac_chip_writeb(bus, RIRBCTL, 0); 126 snd_hdac_chip_writeb(bus, CORBCTL, 0); 127 spin_unlock_irq(&bus->reg_lock); 128 129 hdac_wait_for_cmd_dmas(bus); 130 131 spin_lock_irq(&bus->reg_lock); 132 /* disable unsolicited responses */ 133 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0); 134 spin_unlock_irq(&bus->reg_lock); 135} 136EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io); 137 138static unsigned int azx_command_addr(u32 cmd) 139{ 140 unsigned int addr = cmd >> 28; 141 142 if (snd_BUG_ON(addr >= HDA_MAX_CODECS)) 143 addr = 0; 144 return addr; 145} 146 147static unsigned int azx_response_addr(u32 res) 148{ 149 unsigned int addr = res & 0xf; 150 151 if (addr >= AZX_MAX_CODECS) { 152 snd_BUG(); 153 addr = 0; 154 } 155 156 return addr; 157} 158 159/** 160 * snd_hdac_bus_send_cmd - send a command verb via CORB 161 * @bus: HD-audio core bus 162 * @val: encoded verb value to send 163 * 164 * Returns zero for success or a negative error code. 165 */ 166int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) 167{ 168 unsigned int addr = azx_command_addr(val); 169 unsigned int wp, rp; 170 171 spin_lock_irq(&bus->reg_lock); 172 173 bus->last_cmd[azx_command_addr(val)] = val; 174 175 /* add command to corb */ 176 wp = snd_hdac_chip_readw(bus, CORBWP); 177 if (wp == 0xffff) { 178 /* something wrong, controller likely turned to D3 */ 179 spin_unlock_irq(&bus->reg_lock); 180 return -EIO; 181 } 182 wp++; 183 wp %= AZX_MAX_CORB_ENTRIES; 184 185 rp = snd_hdac_chip_readw(bus, CORBRP); 186 if (wp == rp) { 187 /* oops, it's full */ 188 spin_unlock_irq(&bus->reg_lock); 189 return -EAGAIN; 190 } 191 192 bus->rirb.cmds[addr]++; 193 bus->corb.buf[wp] = cpu_to_le32(val); 194 snd_hdac_chip_writew(bus, CORBWP, wp); 195 196 spin_unlock_irq(&bus->reg_lock); 197 198 return 0; 199} 200EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd); 201 202#define AZX_RIRB_EX_UNSOL_EV (1<<4) 203 204/** 205 * snd_hdac_bus_update_rirb - retrieve RIRB entries 206 * @bus: HD-audio core bus 207 * 208 * Usually called from interrupt handler. 209 * The caller needs bus->reg_lock spinlock before calling this. 210 */ 211void snd_hdac_bus_update_rirb(struct hdac_bus *bus) 212{ 213 unsigned int rp, wp; 214 unsigned int addr; 215 u32 res, res_ex; 216 217 wp = snd_hdac_chip_readw(bus, RIRBWP); 218 if (wp == 0xffff) { 219 /* something wrong, controller likely turned to D3 */ 220 return; 221 } 222 223 if (wp == bus->rirb.wp) 224 return; 225 bus->rirb.wp = wp; 226 227 while (bus->rirb.rp != wp) { 228 bus->rirb.rp++; 229 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES; 230 231 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 232 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]); 233 res = le32_to_cpu(bus->rirb.buf[rp]); 234 addr = azx_response_addr(res_ex); 235 if (res_ex & AZX_RIRB_EX_UNSOL_EV) 236 snd_hdac_bus_queue_event(bus, res, res_ex); 237 else if (bus->rirb.cmds[addr]) { 238 bus->rirb.res[addr] = res; 239 bus->rirb.cmds[addr]--; 240 if (!bus->rirb.cmds[addr] && 241 waitqueue_active(&bus->rirb_wq)) 242 wake_up(&bus->rirb_wq); 243 } else { 244 dev_err_ratelimited(bus->dev, 245 "spurious response %#x:%#x, last cmd=%#08x\n", 246 res, res_ex, bus->last_cmd[addr]); 247 } 248 } 249} 250EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb); 251 252/** 253 * snd_hdac_bus_get_response - receive a response via RIRB 254 * @bus: HD-audio core bus 255 * @addr: codec address 256 * @res: pointer to store the value, NULL when not needed 257 * 258 * Returns zero if a value is read, or a negative error code. 259 */ 260int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, 261 unsigned int *res) 262{ 263 unsigned long timeout; 264 unsigned long loopcounter; 265 wait_queue_entry_t wait; 266 bool warned = false; 267 268 init_wait_entry(&wait, 0); 269 timeout = jiffies + msecs_to_jiffies(1000); 270 271 for (loopcounter = 0;; loopcounter++) { 272 spin_lock_irq(&bus->reg_lock); 273 if (!bus->polling_mode) 274 prepare_to_wait(&bus->rirb_wq, &wait, 275 TASK_UNINTERRUPTIBLE); 276 if (bus->polling_mode) 277 snd_hdac_bus_update_rirb(bus); 278 if (!bus->rirb.cmds[addr]) { 279 if (res) 280 *res = bus->rirb.res[addr]; /* the last value */ 281 if (!bus->polling_mode) 282 finish_wait(&bus->rirb_wq, &wait); 283 spin_unlock_irq(&bus->reg_lock); 284 return 0; 285 } 286 spin_unlock_irq(&bus->reg_lock); 287 if (time_after(jiffies, timeout)) 288 break; 289#define LOOP_COUNT_MAX 3000 290 if (!bus->polling_mode) { 291 schedule_timeout(msecs_to_jiffies(2)); 292 } else if (bus->needs_damn_long_delay || 293 loopcounter > LOOP_COUNT_MAX) { 294 if (loopcounter > LOOP_COUNT_MAX && !warned) { 295 dev_dbg_ratelimited(bus->dev, 296 "too slow response, last cmd=%#08x\n", 297 bus->last_cmd[addr]); 298 warned = true; 299 } 300 msleep(2); /* temporary workaround */ 301 } else { 302 udelay(10); 303 cond_resched(); 304 } 305 } 306 307 if (!bus->polling_mode) 308 finish_wait(&bus->rirb_wq, &wait); 309 310 return -EIO; 311} 312EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response); 313 314#define HDAC_MAX_CAPS 10 315/** 316 * snd_hdac_bus_parse_capabilities - parse capability structure 317 * @bus: the pointer to bus object 318 * 319 * Returns 0 if successful, or a negative error code. 320 */ 321int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus) 322{ 323 unsigned int cur_cap; 324 unsigned int offset; 325 unsigned int counter = 0; 326 327 offset = snd_hdac_chip_readw(bus, LLCH); 328 329 /* Lets walk the linked capabilities list */ 330 do { 331 cur_cap = _snd_hdac_chip_readl(bus, offset); 332 333 dev_dbg(bus->dev, "Capability version: 0x%x\n", 334 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF); 335 336 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n", 337 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF); 338 339 if (cur_cap == -1) { 340 dev_dbg(bus->dev, "Invalid capability reg read\n"); 341 break; 342 } 343 344 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) { 345 case AZX_ML_CAP_ID: 346 dev_dbg(bus->dev, "Found ML capability\n"); 347 bus->mlcap = bus->remap_addr + offset; 348 break; 349 350 case AZX_GTS_CAP_ID: 351 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset); 352 bus->gtscap = bus->remap_addr + offset; 353 break; 354 355 case AZX_PP_CAP_ID: 356 /* PP capability found, the Audio DSP is present */ 357 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset); 358 bus->ppcap = bus->remap_addr + offset; 359 break; 360 361 case AZX_SPB_CAP_ID: 362 /* SPIB capability found, handler function */ 363 dev_dbg(bus->dev, "Found SPB capability\n"); 364 bus->spbcap = bus->remap_addr + offset; 365 break; 366 367 case AZX_DRSM_CAP_ID: 368 /* DMA resume capability found, handler function */ 369 dev_dbg(bus->dev, "Found DRSM capability\n"); 370 bus->drsmcap = bus->remap_addr + offset; 371 break; 372 373 default: 374 dev_err(bus->dev, "Unknown capability %d\n", cur_cap); 375 cur_cap = 0; 376 break; 377 } 378 379 counter++; 380 381 if (counter > HDAC_MAX_CAPS) { 382 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n"); 383 break; 384 } 385 386 /* read the offset of next capability */ 387 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK; 388 389 } while (offset); 390 391 return 0; 392} 393EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities); 394 395/* 396 * Lowlevel interface 397 */ 398 399/** 400 * snd_hdac_bus_enter_link_reset - enter link reset 401 * @bus: HD-audio core bus 402 * 403 * Enter to the link reset state. 404 */ 405void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus) 406{ 407 unsigned long timeout; 408 409 /* reset controller */ 410 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0); 411 412 timeout = jiffies + msecs_to_jiffies(100); 413 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) && 414 time_before(jiffies, timeout)) 415 usleep_range(500, 1000); 416} 417EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset); 418 419/** 420 * snd_hdac_bus_exit_link_reset - exit link reset 421 * @bus: HD-audio core bus 422 * 423 * Exit from the link reset state. 424 */ 425void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus) 426{ 427 unsigned long timeout; 428 429 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET); 430 431 timeout = jiffies + msecs_to_jiffies(100); 432 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout)) 433 usleep_range(500, 1000); 434} 435EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset); 436 437/* reset codec link */ 438int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset) 439{ 440 if (!full_reset) 441 goto skip_reset; 442 443 /* clear STATESTS if not in reset */ 444 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) 445 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); 446 447 /* reset controller */ 448 snd_hdac_bus_enter_link_reset(bus); 449 450 /* delay for >= 100us for codec PLL to settle per spec 451 * Rev 0.9 section 5.5.1 452 */ 453 usleep_range(500, 1000); 454 455 /* Bring controller out of reset */ 456 snd_hdac_bus_exit_link_reset(bus); 457 458 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 459 usleep_range(1000, 1200); 460 461 skip_reset: 462 /* check to see if controller is ready */ 463 if (!snd_hdac_chip_readb(bus, GCTL)) { 464 dev_dbg(bus->dev, "controller not ready!\n"); 465 return -EBUSY; 466 } 467 468 /* detect codecs */ 469 if (!bus->codec_mask) { 470 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS); 471 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask); 472 } 473 474 return 0; 475} 476EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link); 477 478/* enable interrupts */ 479static void azx_int_enable(struct hdac_bus *bus) 480{ 481 /* enable controller CIE and GIE */ 482 snd_hdac_chip_updatel(bus, INTCTL, 483 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 484 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN); 485} 486 487/* disable interrupts */ 488static void azx_int_disable(struct hdac_bus *bus) 489{ 490 struct hdac_stream *azx_dev; 491 492 /* disable interrupts in stream descriptor */ 493 list_for_each_entry(azx_dev, &bus->stream_list, list) 494 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0); 495 496 /* disable SIE for all streams */ 497 snd_hdac_chip_writeb(bus, INTCTL, 0); 498 499 /* disable controller CIE and GIE */ 500 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0); 501} 502 503/* clear interrupts */ 504static void azx_int_clear(struct hdac_bus *bus) 505{ 506 struct hdac_stream *azx_dev; 507 struct azx *chip = bus_to_azx(bus); 508 509 /* clear stream status */ 510 list_for_each_entry(azx_dev, &bus->stream_list, list) { 511 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 512 snd_hdac_stream_updateb(azx_dev, SD_STS, 0, 0); 513 else 514 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); 515 } 516 517 /* clear STATESTS */ 518 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); 519 520 /* clear rirb status */ 521 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 522 snd_hdac_chip_updateb(bus, RIRBSTS, ~RIRB_INT_MASK, 0); 523 else 524 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 525 526 /* clear int status */ 527 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM); 528} 529 530/** 531 * snd_hdac_bus_init_chip - reset and start the controller registers 532 * @bus: HD-audio core bus 533 * @full_reset: Do full reset 534 */ 535bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset) 536{ 537 if (bus->chip_init) 538 return false; 539 540 /* reset controller */ 541 snd_hdac_bus_reset_link(bus, full_reset); 542 543 /* clear interrupts */ 544 azx_int_clear(bus); 545 546 /* initialize the codec command I/O */ 547 snd_hdac_bus_init_cmd_io(bus); 548 549 /* enable interrupts after CORB/RIRB buffers are initialized above */ 550 azx_int_enable(bus); 551 552 /* program the position buffer */ 553 if (bus->use_posbuf && bus->posbuf.addr) { 554 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr); 555 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr)); 556 } 557 558 bus->chip_init = true; 559 560 return true; 561} 562EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip); 563 564/** 565 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os 566 * @bus: HD-audio core bus 567 */ 568void snd_hdac_bus_stop_chip(struct hdac_bus *bus) 569{ 570 if (!bus->chip_init) 571 return; 572 573 /* disable interrupts */ 574 azx_int_disable(bus); 575 azx_int_clear(bus); 576 577 /* disable CORB/RIRB */ 578 snd_hdac_bus_stop_cmd_io(bus); 579 580 /* disable position buffer */ 581 if (bus->posbuf.addr) { 582 snd_hdac_chip_writel(bus, DPLBASE, 0); 583 snd_hdac_chip_writel(bus, DPUBASE, 0); 584 } 585 586 bus->chip_init = false; 587} 588EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip); 589 590/** 591 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams 592 * @bus: HD-audio core bus 593 * @status: INTSTS register value 594 * @ack: callback to be called for woken streams 595 * 596 * Returns the bits of handled streams, or zero if no stream is handled. 597 */ 598int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, 599 void (*ack)(struct hdac_bus *, 600 struct hdac_stream *)) 601{ 602 struct hdac_stream *azx_dev; 603 u8 sd_status; 604 int handled = 0; 605 struct azx *chip = bus_to_azx(bus); 606 607 list_for_each_entry(azx_dev, &bus->stream_list, list) { 608 if (status & azx_dev->sd_int_sta_mask) { 609 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS); 610 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) { 611 snd_hdac_stream_writeb(azx_dev, SD_STS, sd_status); 612 snd_hdac_stream_readb(azx_dev, SD_STS); 613 } 614 else 615 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); 616 handled |= 1 << azx_dev->index; 617 if (!azx_dev->substream || !azx_dev->running || 618 !(sd_status & SD_INT_COMPLETE)) 619 continue; 620 if (ack) 621 ack(bus, azx_dev); 622 } 623 } 624 return handled; 625} 626EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq); 627 628/** 629 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers 630 * @bus: HD-audio core bus 631 * 632 * Call this after assigning the all streams. 633 * Returns zero for success, or a negative error code. 634 */ 635int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus) 636{ 637 struct hdac_stream *s; 638 int num_streams = 0; 639 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV; 640 int err; 641 642 list_for_each_entry(s, &bus->stream_list, list) { 643 /* allocate memory for the BDL for each stream */ 644 err = snd_dma_alloc_pages(dma_type, bus->dev, 645 BDL_SIZE, &s->bdl); 646 num_streams++; 647 if (err < 0) 648 return -ENOMEM; 649 } 650 651 if (WARN_ON(!num_streams)) 652 return -EINVAL; 653 /* allocate memory for the position buffer */ 654 err = snd_dma_alloc_pages(dma_type, bus->dev, 655 num_streams * 8, &bus->posbuf); 656 if (err < 0) 657 return -ENOMEM; 658 list_for_each_entry(s, &bus->stream_list, list) 659 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8); 660 661 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 662 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb); 663} 664EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages); 665 666/** 667 * snd_hdac_bus_free_stream_pages - release BDL and other buffers 668 * @bus: HD-audio core bus 669 */ 670void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus) 671{ 672 struct hdac_stream *s; 673 674 list_for_each_entry(s, &bus->stream_list, list) { 675 if (s->bdl.area) 676 snd_dma_free_pages(&s->bdl); 677 } 678 679 if (bus->rb.area) 680 snd_dma_free_pages(&bus->rb); 681 if (bus->posbuf.area) 682 snd_dma_free_pages(&bus->posbuf); 683} 684EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages); 685