1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * HD-audio core bus driver 4 */ 5 6#include <linux/init.h> 7#include <linux/io.h> 8#include <linux/device.h> 9#include <linux/module.h> 10#include <linux/export.h> 11#include <sound/hdaudio.h> 12#include "local.h" 13#include "trace.h" 14#include "../pci/hda/hda_controller.h" 15 16static void snd_hdac_bus_process_unsol_events(struct work_struct *work); 17 18static const struct hdac_bus_ops default_ops = { 19 .command = snd_hdac_bus_send_cmd, 20 .get_response = snd_hdac_bus_get_response, 21}; 22 23/** 24 * snd_hdac_bus_init - initialize a HD-audio bas bus 25 * @bus: the pointer to bus object 26 * @dev: device pointer 27 * @ops: bus verb operators 28 * 29 * Returns 0 if successful, or a negative error code. 30 */ 31int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, 32 const struct hdac_bus_ops *ops) 33{ 34 memset(bus, 0, sizeof(*bus)); 35 bus->dev = dev; 36 if (ops) 37 bus->ops = ops; 38 else 39 bus->ops = &default_ops; 40 bus->dma_type = SNDRV_DMA_TYPE_DEV; 41 INIT_LIST_HEAD(&bus->stream_list); 42 INIT_LIST_HEAD(&bus->codec_list); 43 INIT_WORK(&bus->unsol_work, snd_hdac_bus_process_unsol_events); 44 spin_lock_init(&bus->reg_lock); 45 mutex_init(&bus->cmd_mutex); 46 mutex_init(&bus->lock); 47 INIT_LIST_HEAD(&bus->hlink_list); 48 init_waitqueue_head(&bus->rirb_wq); 49 bus->irq = -1; 50 51 /* 52 * Default value of '8' is as per the HD audio specification (Rev 1.0a). 53 * Following relation is used to derive STRIPE control value. 54 * For sample rate <= 48K: 55 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } 56 * For sample rate > 48K: 57 * { ((num_channels * bits_per_sample * rate/48000) / 58 * number of SDOs) >= 8 } 59 */ 60 bus->sdo_limit = 8; 61 62 return 0; 63} 64EXPORT_SYMBOL_GPL(snd_hdac_bus_init); 65 66/** 67 * snd_hdac_bus_exit - clean up a HD-audio bas bus 68 * @bus: the pointer to bus object 69 */ 70void snd_hdac_bus_exit(struct hdac_bus *bus) 71{ 72 WARN_ON(!list_empty(&bus->stream_list)); 73 WARN_ON(!list_empty(&bus->codec_list)); 74 cancel_work_sync(&bus->unsol_work); 75} 76EXPORT_SYMBOL_GPL(snd_hdac_bus_exit); 77 78/** 79 * snd_hdac_bus_exec_verb - execute a HD-audio verb on the given bus 80 * @bus: bus object 81 * @addr: the HDAC device address 82 * @cmd: HD-audio encoded verb 83 * @res: pointer to store the response, NULL if performing asynchronously 84 * 85 * Returns 0 if successful, or a negative error code. 86 */ 87int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr, 88 unsigned int cmd, unsigned int *res) 89{ 90 int err; 91 92 mutex_lock(&bus->cmd_mutex); 93 err = snd_hdac_bus_exec_verb_unlocked(bus, addr, cmd, res); 94 mutex_unlock(&bus->cmd_mutex); 95 return err; 96} 97 98/** 99 * snd_hdac_bus_exec_verb_unlocked - unlocked version 100 * @bus: bus object 101 * @addr: the HDAC device address 102 * @cmd: HD-audio encoded verb 103 * @res: pointer to store the response, NULL if performing asynchronously 104 * 105 * Returns 0 if successful, or a negative error code. 106 */ 107int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, 108 unsigned int cmd, unsigned int *res) 109{ 110 unsigned int tmp; 111 int err; 112 struct azx *chip = bus_to_azx(bus); 113 114 if (cmd == ~0) 115 return -EINVAL; 116 117 if (res) 118 *res = -1; 119 else if (bus->sync_write) 120 res = &tmp; 121 if (chip->driver_caps & AZX_DCAPS_LS2X_WORKAROUND) 122 err = bus->ops->command(bus, cmd); 123 else for (;;) { 124 trace_hda_send_cmd(bus, cmd); 125 err = bus->ops->command(bus, cmd); 126 if (err != -EAGAIN) 127 break; 128 /* process pending verbs */ 129 err = bus->ops->get_response(bus, addr, &tmp); 130 if (err) 131 break; 132 } 133 if (!err && res) { 134 err = bus->ops->get_response(bus, addr, res); 135 trace_hda_get_response(bus, addr, *res); 136 } 137 return err; 138} 139EXPORT_SYMBOL_GPL(snd_hdac_bus_exec_verb_unlocked); 140 141/** 142 * snd_hdac_bus_queue_event - add an unsolicited event to queue 143 * @bus: the BUS 144 * @res: unsolicited event (lower 32bit of RIRB entry) 145 * @res_ex: codec addr and flags (upper 32bit or RIRB entry) 146 * 147 * Adds the given event to the queue. The events are processed in 148 * the workqueue asynchronously. Call this function in the interrupt 149 * hanlder when RIRB receives an unsolicited event. 150 */ 151void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex) 152{ 153 unsigned int wp; 154 155 if (!bus) 156 return; 157 158 trace_hda_unsol_event(bus, res, res_ex); 159 wp = (bus->unsol_wp + 1) % HDA_UNSOL_QUEUE_SIZE; 160 bus->unsol_wp = wp; 161 162 wp <<= 1; 163 bus->unsol_queue[wp] = res; 164 bus->unsol_queue[wp + 1] = res_ex; 165 166 schedule_work(&bus->unsol_work); 167} 168 169/* 170 * process queued unsolicited events 171 */ 172static void snd_hdac_bus_process_unsol_events(struct work_struct *work) 173{ 174 struct hdac_bus *bus = container_of(work, struct hdac_bus, unsol_work); 175 struct hdac_device *codec; 176 struct hdac_driver *drv; 177 unsigned int rp, caddr, res; 178 179 spin_lock_irq(&bus->reg_lock); 180 while (bus->unsol_rp != bus->unsol_wp) { 181 rp = (bus->unsol_rp + 1) % HDA_UNSOL_QUEUE_SIZE; 182 bus->unsol_rp = rp; 183 rp <<= 1; 184 res = bus->unsol_queue[rp]; 185 caddr = bus->unsol_queue[rp + 1]; 186 if (!(caddr & (1 << 4))) /* no unsolicited event? */ 187 continue; 188 codec = bus->caddr_tbl[caddr & 0x0f]; 189 if (!codec || !codec->dev.driver) 190 continue; 191 spin_unlock_irq(&bus->reg_lock); 192 drv = drv_to_hdac_driver(codec->dev.driver); 193 if (drv->unsol_event) 194 drv->unsol_event(codec, res); 195 spin_lock_irq(&bus->reg_lock); 196 } 197 spin_unlock_irq(&bus->reg_lock); 198} 199 200/** 201 * snd_hdac_bus_add_device - Add a codec to bus 202 * @bus: HDA core bus 203 * @codec: HDA core device to add 204 * 205 * Adds the given codec to the list in the bus. The caddr_tbl array 206 * and codec_powered bits are updated, as well. 207 * Returns zero if success, or a negative error code. 208 */ 209int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec) 210{ 211 if (bus->caddr_tbl[codec->addr]) { 212 dev_err(bus->dev, "address 0x%x is already occupied\n", 213 codec->addr); 214 return -EBUSY; 215 } 216 217 list_add_tail(&codec->list, &bus->codec_list); 218 bus->caddr_tbl[codec->addr] = codec; 219 set_bit(codec->addr, &bus->codec_powered); 220 bus->num_codecs++; 221 return 0; 222} 223 224/** 225 * snd_hdac_bus_remove_device - Remove a codec from bus 226 * @bus: HDA core bus 227 * @codec: HDA core device to remove 228 */ 229void snd_hdac_bus_remove_device(struct hdac_bus *bus, 230 struct hdac_device *codec) 231{ 232 WARN_ON(bus != codec->bus); 233 if (list_empty(&codec->list)) 234 return; 235 list_del_init(&codec->list); 236 bus->caddr_tbl[codec->addr] = NULL; 237 clear_bit(codec->addr, &bus->codec_powered); 238 bus->num_codecs--; 239 flush_work(&bus->unsol_work); 240} 241 242#ifdef CONFIG_SND_HDA_ALIGNED_MMIO 243/* Helpers for aligned read/write of mmio space, for Tegra */ 244unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask) 245{ 246 void __iomem *aligned_addr = 247 (void __iomem *)((unsigned long)(addr) & ~0x3); 248 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 249 unsigned int v; 250 251 v = readl(aligned_addr); 252 return (v >> shift) & mask; 253} 254EXPORT_SYMBOL_GPL(snd_hdac_aligned_read); 255 256void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, 257 unsigned int mask) 258{ 259 void __iomem *aligned_addr = 260 (void __iomem *)((unsigned long)(addr) & ~0x3); 261 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 262 unsigned int v; 263 264 v = readl(aligned_addr); 265 v &= ~(mask << shift); 266 v |= val << shift; 267 writel(v, aligned_addr); 268} 269EXPORT_SYMBOL_GPL(snd_hdac_aligned_write); 270#endif /* CONFIG_SND_HDA_ALIGNED_MMIO */ 271