18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2018 Zodiac Inflight Innovations 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef DT_BINDING_RESET_IMX8MQ_H 98c2ecf20Sopenharmony_ci#define DT_BINDING_RESET_IMX8MQ_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 128c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 138c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 148c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 158c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_RESET0 4 168c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_RESET1 5 178c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_RESET2 6 188c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_RESET3 7 198c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_DBG_RESET0 8 208c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_DBG_RESET1 9 218c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_DBG_RESET2 10 228c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_DBG_RESET3 11 238c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_ETM_RESET0 12 248c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_ETM_RESET1 13 258c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_ETM_RESET2 14 268c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_ETM_RESET3 15 278c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 288c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_A53_L2RESET 17 298c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 308c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_OTG1_PHY_RESET 19 318c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ 328c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ 338c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ 348c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ 358c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ 368c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ 378c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ 388c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ 398c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ 408c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ 418c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ 428c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_DISP_RESET 31 438c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_GPU_RESET 32 448c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ 458c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ 468c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ 478c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ 488c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ 498c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ 508c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ 518c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ 528c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ 538c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ 548c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ 558c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ 568c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ 578c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ 588c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ 598c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ 608c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ 618c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_SW_M4C_RST 50 628c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_SW_M4P_RST 51 638c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_M4_ENABLE 52 648c2ecf20Sopenharmony_ci 658c2ecf20Sopenharmony_ci#define IMX8MQ_RESET_NUM 53 668c2ecf20Sopenharmony_ci 678c2ecf20Sopenharmony_ci#endif 68