18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2017 Impinj, Inc. 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef DT_BINDING_RESET_IMX7_H 98c2ecf20Sopenharmony_ci#define DT_BINDING_RESET_IMX7_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_CORE_POR_RESET0 0 128c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_CORE_POR_RESET1 1 138c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_CORE_RESET0 2 148c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_CORE_RESET1 3 158c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_DBG_RESET0 4 168c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_DBG_RESET1 5 178c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_ETM_RESET0 6 188c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_ETM_RESET1 7 198c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_SOC_DBG_RESET 8 208c2ecf20Sopenharmony_ci#define IMX7_RESET_A7_L2RESET 9 218c2ecf20Sopenharmony_ci#define IMX7_RESET_SW_M4C_RST 10 228c2ecf20Sopenharmony_ci#define IMX7_RESET_SW_M4P_RST 11 238c2ecf20Sopenharmony_ci#define IMX7_RESET_EIM_RST 12 248c2ecf20Sopenharmony_ci#define IMX7_RESET_HSICPHY_PORT_RST 13 258c2ecf20Sopenharmony_ci#define IMX7_RESET_USBPHY1_POR 14 268c2ecf20Sopenharmony_ci#define IMX7_RESET_USBPHY1_PORT_RST 15 278c2ecf20Sopenharmony_ci#define IMX7_RESET_USBPHY2_POR 16 288c2ecf20Sopenharmony_ci#define IMX7_RESET_USBPHY2_PORT_RST 17 298c2ecf20Sopenharmony_ci#define IMX7_RESET_MIPI_PHY_MRST 18 308c2ecf20Sopenharmony_ci#define IMX7_RESET_MIPI_PHY_SRST 19 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci/* 338c2ecf20Sopenharmony_ci * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN 348c2ecf20Sopenharmony_ci * and PCIEPHY_G_RST 358c2ecf20Sopenharmony_ci */ 368c2ecf20Sopenharmony_ci#define IMX7_RESET_PCIEPHY 20 378c2ecf20Sopenharmony_ci#define IMX7_RESET_PCIEPHY_PERST 21 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci/* 408c2ecf20Sopenharmony_ci * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it 418c2ecf20Sopenharmony_ci * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht 428c2ecf20Sopenharmony_ci * of as one 438c2ecf20Sopenharmony_ci */ 448c2ecf20Sopenharmony_ci#define IMX7_RESET_PCIE_CTRL_APPS_EN 22 458c2ecf20Sopenharmony_ci#define IMX7_RESET_DDRC_PRST 23 468c2ecf20Sopenharmony_ci#define IMX7_RESET_DDRC_CORE_RST 24 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci#define IMX7_RESET_NUM 26 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#endif 538c2ecf20Sopenharmony_ci 54