18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2016 Intel Corporation. All rights reserved 48c2ecf20Sopenharmony_ci * Copyright (C) 2016 Altera Corporation. All rights reserved 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 108c2ecf20Sopenharmony_ci#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci/* MPUMODRST */ 138c2ecf20Sopenharmony_ci#define CPU0_RESET 0 148c2ecf20Sopenharmony_ci#define CPU1_RESET 1 158c2ecf20Sopenharmony_ci#define CPU2_RESET 2 168c2ecf20Sopenharmony_ci#define CPU3_RESET 3 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci/* PER0MODRST */ 198c2ecf20Sopenharmony_ci#define EMAC0_RESET 32 208c2ecf20Sopenharmony_ci#define EMAC1_RESET 33 218c2ecf20Sopenharmony_ci#define EMAC2_RESET 34 228c2ecf20Sopenharmony_ci#define USB0_RESET 35 238c2ecf20Sopenharmony_ci#define USB1_RESET 36 248c2ecf20Sopenharmony_ci#define NAND_RESET 37 258c2ecf20Sopenharmony_ci/* 38 is empty */ 268c2ecf20Sopenharmony_ci#define SDMMC_RESET 39 278c2ecf20Sopenharmony_ci#define EMAC0_OCP_RESET 40 288c2ecf20Sopenharmony_ci#define EMAC1_OCP_RESET 41 298c2ecf20Sopenharmony_ci#define EMAC2_OCP_RESET 42 308c2ecf20Sopenharmony_ci#define USB0_OCP_RESET 43 318c2ecf20Sopenharmony_ci#define USB1_OCP_RESET 44 328c2ecf20Sopenharmony_ci#define NAND_OCP_RESET 45 338c2ecf20Sopenharmony_ci/* 46 is empty */ 348c2ecf20Sopenharmony_ci#define SDMMC_OCP_RESET 47 358c2ecf20Sopenharmony_ci#define DMA_RESET 48 368c2ecf20Sopenharmony_ci#define SPIM0_RESET 49 378c2ecf20Sopenharmony_ci#define SPIM1_RESET 50 388c2ecf20Sopenharmony_ci#define SPIS0_RESET 51 398c2ecf20Sopenharmony_ci#define SPIS1_RESET 52 408c2ecf20Sopenharmony_ci#define DMA_OCP_RESET 53 418c2ecf20Sopenharmony_ci#define EMAC_PTP_RESET 54 428c2ecf20Sopenharmony_ci/* 55 is empty*/ 438c2ecf20Sopenharmony_ci#define DMAIF0_RESET 56 448c2ecf20Sopenharmony_ci#define DMAIF1_RESET 57 458c2ecf20Sopenharmony_ci#define DMAIF2_RESET 58 468c2ecf20Sopenharmony_ci#define DMAIF3_RESET 59 478c2ecf20Sopenharmony_ci#define DMAIF4_RESET 60 488c2ecf20Sopenharmony_ci#define DMAIF5_RESET 61 498c2ecf20Sopenharmony_ci#define DMAIF6_RESET 62 508c2ecf20Sopenharmony_ci#define DMAIF7_RESET 63 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci/* PER1MODRST */ 538c2ecf20Sopenharmony_ci#define WATCHDOG0_RESET 64 548c2ecf20Sopenharmony_ci#define WATCHDOG1_RESET 65 558c2ecf20Sopenharmony_ci#define WATCHDOG2_RESET 66 568c2ecf20Sopenharmony_ci#define WATCHDOG3_RESET 67 578c2ecf20Sopenharmony_ci#define L4SYSTIMER0_RESET 68 588c2ecf20Sopenharmony_ci#define L4SYSTIMER1_RESET 69 598c2ecf20Sopenharmony_ci#define SPTIMER0_RESET 70 608c2ecf20Sopenharmony_ci#define SPTIMER1_RESET 71 618c2ecf20Sopenharmony_ci#define I2C0_RESET 72 628c2ecf20Sopenharmony_ci#define I2C1_RESET 73 638c2ecf20Sopenharmony_ci#define I2C2_RESET 74 648c2ecf20Sopenharmony_ci#define I2C3_RESET 75 658c2ecf20Sopenharmony_ci#define I2C4_RESET 76 668c2ecf20Sopenharmony_ci/* 77-79 is empty */ 678c2ecf20Sopenharmony_ci#define UART0_RESET 80 688c2ecf20Sopenharmony_ci#define UART1_RESET 81 698c2ecf20Sopenharmony_ci/* 82-87 is empty */ 708c2ecf20Sopenharmony_ci#define GPIO0_RESET 88 718c2ecf20Sopenharmony_ci#define GPIO1_RESET 89 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ci/* BRGMODRST */ 748c2ecf20Sopenharmony_ci#define SOC2FPGA_RESET 96 758c2ecf20Sopenharmony_ci#define LWHPS2FPGA_RESET 97 768c2ecf20Sopenharmony_ci#define FPGA2SOC_RESET 98 778c2ecf20Sopenharmony_ci#define F2SSDRAM0_RESET 99 788c2ecf20Sopenharmony_ci#define F2SSDRAM1_RESET 100 798c2ecf20Sopenharmony_ci#define F2SSDRAM2_RESET 101 808c2ecf20Sopenharmony_ci#define DDRSCH_RESET 102 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_ci/* COLDMODRST */ 838c2ecf20Sopenharmony_ci#define CPUPO0_RESET 160 848c2ecf20Sopenharmony_ci#define CPUPO1_RESET 161 858c2ecf20Sopenharmony_ci#define CPUPO2_RESET 162 868c2ecf20Sopenharmony_ci#define CPUPO3_RESET 163 878c2ecf20Sopenharmony_ci/* 164-167 is empty */ 888c2ecf20Sopenharmony_ci#define L2_RESET 168 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ci/* DBGMODRST */ 918c2ecf20Sopenharmony_ci#define DBG_RESET 224 928c2ecf20Sopenharmony_ci#define CSDAP_RESET 225 938c2ecf20Sopenharmony_ci 948c2ecf20Sopenharmony_ci/* TAPMODRST */ 958c2ecf20Sopenharmony_ci#define TAP_RESET 256 968c2ecf20Sopenharmony_ci 978c2ecf20Sopenharmony_ci#endif 98