18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 78c2ecf20Sopenharmony_ci#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci/* MPUMODRST */ 108c2ecf20Sopenharmony_ci#define CPU0_RESET 0 118c2ecf20Sopenharmony_ci#define CPU1_RESET 1 128c2ecf20Sopenharmony_ci#define WDS_RESET 2 138c2ecf20Sopenharmony_ci#define SCUPER_RESET 3 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci/* PER0MODRST */ 168c2ecf20Sopenharmony_ci#define EMAC0_RESET 32 178c2ecf20Sopenharmony_ci#define EMAC1_RESET 33 188c2ecf20Sopenharmony_ci#define EMAC2_RESET 34 198c2ecf20Sopenharmony_ci#define USB0_RESET 35 208c2ecf20Sopenharmony_ci#define USB1_RESET 36 218c2ecf20Sopenharmony_ci#define NAND_RESET 37 228c2ecf20Sopenharmony_ci#define QSPI_RESET 38 238c2ecf20Sopenharmony_ci#define SDMMC_RESET 39 248c2ecf20Sopenharmony_ci#define EMAC0_OCP_RESET 40 258c2ecf20Sopenharmony_ci#define EMAC1_OCP_RESET 41 268c2ecf20Sopenharmony_ci#define EMAC2_OCP_RESET 42 278c2ecf20Sopenharmony_ci#define USB0_OCP_RESET 43 288c2ecf20Sopenharmony_ci#define USB1_OCP_RESET 44 298c2ecf20Sopenharmony_ci#define NAND_OCP_RESET 45 308c2ecf20Sopenharmony_ci#define QSPI_OCP_RESET 46 318c2ecf20Sopenharmony_ci#define SDMMC_OCP_RESET 47 328c2ecf20Sopenharmony_ci#define DMA_RESET 48 338c2ecf20Sopenharmony_ci#define SPIM0_RESET 49 348c2ecf20Sopenharmony_ci#define SPIM1_RESET 50 358c2ecf20Sopenharmony_ci#define SPIS0_RESET 51 368c2ecf20Sopenharmony_ci#define SPIS1_RESET 52 378c2ecf20Sopenharmony_ci#define DMA_OCP_RESET 53 388c2ecf20Sopenharmony_ci#define EMAC_PTP_RESET 54 398c2ecf20Sopenharmony_ci/* 55 is empty*/ 408c2ecf20Sopenharmony_ci#define DMAIF0_RESET 56 418c2ecf20Sopenharmony_ci#define DMAIF1_RESET 57 428c2ecf20Sopenharmony_ci#define DMAIF2_RESET 58 438c2ecf20Sopenharmony_ci#define DMAIF3_RESET 59 448c2ecf20Sopenharmony_ci#define DMAIF4_RESET 60 458c2ecf20Sopenharmony_ci#define DMAIF5_RESET 61 468c2ecf20Sopenharmony_ci#define DMAIF6_RESET 62 478c2ecf20Sopenharmony_ci#define DMAIF7_RESET 63 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci/* PER1MODRST */ 508c2ecf20Sopenharmony_ci#define L4WD0_RESET 64 518c2ecf20Sopenharmony_ci#define L4WD1_RESET 65 528c2ecf20Sopenharmony_ci#define L4SYSTIMER0_RESET 66 538c2ecf20Sopenharmony_ci#define L4SYSTIMER1_RESET 67 548c2ecf20Sopenharmony_ci#define SPTIMER0_RESET 68 558c2ecf20Sopenharmony_ci#define SPTIMER1_RESET 69 568c2ecf20Sopenharmony_ci/* 70-71 is reserved */ 578c2ecf20Sopenharmony_ci#define I2C0_RESET 72 588c2ecf20Sopenharmony_ci#define I2C1_RESET 73 598c2ecf20Sopenharmony_ci#define I2C2_RESET 74 608c2ecf20Sopenharmony_ci#define I2C3_RESET 75 618c2ecf20Sopenharmony_ci#define I2C4_RESET 76 628c2ecf20Sopenharmony_ci/* 77-79 is reserved */ 638c2ecf20Sopenharmony_ci#define UART0_RESET 80 648c2ecf20Sopenharmony_ci#define UART1_RESET 81 658c2ecf20Sopenharmony_ci/* 82-87 is reserved */ 668c2ecf20Sopenharmony_ci#define GPIO0_RESET 88 678c2ecf20Sopenharmony_ci#define GPIO1_RESET 89 688c2ecf20Sopenharmony_ci#define GPIO2_RESET 90 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci/* BRGMODRST */ 718c2ecf20Sopenharmony_ci#define HPS2FPGA_RESET 96 728c2ecf20Sopenharmony_ci#define LWHPS2FPGA_RESET 97 738c2ecf20Sopenharmony_ci#define FPGA2HPS_RESET 98 748c2ecf20Sopenharmony_ci#define F2SSDRAM0_RESET 99 758c2ecf20Sopenharmony_ci#define F2SSDRAM1_RESET 100 768c2ecf20Sopenharmony_ci#define F2SSDRAM2_RESET 101 778c2ecf20Sopenharmony_ci#define DDRSCH_RESET 102 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci/* SYSMODRST*/ 808c2ecf20Sopenharmony_ci#define ROM_RESET 128 818c2ecf20Sopenharmony_ci#define OCRAM_RESET 129 828c2ecf20Sopenharmony_ci/* 130 is reserved */ 838c2ecf20Sopenharmony_ci#define FPGAMGR_RESET 131 848c2ecf20Sopenharmony_ci#define S2F_RESET 132 858c2ecf20Sopenharmony_ci#define SYSDBG_RESET 133 868c2ecf20Sopenharmony_ci#define OCRAM_OCP_RESET 134 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_ci/* COLDMODRST */ 898c2ecf20Sopenharmony_ci#define CLKMGRCOLD_RESET 160 908c2ecf20Sopenharmony_ci/* 161-162 is reserved */ 918c2ecf20Sopenharmony_ci#define S2FCOLD_RESET 163 928c2ecf20Sopenharmony_ci#define TIMESTAMPCOLD_RESET 164 938c2ecf20Sopenharmony_ci#define TAPCOLD_RESET 165 948c2ecf20Sopenharmony_ci#define HMCCOLD_RESET 166 958c2ecf20Sopenharmony_ci#define IOMGRCOLD_RESET 167 968c2ecf20Sopenharmony_ci 978c2ecf20Sopenharmony_ci/* NRSTMODRST */ 988c2ecf20Sopenharmony_ci#define NRSTPINOE_RESET 192 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci/* DBGMODRST */ 1018c2ecf20Sopenharmony_ci#define DBG_RESET 224 1028c2ecf20Sopenharmony_ci#endif 103