18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
48c2ecf20Sopenharmony_ci */
58c2ecf20Sopenharmony_ci
68c2ecf20Sopenharmony_ci#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
78c2ecf20Sopenharmony_ci#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ci/* MPUMODRST */
108c2ecf20Sopenharmony_ci#define CPU0_RESET		0
118c2ecf20Sopenharmony_ci#define CPU1_RESET		1
128c2ecf20Sopenharmony_ci#define WDS_RESET		2
138c2ecf20Sopenharmony_ci#define SCUPER_RESET		3
148c2ecf20Sopenharmony_ci#define L2_RESET		4
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci/* PERMODRST */
178c2ecf20Sopenharmony_ci#define EMAC0_RESET		32
188c2ecf20Sopenharmony_ci#define EMAC1_RESET		33
198c2ecf20Sopenharmony_ci#define USB0_RESET		34
208c2ecf20Sopenharmony_ci#define USB1_RESET		35
218c2ecf20Sopenharmony_ci#define NAND_RESET		36
228c2ecf20Sopenharmony_ci#define QSPI_RESET		37
238c2ecf20Sopenharmony_ci#define L4WD0_RESET		38
248c2ecf20Sopenharmony_ci#define L4WD1_RESET		39
258c2ecf20Sopenharmony_ci#define OSC1TIMER0_RESET	40
268c2ecf20Sopenharmony_ci#define OSC1TIMER1_RESET	41
278c2ecf20Sopenharmony_ci#define SPTIMER0_RESET		42
288c2ecf20Sopenharmony_ci#define SPTIMER1_RESET		43
298c2ecf20Sopenharmony_ci#define I2C0_RESET		44
308c2ecf20Sopenharmony_ci#define I2C1_RESET		45
318c2ecf20Sopenharmony_ci#define I2C2_RESET		46
328c2ecf20Sopenharmony_ci#define I2C3_RESET		47
338c2ecf20Sopenharmony_ci#define UART0_RESET		48
348c2ecf20Sopenharmony_ci#define UART1_RESET		49
358c2ecf20Sopenharmony_ci#define SPIM0_RESET		50
368c2ecf20Sopenharmony_ci#define SPIM1_RESET		51
378c2ecf20Sopenharmony_ci#define SPIS0_RESET		52
388c2ecf20Sopenharmony_ci#define SPIS1_RESET		53
398c2ecf20Sopenharmony_ci#define SDMMC_RESET		54
408c2ecf20Sopenharmony_ci#define CAN0_RESET		55
418c2ecf20Sopenharmony_ci#define CAN1_RESET		56
428c2ecf20Sopenharmony_ci#define GPIO0_RESET		57
438c2ecf20Sopenharmony_ci#define GPIO1_RESET		58
448c2ecf20Sopenharmony_ci#define GPIO2_RESET		59
458c2ecf20Sopenharmony_ci#define DMA_RESET		60
468c2ecf20Sopenharmony_ci#define SDR_RESET		61
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci/* PER2MODRST */
498c2ecf20Sopenharmony_ci#define DMAIF0_RESET		64
508c2ecf20Sopenharmony_ci#define DMAIF1_RESET		65
518c2ecf20Sopenharmony_ci#define DMAIF2_RESET		66
528c2ecf20Sopenharmony_ci#define DMAIF3_RESET		67
538c2ecf20Sopenharmony_ci#define DMAIF4_RESET		68
548c2ecf20Sopenharmony_ci#define DMAIF5_RESET		69
558c2ecf20Sopenharmony_ci#define DMAIF6_RESET		70
568c2ecf20Sopenharmony_ci#define DMAIF7_RESET		71
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci/* BRGMODRST */
598c2ecf20Sopenharmony_ci#define HPS2FPGA_RESET		96
608c2ecf20Sopenharmony_ci#define LWHPS2FPGA_RESET	97
618c2ecf20Sopenharmony_ci#define FPGA2HPS_RESET		98
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ci/* MISCMODRST*/
648c2ecf20Sopenharmony_ci#define ROM_RESET		128
658c2ecf20Sopenharmony_ci#define OCRAM_RESET		129
668c2ecf20Sopenharmony_ci#define SYSMGR_RESET		130
678c2ecf20Sopenharmony_ci#define SYSMGRCOLD_RESET	131
688c2ecf20Sopenharmony_ci#define FPGAMGR_RESET		132
698c2ecf20Sopenharmony_ci#define ACPIDMAP_RESET		133
708c2ecf20Sopenharmony_ci#define S2F_RESET		134
718c2ecf20Sopenharmony_ci#define S2FCOLD_RESET		135
728c2ecf20Sopenharmony_ci#define NRSTPIN_RESET		136
738c2ecf20Sopenharmony_ci#define TIMESTAMPCOLD_RESET	137
748c2ecf20Sopenharmony_ci#define CLKMGRCOLD_RESET	138
758c2ecf20Sopenharmony_ci#define SCANMGR_RESET		139
768c2ecf20Sopenharmony_ci#define FRZCTRLCOLD_RESET	140
778c2ecf20Sopenharmony_ci#define SYSDBG_RESET		141
788c2ecf20Sopenharmony_ci#define DBG_RESET		142
798c2ecf20Sopenharmony_ci#define TAPCOLD_RESET		143
808c2ecf20Sopenharmony_ci#define SDRCOLD_RESET		144
818c2ecf20Sopenharmony_ci
828c2ecf20Sopenharmony_ci#endif
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