18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Device Tree constants for the Texas Instruments DP83867 PHY 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Author: Dan Murphy <dmurphy@ti.com> 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Copyright: (C) 2015 Texas Instruments, Inc. 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#ifndef _DT_BINDINGS_TI_DP83867_H 118c2ecf20Sopenharmony_ci#define _DT_BINDINGS_TI_DP83867_H 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci/* PHY CTRL bits */ 148c2ecf20Sopenharmony_ci#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 158c2ecf20Sopenharmony_ci#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 168c2ecf20Sopenharmony_ci#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 178c2ecf20Sopenharmony_ci#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci/* RGMIIDCTL internal delay for rx and tx */ 208c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_250_PS 0x0 218c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_500_PS 0x1 228c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_750_PS 0x2 238c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_1_NS 0x3 248c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_1_25_NS 0x4 258c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_1_50_NS 0x5 268c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_1_75_NS 0x6 278c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_2_00_NS 0x7 288c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_2_25_NS 0x8 298c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_2_50_NS 0x9 308c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_2_75_NS 0xa 318c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_3_00_NS 0xb 328c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_3_25_NS 0xc 338c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_3_50_NS 0xd 348c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_3_75_NS 0xe 358c2ecf20Sopenharmony_ci#define DP83867_RGMIIDCTL_4_00_NS 0xf 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci/* IO_MUX_CFG - Clock output selection */ 388c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 398c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 408c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 418c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 428c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 438c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 448c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 458c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 468c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 478c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 488c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 498c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 508c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_REF_CLK 0xC 518c2ecf20Sopenharmony_ci/* Special flag to indicate clock should be off */ 528c2ecf20Sopenharmony_ci#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF 538c2ecf20Sopenharmony_ci#endif 54