18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci/dts-v1/; 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#include "k3-j7200.dtsi" 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci/ { 118c2ecf20Sopenharmony_ci memory@80000000 { 128c2ecf20Sopenharmony_ci device_type = "memory"; 138c2ecf20Sopenharmony_ci /* 4G RAM */ 148c2ecf20Sopenharmony_ci reg = <0x00 0x80000000 0x00 0x80000000>, 158c2ecf20Sopenharmony_ci <0x08 0x80000000 0x00 0x80000000>; 168c2ecf20Sopenharmony_ci }; 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci reserved_memory: reserved-memory { 198c2ecf20Sopenharmony_ci #address-cells = <2>; 208c2ecf20Sopenharmony_ci #size-cells = <2>; 218c2ecf20Sopenharmony_ci ranges; 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci secure_ddr: optee@9e800000 { 248c2ecf20Sopenharmony_ci reg = <0x00 0x9e800000 0x00 0x01800000>; 258c2ecf20Sopenharmony_ci alignment = <0x1000>; 268c2ecf20Sopenharmony_ci no-map; 278c2ecf20Sopenharmony_ci }; 288c2ecf20Sopenharmony_ci }; 298c2ecf20Sopenharmony_ci}; 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci&wkup_pmx0 { 328c2ecf20Sopenharmony_ci mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { 338c2ecf20Sopenharmony_ci pinctrl-single,pins = < 348c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 358c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 368c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 378c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 388c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 398c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 408c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 418c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 428c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 438c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 448c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 458c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 468c2ecf20Sopenharmony_ci J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 478c2ecf20Sopenharmony_ci >; 488c2ecf20Sopenharmony_ci }; 498c2ecf20Sopenharmony_ci}; 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci&hbmc { 528c2ecf20Sopenharmony_ci /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 538c2ecf20Sopenharmony_ci * appropriate node based on board detection 548c2ecf20Sopenharmony_ci */ 558c2ecf20Sopenharmony_ci status = "disabled"; 568c2ecf20Sopenharmony_ci pinctrl-names = "default"; 578c2ecf20Sopenharmony_ci pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 588c2ecf20Sopenharmony_ci ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 598c2ecf20Sopenharmony_ci <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci flash@0,0 { 628c2ecf20Sopenharmony_ci compatible = "cypress,hyperflash", "cfi-flash"; 638c2ecf20Sopenharmony_ci reg = <0x00 0x00 0x4000000>; 648c2ecf20Sopenharmony_ci }; 658c2ecf20Sopenharmony_ci}; 66