18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (C) 2019 Marvell International Ltd.
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Device tree for the CN9132-DB board.
68c2ecf20Sopenharmony_ci */
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci#include "cn9131-db.dts"
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ci/ {
118c2ecf20Sopenharmony_ci	model = "Marvell Armada CN9132-DB";
128c2ecf20Sopenharmony_ci	compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
138c2ecf20Sopenharmony_ci		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci	aliases {
168c2ecf20Sopenharmony_ci		gpio5 = &cp2_gpio1;
178c2ecf20Sopenharmony_ci		gpio6 = &cp2_gpio2;
188c2ecf20Sopenharmony_ci		ethernet5 = &cp2_eth0;
198c2ecf20Sopenharmony_ci	};
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci	cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
228c2ecf20Sopenharmony_ci		compatible = "regulator-fixed";
238c2ecf20Sopenharmony_ci		regulator-name = "cp2-xhci0-vbus";
248c2ecf20Sopenharmony_ci		regulator-min-microvolt = <5000000>;
258c2ecf20Sopenharmony_ci		regulator-max-microvolt = <5000000>;
268c2ecf20Sopenharmony_ci		enable-active-high;
278c2ecf20Sopenharmony_ci		gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
288c2ecf20Sopenharmony_ci	};
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci	cp2_usb3_0_phy0: cp2_usb3_phy0 {
318c2ecf20Sopenharmony_ci		compatible = "usb-nop-xceiv";
328c2ecf20Sopenharmony_ci		vcc-supply = <&cp2_reg_usb3_vbus0>;
338c2ecf20Sopenharmony_ci	};
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci	cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
368c2ecf20Sopenharmony_ci		compatible = "regulator-fixed";
378c2ecf20Sopenharmony_ci		regulator-name = "cp2-xhci1-vbus";
388c2ecf20Sopenharmony_ci		regulator-min-microvolt = <5000000>;
398c2ecf20Sopenharmony_ci		regulator-max-microvolt = <5000000>;
408c2ecf20Sopenharmony_ci		enable-active-high;
418c2ecf20Sopenharmony_ci		gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
428c2ecf20Sopenharmony_ci	};
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci	cp2_usb3_0_phy1: cp2_usb3_phy1 {
458c2ecf20Sopenharmony_ci		compatible = "usb-nop-xceiv";
468c2ecf20Sopenharmony_ci		vcc-supply = <&cp2_reg_usb3_vbus1>;
478c2ecf20Sopenharmony_ci	};
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci	cp2_reg_sd_vccq: cp2_sd_vccq@0 {
508c2ecf20Sopenharmony_ci		compatible = "regulator-gpio";
518c2ecf20Sopenharmony_ci		regulator-name = "cp2_sd_vcc";
528c2ecf20Sopenharmony_ci		regulator-min-microvolt = <1800000>;
538c2ecf20Sopenharmony_ci		regulator-max-microvolt = <3300000>;
548c2ecf20Sopenharmony_ci		gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
558c2ecf20Sopenharmony_ci		states = <1800000 0x1 3300000 0x0>;
568c2ecf20Sopenharmony_ci	};
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci	cp2_sfp_eth0: sfp-eth0 {
598c2ecf20Sopenharmony_ci		compatible = "sff,sfp";
608c2ecf20Sopenharmony_ci		i2c-bus = <&cp2_sfpp0_i2c>;
618c2ecf20Sopenharmony_ci		los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
628c2ecf20Sopenharmony_ci		mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
638c2ecf20Sopenharmony_ci		tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
648c2ecf20Sopenharmony_ci		tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
658c2ecf20Sopenharmony_ci		/*
668c2ecf20Sopenharmony_ci		 * SFP cages are unconnected on early PCBs because of an the I2C
678c2ecf20Sopenharmony_ci		 * lanes not being connected. Prevent the port for being
688c2ecf20Sopenharmony_ci		 * unusable by disabling the SFP node.
698c2ecf20Sopenharmony_ci		 */
708c2ecf20Sopenharmony_ci		status = "disabled";
718c2ecf20Sopenharmony_ci	};
728c2ecf20Sopenharmony_ci};
738c2ecf20Sopenharmony_ci
748c2ecf20Sopenharmony_ci/*
758c2ecf20Sopenharmony_ci * Instantiate the second slave CP115
768c2ecf20Sopenharmony_ci */
778c2ecf20Sopenharmony_ci
788c2ecf20Sopenharmony_ci#define CP11X_NAME		cp2
798c2ecf20Sopenharmony_ci#define CP11X_BASE		f6000000
808c2ecf20Sopenharmony_ci#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
818c2ecf20Sopenharmony_ci#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
828c2ecf20Sopenharmony_ci#define CP11X_PCIE0_BASE	f6600000
838c2ecf20Sopenharmony_ci#define CP11X_PCIE1_BASE	f6620000
848c2ecf20Sopenharmony_ci#define CP11X_PCIE2_BASE	f6640000
858c2ecf20Sopenharmony_ci
868c2ecf20Sopenharmony_ci#include "armada-cp115.dtsi"
878c2ecf20Sopenharmony_ci
888c2ecf20Sopenharmony_ci#undef CP11X_NAME
898c2ecf20Sopenharmony_ci#undef CP11X_BASE
908c2ecf20Sopenharmony_ci#undef CP11X_PCIEx_MEM_BASE
918c2ecf20Sopenharmony_ci#undef CP11X_PCIEx_MEM_SIZE
928c2ecf20Sopenharmony_ci#undef CP11X_PCIE0_BASE
938c2ecf20Sopenharmony_ci#undef CP11X_PCIE1_BASE
948c2ecf20Sopenharmony_ci#undef CP11X_PCIE2_BASE
958c2ecf20Sopenharmony_ci
968c2ecf20Sopenharmony_ci&cp2_crypto {
978c2ecf20Sopenharmony_ci	status = "disabled";
988c2ecf20Sopenharmony_ci};
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_ci&cp2_ethernet {
1018c2ecf20Sopenharmony_ci	status = "okay";
1028c2ecf20Sopenharmony_ci};
1038c2ecf20Sopenharmony_ci
1048c2ecf20Sopenharmony_ci/* SLM-1521-V2, CON9 */
1058c2ecf20Sopenharmony_ci&cp2_eth0 {
1068c2ecf20Sopenharmony_ci	status = "disabled";
1078c2ecf20Sopenharmony_ci	phy-mode = "10gbase-kr";
1088c2ecf20Sopenharmony_ci	/* Generic PHY, providing serdes lanes */
1098c2ecf20Sopenharmony_ci	phys = <&cp2_comphy4 0>;
1108c2ecf20Sopenharmony_ci	managed = "in-band-status";
1118c2ecf20Sopenharmony_ci	sfp = <&cp2_sfp_eth0>;
1128c2ecf20Sopenharmony_ci};
1138c2ecf20Sopenharmony_ci
1148c2ecf20Sopenharmony_ci&cp2_gpio1 {
1158c2ecf20Sopenharmony_ci	status = "okay";
1168c2ecf20Sopenharmony_ci};
1178c2ecf20Sopenharmony_ci
1188c2ecf20Sopenharmony_ci&cp2_gpio2 {
1198c2ecf20Sopenharmony_ci	status = "okay";
1208c2ecf20Sopenharmony_ci};
1218c2ecf20Sopenharmony_ci
1228c2ecf20Sopenharmony_ci&cp2_i2c0 {
1238c2ecf20Sopenharmony_ci	clock-frequency = <100000>;
1248c2ecf20Sopenharmony_ci
1258c2ecf20Sopenharmony_ci	/* SLM-1521-V2 - U3 */
1268c2ecf20Sopenharmony_ci	i2c-mux@72 {
1278c2ecf20Sopenharmony_ci		compatible = "nxp,pca9544";
1288c2ecf20Sopenharmony_ci		#address-cells = <1>;
1298c2ecf20Sopenharmony_ci		#size-cells = <0>;
1308c2ecf20Sopenharmony_ci		reg = <0x72>;
1318c2ecf20Sopenharmony_ci		cp2_sfpp0_i2c: i2c@0 {
1328c2ecf20Sopenharmony_ci			#address-cells = <1>;
1338c2ecf20Sopenharmony_ci			#size-cells = <0>;
1348c2ecf20Sopenharmony_ci			reg = <0>;
1358c2ecf20Sopenharmony_ci		};
1368c2ecf20Sopenharmony_ci
1378c2ecf20Sopenharmony_ci		i2c@1 {
1388c2ecf20Sopenharmony_ci			#address-cells = <1>;
1398c2ecf20Sopenharmony_ci			#size-cells = <0>;
1408c2ecf20Sopenharmony_ci			reg = <1>;
1418c2ecf20Sopenharmony_ci			/* U12 */
1428c2ecf20Sopenharmony_ci			cp2_module_expander1: pca9555@21 {
1438c2ecf20Sopenharmony_ci				compatible = "nxp,pca9555";
1448c2ecf20Sopenharmony_ci				pinctrl-names = "default";
1458c2ecf20Sopenharmony_ci				gpio-controller;
1468c2ecf20Sopenharmony_ci				#gpio-cells = <2>;
1478c2ecf20Sopenharmony_ci				reg = <0x21>;
1488c2ecf20Sopenharmony_ci			};
1498c2ecf20Sopenharmony_ci		};
1508c2ecf20Sopenharmony_ci	};
1518c2ecf20Sopenharmony_ci};
1528c2ecf20Sopenharmony_ci
1538c2ecf20Sopenharmony_ci/* SLM-1521-V2, CON6 */
1548c2ecf20Sopenharmony_ci&cp2_pcie0 {
1558c2ecf20Sopenharmony_ci	status = "okay";
1568c2ecf20Sopenharmony_ci	num-lanes = <2>;
1578c2ecf20Sopenharmony_ci	num-viewport = <8>;
1588c2ecf20Sopenharmony_ci	/* Generic PHY, providing serdes lanes */
1598c2ecf20Sopenharmony_ci	phys = <&cp2_comphy0 0
1608c2ecf20Sopenharmony_ci		&cp2_comphy1 0>;
1618c2ecf20Sopenharmony_ci};
1628c2ecf20Sopenharmony_ci
1638c2ecf20Sopenharmony_ci/* SLM-1521-V2, CON8 */
1648c2ecf20Sopenharmony_ci&cp2_pcie2 {
1658c2ecf20Sopenharmony_ci	status = "okay";
1668c2ecf20Sopenharmony_ci	num-lanes = <1>;
1678c2ecf20Sopenharmony_ci	num-viewport = <8>;
1688c2ecf20Sopenharmony_ci	/* Generic PHY, providing serdes lanes */
1698c2ecf20Sopenharmony_ci	phys = <&cp2_comphy5 2>;
1708c2ecf20Sopenharmony_ci};
1718c2ecf20Sopenharmony_ci
1728c2ecf20Sopenharmony_ci&cp2_sata0 {
1738c2ecf20Sopenharmony_ci	status = "okay";
1748c2ecf20Sopenharmony_ci
1758c2ecf20Sopenharmony_ci	/* SLM-1521-V2, CON4 */
1768c2ecf20Sopenharmony_ci	sata-port@0 {
1778c2ecf20Sopenharmony_ci		/* Generic PHY, providing serdes lanes */
1788c2ecf20Sopenharmony_ci		phys = <&cp2_comphy2 0>;
1798c2ecf20Sopenharmony_ci	};
1808c2ecf20Sopenharmony_ci};
1818c2ecf20Sopenharmony_ci
1828c2ecf20Sopenharmony_ci/* CON 2 on SLM-1683 - microSD */
1838c2ecf20Sopenharmony_ci&cp2_sdhci0 {
1848c2ecf20Sopenharmony_ci	status = "okay";
1858c2ecf20Sopenharmony_ci	pinctrl-names = "default";
1868c2ecf20Sopenharmony_ci	pinctrl-0 = <&cp2_sdhci_pins>;
1878c2ecf20Sopenharmony_ci	bus-width = <4>;
1888c2ecf20Sopenharmony_ci	cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
1898c2ecf20Sopenharmony_ci	vqmmc-supply = <&cp2_reg_sd_vccq>;
1908c2ecf20Sopenharmony_ci};
1918c2ecf20Sopenharmony_ci
1928c2ecf20Sopenharmony_ci&cp2_syscon0 {
1938c2ecf20Sopenharmony_ci	cp2_pinctrl: pinctrl {
1948c2ecf20Sopenharmony_ci		compatible = "marvell,cp115-standalone-pinctrl";
1958c2ecf20Sopenharmony_ci
1968c2ecf20Sopenharmony_ci		cp2_i2c0_pins: cp2-i2c-pins-0 {
1978c2ecf20Sopenharmony_ci			marvell,pins = "mpp37", "mpp38";
1988c2ecf20Sopenharmony_ci			marvell,function = "i2c0";
1998c2ecf20Sopenharmony_ci		};
2008c2ecf20Sopenharmony_ci		cp2_sdhci_pins: cp2-sdhi-pins-0 {
2018c2ecf20Sopenharmony_ci			marvell,pins = "mpp56", "mpp57", "mpp58",
2028c2ecf20Sopenharmony_ci				       "mpp59", "mpp60", "mpp61";
2038c2ecf20Sopenharmony_ci			marvell,function = "sdio";
2048c2ecf20Sopenharmony_ci		};
2058c2ecf20Sopenharmony_ci	};
2068c2ecf20Sopenharmony_ci};
2078c2ecf20Sopenharmony_ci
2088c2ecf20Sopenharmony_ci&cp2_usb3_0 {
2098c2ecf20Sopenharmony_ci	status = "okay";
2108c2ecf20Sopenharmony_ci	usb-phy = <&cp2_usb3_0_phy0>;
2118c2ecf20Sopenharmony_ci	phy-names = "usb";
2128c2ecf20Sopenharmony_ci};
2138c2ecf20Sopenharmony_ci
2148c2ecf20Sopenharmony_ci/* SLM-1521-V2, CON11 */
2158c2ecf20Sopenharmony_ci&cp2_usb3_1 {
2168c2ecf20Sopenharmony_ci	status = "okay";
2178c2ecf20Sopenharmony_ci	usb-phy = <&cp2_usb3_0_phy1>;
2188c2ecf20Sopenharmony_ci	phy-names = "usb";
2198c2ecf20Sopenharmony_ci	/* Generic PHY, providing serdes lanes */
2208c2ecf20Sopenharmony_ci	phys = <&cp2_comphy3 1>;
2218c2ecf20Sopenharmony_ci};
222