18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2019 Marvell International Ltd. 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Device tree for the CN9131-DB board. 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#include "cn9130-db.dts" 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci/ { 118c2ecf20Sopenharmony_ci model = "Marvell Armada CN9131-DB"; 128c2ecf20Sopenharmony_ci compatible = "marvell,cn9131", "marvell,cn9130", 138c2ecf20Sopenharmony_ci "marvell,armada-ap807-quad", "marvell,armada-ap807"; 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci aliases { 168c2ecf20Sopenharmony_ci gpio3 = &cp1_gpio1; 178c2ecf20Sopenharmony_ci gpio4 = &cp1_gpio2; 188c2ecf20Sopenharmony_ci ethernet3 = &cp1_eth0; 198c2ecf20Sopenharmony_ci ethernet4 = &cp1_eth1; 208c2ecf20Sopenharmony_ci }; 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { 238c2ecf20Sopenharmony_ci compatible = "regulator-fixed"; 248c2ecf20Sopenharmony_ci pinctrl-names = "default"; 258c2ecf20Sopenharmony_ci pinctrl-0 = <&cp1_xhci0_vbus_pins>; 268c2ecf20Sopenharmony_ci regulator-name = "cp1-xhci0-vbus"; 278c2ecf20Sopenharmony_ci regulator-min-microvolt = <5000000>; 288c2ecf20Sopenharmony_ci regulator-max-microvolt = <5000000>; 298c2ecf20Sopenharmony_ci enable-active-high; 308c2ecf20Sopenharmony_ci gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; 318c2ecf20Sopenharmony_ci }; 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci cp1_usb3_0_phy0: cp1_usb3_phy0 { 348c2ecf20Sopenharmony_ci compatible = "usb-nop-xceiv"; 358c2ecf20Sopenharmony_ci vcc-supply = <&cp1_reg_usb3_vbus0>; 368c2ecf20Sopenharmony_ci }; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci cp1_sfp_eth1: sfp-eth1 { 398c2ecf20Sopenharmony_ci compatible = "sff,sfp"; 408c2ecf20Sopenharmony_ci i2c-bus = <&cp1_i2c0>; 418c2ecf20Sopenharmony_ci los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; 428c2ecf20Sopenharmony_ci mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; 438c2ecf20Sopenharmony_ci tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; 448c2ecf20Sopenharmony_ci tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; 458c2ecf20Sopenharmony_ci pinctrl-names = "default"; 468c2ecf20Sopenharmony_ci pinctrl-0 = <&cp1_sfp_pins>; 478c2ecf20Sopenharmony_ci /* 488c2ecf20Sopenharmony_ci * SFP cages are unconnected on early PCBs because of an the I2C 498c2ecf20Sopenharmony_ci * lanes not being connected. Prevent the port for being 508c2ecf20Sopenharmony_ci * unusable by disabling the SFP node. 518c2ecf20Sopenharmony_ci */ 528c2ecf20Sopenharmony_ci status = "disabled"; 538c2ecf20Sopenharmony_ci }; 548c2ecf20Sopenharmony_ci}; 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci/* 578c2ecf20Sopenharmony_ci * Instantiate the first slave CP115 588c2ecf20Sopenharmony_ci */ 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci#define CP11X_NAME cp1 618c2ecf20Sopenharmony_ci#define CP11X_BASE f4000000 628c2ecf20Sopenharmony_ci#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) 638c2ecf20Sopenharmony_ci#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 648c2ecf20Sopenharmony_ci#define CP11X_PCIE0_BASE f4600000 658c2ecf20Sopenharmony_ci#define CP11X_PCIE1_BASE f4620000 668c2ecf20Sopenharmony_ci#define CP11X_PCIE2_BASE f4640000 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci#include "armada-cp115.dtsi" 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci#undef CP11X_NAME 718c2ecf20Sopenharmony_ci#undef CP11X_BASE 728c2ecf20Sopenharmony_ci#undef CP11X_PCIEx_MEM_BASE 738c2ecf20Sopenharmony_ci#undef CP11X_PCIEx_MEM_SIZE 748c2ecf20Sopenharmony_ci#undef CP11X_PCIE0_BASE 758c2ecf20Sopenharmony_ci#undef CP11X_PCIE1_BASE 768c2ecf20Sopenharmony_ci#undef CP11X_PCIE2_BASE 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci&cp1_crypto { 798c2ecf20Sopenharmony_ci status = "disabled"; 808c2ecf20Sopenharmony_ci}; 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_ci&cp1_ethernet { 838c2ecf20Sopenharmony_ci status = "okay"; 848c2ecf20Sopenharmony_ci}; 858c2ecf20Sopenharmony_ci 868c2ecf20Sopenharmony_ci/* CON50 */ 878c2ecf20Sopenharmony_ci&cp1_eth0 { 888c2ecf20Sopenharmony_ci status = "disabled"; 898c2ecf20Sopenharmony_ci phy-mode = "10gbase-kr"; 908c2ecf20Sopenharmony_ci /* Generic PHY, providing serdes lanes */ 918c2ecf20Sopenharmony_ci phys = <&cp1_comphy4 0>; 928c2ecf20Sopenharmony_ci managed = "in-band-status"; 938c2ecf20Sopenharmony_ci sfp = <&cp1_sfp_eth1>; 948c2ecf20Sopenharmony_ci}; 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ci&cp1_gpio1 { 978c2ecf20Sopenharmony_ci status = "okay"; 988c2ecf20Sopenharmony_ci}; 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci&cp1_gpio2 { 1018c2ecf20Sopenharmony_ci status = "okay"; 1028c2ecf20Sopenharmony_ci}; 1038c2ecf20Sopenharmony_ci 1048c2ecf20Sopenharmony_ci&cp1_i2c0 { 1058c2ecf20Sopenharmony_ci status = "okay"; 1068c2ecf20Sopenharmony_ci pinctrl-names = "default"; 1078c2ecf20Sopenharmony_ci pinctrl-0 = <&cp1_i2c0_pins>; 1088c2ecf20Sopenharmony_ci clock-frequency = <100000>; 1098c2ecf20Sopenharmony_ci}; 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci/* CON40 */ 1128c2ecf20Sopenharmony_ci&cp1_pcie0 { 1138c2ecf20Sopenharmony_ci pinctrl-names = "default"; 1148c2ecf20Sopenharmony_ci pinctrl-0 = <&cp1_pcie_reset_pins>; 1158c2ecf20Sopenharmony_ci num-lanes = <2>; 1168c2ecf20Sopenharmony_ci num-viewport = <8>; 1178c2ecf20Sopenharmony_ci marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>; 1188c2ecf20Sopenharmony_ci status = "okay"; 1198c2ecf20Sopenharmony_ci /* Generic PHY, providing serdes lanes */ 1208c2ecf20Sopenharmony_ci phys = <&cp1_comphy0 0 1218c2ecf20Sopenharmony_ci &cp1_comphy1 0>; 1228c2ecf20Sopenharmony_ci}; 1238c2ecf20Sopenharmony_ci 1248c2ecf20Sopenharmony_ci&cp1_sata0 { 1258c2ecf20Sopenharmony_ci status = "okay"; 1268c2ecf20Sopenharmony_ci 1278c2ecf20Sopenharmony_ci /* CON32 */ 1288c2ecf20Sopenharmony_ci sata-port@1 { 1298c2ecf20Sopenharmony_ci /* Generic PHY, providing serdes lanes */ 1308c2ecf20Sopenharmony_ci phys = <&cp1_comphy5 1>; 1318c2ecf20Sopenharmony_ci }; 1328c2ecf20Sopenharmony_ci}; 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ci/* U24 */ 1358c2ecf20Sopenharmony_ci&cp1_spi1 { 1368c2ecf20Sopenharmony_ci status = "okay"; 1378c2ecf20Sopenharmony_ci pinctrl-names = "default"; 1388c2ecf20Sopenharmony_ci pinctrl-0 = <&cp1_spi0_pins>; 1398c2ecf20Sopenharmony_ci reg = <0x700680 0x50>; 1408c2ecf20Sopenharmony_ci 1418c2ecf20Sopenharmony_ci spi-flash@0 { 1428c2ecf20Sopenharmony_ci #address-cells = <0x1>; 1438c2ecf20Sopenharmony_ci #size-cells = <0x1>; 1448c2ecf20Sopenharmony_ci compatible = "jedec,spi-nor"; 1458c2ecf20Sopenharmony_ci reg = <0x0>; 1468c2ecf20Sopenharmony_ci /* On-board MUX does not allow higher frequencies */ 1478c2ecf20Sopenharmony_ci spi-max-frequency = <40000000>; 1488c2ecf20Sopenharmony_ci 1498c2ecf20Sopenharmony_ci partitions { 1508c2ecf20Sopenharmony_ci compatible = "fixed-partitions"; 1518c2ecf20Sopenharmony_ci #address-cells = <1>; 1528c2ecf20Sopenharmony_ci #size-cells = <1>; 1538c2ecf20Sopenharmony_ci 1548c2ecf20Sopenharmony_ci partition@0 { 1558c2ecf20Sopenharmony_ci label = "U-Boot-1"; 1568c2ecf20Sopenharmony_ci reg = <0x0 0x200000>; 1578c2ecf20Sopenharmony_ci }; 1588c2ecf20Sopenharmony_ci 1598c2ecf20Sopenharmony_ci partition@400000 { 1608c2ecf20Sopenharmony_ci label = "Filesystem-1"; 1618c2ecf20Sopenharmony_ci reg = <0x200000 0xe00000>; 1628c2ecf20Sopenharmony_ci }; 1638c2ecf20Sopenharmony_ci }; 1648c2ecf20Sopenharmony_ci }; 1658c2ecf20Sopenharmony_ci 1668c2ecf20Sopenharmony_ci}; 1678c2ecf20Sopenharmony_ci 1688c2ecf20Sopenharmony_ci&cp1_syscon0 { 1698c2ecf20Sopenharmony_ci cp1_pinctrl: pinctrl { 1708c2ecf20Sopenharmony_ci compatible = "marvell,cp115-standalone-pinctrl"; 1718c2ecf20Sopenharmony_ci 1728c2ecf20Sopenharmony_ci cp1_i2c0_pins: cp1-i2c-pins-0 { 1738c2ecf20Sopenharmony_ci marvell,pins = "mpp37", "mpp38"; 1748c2ecf20Sopenharmony_ci marvell,function = "i2c0"; 1758c2ecf20Sopenharmony_ci }; 1768c2ecf20Sopenharmony_ci cp1_spi0_pins: cp1-spi-pins-0 { 1778c2ecf20Sopenharmony_ci marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; 1788c2ecf20Sopenharmony_ci marvell,function = "spi1"; 1798c2ecf20Sopenharmony_ci }; 1808c2ecf20Sopenharmony_ci cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { 1818c2ecf20Sopenharmony_ci marvell,pins = "mpp3"; 1828c2ecf20Sopenharmony_ci marvell,function = "gpio"; 1838c2ecf20Sopenharmony_ci }; 1848c2ecf20Sopenharmony_ci cp1_sfp_pins: sfp-pins { 1858c2ecf20Sopenharmony_ci marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11"; 1868c2ecf20Sopenharmony_ci marvell,function = "gpio"; 1878c2ecf20Sopenharmony_ci }; 1888c2ecf20Sopenharmony_ci cp1_pcie_reset_pins: cp1-pcie-reset-pins { 1898c2ecf20Sopenharmony_ci marvell,pins = "mpp0"; 1908c2ecf20Sopenharmony_ci marvell,function = "gpio"; 1918c2ecf20Sopenharmony_ci }; 1928c2ecf20Sopenharmony_ci }; 1938c2ecf20Sopenharmony_ci}; 1948c2ecf20Sopenharmony_ci 1958c2ecf20Sopenharmony_ci/* CON58 */ 1968c2ecf20Sopenharmony_ci&cp1_usb3_1 { 1978c2ecf20Sopenharmony_ci status = "okay"; 1988c2ecf20Sopenharmony_ci usb-phy = <&cp1_usb3_0_phy0>; 1998c2ecf20Sopenharmony_ci /* Generic PHY, providing serdes lanes */ 2008c2ecf20Sopenharmony_ci phys = <&cp1_comphy3 1>; 2018c2ecf20Sopenharmony_ci phy-names = "usb"; 2028c2ecf20Sopenharmony_ci}; 203