18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Support for the w100 frame buffer. 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (c) 2004-2005 Richard Purdie 68c2ecf20Sopenharmony_ci * Copyright (c) 2005 Ian Molton 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#define W100_GPIO_PORT_A 0 108c2ecf20Sopenharmony_ci#define W100_GPIO_PORT_B 1 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#define CLK_SRC_XTAL 0 138c2ecf20Sopenharmony_ci#define CLK_SRC_PLL 1 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_cistruct w100fb_par; 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciunsigned long w100fb_gpio_read(int port); 188c2ecf20Sopenharmony_civoid w100fb_gpio_write(int port, unsigned long value); 198c2ecf20Sopenharmony_ciunsigned long w100fb_get_hsynclen(struct device *dev); 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci/* LCD Specific Routines and Config */ 228c2ecf20Sopenharmony_cistruct w100_tg_info { 238c2ecf20Sopenharmony_ci void (*change)(struct w100fb_par*); 248c2ecf20Sopenharmony_ci void (*suspend)(struct w100fb_par*); 258c2ecf20Sopenharmony_ci void (*resume)(struct w100fb_par*); 268c2ecf20Sopenharmony_ci}; 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci/* General Platform Specific w100 Register Values */ 298c2ecf20Sopenharmony_cistruct w100_gen_regs { 308c2ecf20Sopenharmony_ci unsigned long lcd_format; 318c2ecf20Sopenharmony_ci unsigned long lcdd_cntl1; 328c2ecf20Sopenharmony_ci unsigned long lcdd_cntl2; 338c2ecf20Sopenharmony_ci unsigned long genlcd_cntl1; 348c2ecf20Sopenharmony_ci unsigned long genlcd_cntl2; 358c2ecf20Sopenharmony_ci unsigned long genlcd_cntl3; 368c2ecf20Sopenharmony_ci}; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_cistruct w100_gpio_regs { 398c2ecf20Sopenharmony_ci unsigned long init_data1; 408c2ecf20Sopenharmony_ci unsigned long init_data2; 418c2ecf20Sopenharmony_ci unsigned long gpio_dir1; 428c2ecf20Sopenharmony_ci unsigned long gpio_oe1; 438c2ecf20Sopenharmony_ci unsigned long gpio_dir2; 448c2ecf20Sopenharmony_ci unsigned long gpio_oe2; 458c2ecf20Sopenharmony_ci}; 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci/* Optional External Memory Configuration */ 488c2ecf20Sopenharmony_cistruct w100_mem_info { 498c2ecf20Sopenharmony_ci unsigned long ext_cntl; 508c2ecf20Sopenharmony_ci unsigned long sdram_mode_reg; 518c2ecf20Sopenharmony_ci unsigned long ext_timing_cntl; 528c2ecf20Sopenharmony_ci unsigned long io_cntl; 538c2ecf20Sopenharmony_ci unsigned int size; 548c2ecf20Sopenharmony_ci}; 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_cistruct w100_bm_mem_info { 578c2ecf20Sopenharmony_ci unsigned long ext_mem_bw; 588c2ecf20Sopenharmony_ci unsigned long offset; 598c2ecf20Sopenharmony_ci unsigned long ext_timing_ctl; 608c2ecf20Sopenharmony_ci unsigned long ext_cntl; 618c2ecf20Sopenharmony_ci unsigned long mode_reg; 628c2ecf20Sopenharmony_ci unsigned long io_cntl; 638c2ecf20Sopenharmony_ci unsigned long config; 648c2ecf20Sopenharmony_ci}; 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci/* LCD Mode definition */ 678c2ecf20Sopenharmony_cistruct w100_mode { 688c2ecf20Sopenharmony_ci unsigned int xres; 698c2ecf20Sopenharmony_ci unsigned int yres; 708c2ecf20Sopenharmony_ci unsigned short left_margin; 718c2ecf20Sopenharmony_ci unsigned short right_margin; 728c2ecf20Sopenharmony_ci unsigned short upper_margin; 738c2ecf20Sopenharmony_ci unsigned short lower_margin; 748c2ecf20Sopenharmony_ci unsigned long crtc_ss; 758c2ecf20Sopenharmony_ci unsigned long crtc_ls; 768c2ecf20Sopenharmony_ci unsigned long crtc_gs; 778c2ecf20Sopenharmony_ci unsigned long crtc_vpos_gs; 788c2ecf20Sopenharmony_ci unsigned long crtc_rev; 798c2ecf20Sopenharmony_ci unsigned long crtc_dclk; 808c2ecf20Sopenharmony_ci unsigned long crtc_gclk; 818c2ecf20Sopenharmony_ci unsigned long crtc_goe; 828c2ecf20Sopenharmony_ci unsigned long crtc_ps1_active; 838c2ecf20Sopenharmony_ci char pll_freq; 848c2ecf20Sopenharmony_ci char fast_pll_freq; 858c2ecf20Sopenharmony_ci int sysclk_src; 868c2ecf20Sopenharmony_ci int sysclk_divider; 878c2ecf20Sopenharmony_ci int pixclk_src; 888c2ecf20Sopenharmony_ci int pixclk_divider; 898c2ecf20Sopenharmony_ci int pixclk_divider_rotated; 908c2ecf20Sopenharmony_ci}; 918c2ecf20Sopenharmony_ci 928c2ecf20Sopenharmony_cistruct w100_pll_info { 938c2ecf20Sopenharmony_ci uint16_t freq; /* desired Fout for PLL (Mhz) */ 948c2ecf20Sopenharmony_ci uint8_t M; /* input divider */ 958c2ecf20Sopenharmony_ci uint8_t N_int; /* VCO multiplier */ 968c2ecf20Sopenharmony_ci uint8_t N_fac; /* VCO multiplier fractional part */ 978c2ecf20Sopenharmony_ci uint8_t tfgoal; 988c2ecf20Sopenharmony_ci uint8_t lock_time; 998c2ecf20Sopenharmony_ci}; 1008c2ecf20Sopenharmony_ci 1018c2ecf20Sopenharmony_ci/* Initial Video mode orientation flags */ 1028c2ecf20Sopenharmony_ci#define INIT_MODE_ROTATED 0x1 1038c2ecf20Sopenharmony_ci#define INIT_MODE_FLIPPED 0x2 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_ci/* 1068c2ecf20Sopenharmony_ci * This structure describes the machine which we are running on. 1078c2ecf20Sopenharmony_ci * It is set by machine specific code and used in the probe routine 1088c2ecf20Sopenharmony_ci * of drivers/video/w100fb.c 1098c2ecf20Sopenharmony_ci */ 1108c2ecf20Sopenharmony_cistruct w100fb_mach_info { 1118c2ecf20Sopenharmony_ci /* General Platform Specific Registers */ 1128c2ecf20Sopenharmony_ci struct w100_gen_regs *regs; 1138c2ecf20Sopenharmony_ci /* Table of modes the LCD is capable of */ 1148c2ecf20Sopenharmony_ci struct w100_mode *modelist; 1158c2ecf20Sopenharmony_ci unsigned int num_modes; 1168c2ecf20Sopenharmony_ci /* Hooks for any platform specific tg/lcd code (optional) */ 1178c2ecf20Sopenharmony_ci struct w100_tg_info *tg; 1188c2ecf20Sopenharmony_ci /* External memory definition (if present) */ 1198c2ecf20Sopenharmony_ci struct w100_mem_info *mem; 1208c2ecf20Sopenharmony_ci /* Additional External memory definition (if present) */ 1218c2ecf20Sopenharmony_ci struct w100_bm_mem_info *bm_mem; 1228c2ecf20Sopenharmony_ci /* GPIO definitions (optional) */ 1238c2ecf20Sopenharmony_ci struct w100_gpio_regs *gpio; 1248c2ecf20Sopenharmony_ci /* Initial Mode flags */ 1258c2ecf20Sopenharmony_ci unsigned int init_mode; 1268c2ecf20Sopenharmony_ci /* Xtal Frequency */ 1278c2ecf20Sopenharmony_ci unsigned int xtal_freq; 1288c2ecf20Sopenharmony_ci /* Enable Xtal input doubler (1 == enable) */ 1298c2ecf20Sopenharmony_ci unsigned int xtal_dbl; 1308c2ecf20Sopenharmony_ci}; 1318c2ecf20Sopenharmony_ci 1328c2ecf20Sopenharmony_ci/* General frame buffer data structure */ 1338c2ecf20Sopenharmony_cistruct w100fb_par { 1348c2ecf20Sopenharmony_ci unsigned int chip_id; 1358c2ecf20Sopenharmony_ci unsigned int xres; 1368c2ecf20Sopenharmony_ci unsigned int yres; 1378c2ecf20Sopenharmony_ci unsigned int extmem_active; 1388c2ecf20Sopenharmony_ci unsigned int flip; 1398c2ecf20Sopenharmony_ci unsigned int blanked; 1408c2ecf20Sopenharmony_ci unsigned int fastpll_mode; 1418c2ecf20Sopenharmony_ci unsigned long hsync_len; 1428c2ecf20Sopenharmony_ci struct w100_mode *mode; 1438c2ecf20Sopenharmony_ci struct w100_pll_info *pll_table; 1448c2ecf20Sopenharmony_ci struct w100fb_mach_info *mach; 1458c2ecf20Sopenharmony_ci uint32_t *saved_intmem; 1468c2ecf20Sopenharmony_ci uint32_t *saved_extmem; 1478c2ecf20Sopenharmony_ci}; 148