1/* 2 * Copyright 2005-2009 Freescale Semiconductor, Inc. 3 * 4 * The code contained herein is licensed under the GNU Lesser General 5 * Public License. You may obtain a copy of the GNU Lesser General 6 * Public License Version 2.1 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/lgpl-license.html 9 * http://www.gnu.org/copyleft/lgpl.html 10 */ 11 12#ifndef __DRM_IPU_H__ 13#define __DRM_IPU_H__ 14 15#include <linux/types.h> 16#include <linux/videodev2.h> 17#include <linux/bitmap.h> 18#include <linux/fb.h> 19#include <linux/of.h> 20#include <media/v4l2-mediabus.h> 21#include <video/videomode.h> 22 23struct ipu_soc; 24 25enum ipuv3_type { 26 IPUV3EX, 27 IPUV3M, 28 IPUV3H, 29}; 30 31#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3') 32 33/* 34 * Bitfield of Display Interface signal polarities. 35 */ 36struct ipu_di_signal_cfg { 37 unsigned data_pol:1; /* true = inverted */ 38 unsigned clk_pol:1; /* true = rising edge */ 39 unsigned enable_pol:1; 40 41 struct videomode mode; 42 43 u32 bus_format; 44 u32 v_to_h_sync; 45 46#define IPU_DI_CLKMODE_SYNC (1 << 0) 47#define IPU_DI_CLKMODE_EXT (1 << 1) 48 unsigned long clkflags; 49 50 u8 hsync_pin; 51 u8 vsync_pin; 52}; 53 54/* 55 * Enumeration of CSI destinations 56 */ 57enum ipu_csi_dest { 58 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */ 59 IPU_CSI_DEST_IC, /* to Image Converter */ 60 IPU_CSI_DEST_VDIC, /* to VDIC */ 61}; 62 63/* 64 * Enumeration of IPU rotation modes 65 */ 66#define IPU_ROT_BIT_VFLIP (1 << 0) 67#define IPU_ROT_BIT_HFLIP (1 << 1) 68#define IPU_ROT_BIT_90 (1 << 2) 69 70enum ipu_rotate_mode { 71 IPU_ROTATE_NONE = 0, 72 IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP, 73 IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP, 74 IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP), 75 IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90, 76 IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP), 77 IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP), 78 IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 | 79 IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP), 80}; 81 82/* 90-degree rotations require the IRT unit */ 83#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0) 84 85enum ipu_color_space { 86 IPUV3_COLORSPACE_RGB, 87 IPUV3_COLORSPACE_YUV, 88 IPUV3_COLORSPACE_UNKNOWN, 89}; 90 91/* 92 * Enumeration of VDI MOTION select 93 */ 94enum ipu_motion_sel { 95 MOTION_NONE = 0, 96 LOW_MOTION, 97 MED_MOTION, 98 HIGH_MOTION, 99}; 100 101struct ipuv3_channel; 102 103enum ipu_channel_irq { 104 IPU_IRQ_EOF = 0, 105 IPU_IRQ_NFACK = 64, 106 IPU_IRQ_NFB4EOF = 128, 107 IPU_IRQ_EOS = 192, 108}; 109 110/* 111 * Enumeration of IDMAC channels 112 */ 113#define IPUV3_CHANNEL_CSI0 0 114#define IPUV3_CHANNEL_CSI1 1 115#define IPUV3_CHANNEL_CSI2 2 116#define IPUV3_CHANNEL_CSI3 3 117#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5 118/* 119 * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels, 120 * but the direct CSI->VDI linking is handled the same way as IDMAC 121 * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so 122 * these channel names are used to support the direct CSI->VDI link. 123 */ 124#define IPUV3_CHANNEL_CSI_DIRECT 6 125#define IPUV3_CHANNEL_CSI_VDI_PREV 7 126#define IPUV3_CHANNEL_MEM_VDI_PREV 8 127#define IPUV3_CHANNEL_MEM_VDI_CUR 9 128#define IPUV3_CHANNEL_MEM_VDI_NEXT 10 129#define IPUV3_CHANNEL_MEM_IC_PP 11 130#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12 131#define IPUV3_CHANNEL_VDI_MEM_RECENT 13 132#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14 133#define IPUV3_CHANNEL_G_MEM_IC_PP 15 134#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17 135#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18 136#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19 137#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20 138#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21 139#define IPUV3_CHANNEL_IC_PP_MEM 22 140#define IPUV3_CHANNEL_MEM_BG_SYNC 23 141#define IPUV3_CHANNEL_MEM_BG_ASYNC 24 142#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25 143#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26 144#define IPUV3_CHANNEL_MEM_FG_SYNC 27 145#define IPUV3_CHANNEL_MEM_DC_SYNC 28 146#define IPUV3_CHANNEL_MEM_FG_ASYNC 29 147#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31 148#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33 149#define IPUV3_CHANNEL_DC_MEM_READ 40 150#define IPUV3_CHANNEL_MEM_DC_ASYNC 41 151#define IPUV3_CHANNEL_MEM_DC_COMMAND 42 152#define IPUV3_CHANNEL_MEM_DC_COMMAND2 43 153#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44 154#define IPUV3_CHANNEL_MEM_ROT_ENC 45 155#define IPUV3_CHANNEL_MEM_ROT_VF 46 156#define IPUV3_CHANNEL_MEM_ROT_PP 47 157#define IPUV3_CHANNEL_ROT_ENC_MEM 48 158#define IPUV3_CHANNEL_ROT_VF_MEM 49 159#define IPUV3_CHANNEL_ROT_PP_MEM 50 160#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51 161#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52 162#define IPUV3_NUM_CHANNELS 64 163 164static inline int ipu_channel_alpha_channel(int ch_num) 165{ 166 switch (ch_num) { 167 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: 168 return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA; 169 case IPUV3_CHANNEL_G_MEM_IC_PP: 170 return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA; 171 case IPUV3_CHANNEL_MEM_FG_SYNC: 172 return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA; 173 case IPUV3_CHANNEL_MEM_FG_ASYNC: 174 return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA; 175 case IPUV3_CHANNEL_MEM_BG_SYNC: 176 return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA; 177 case IPUV3_CHANNEL_MEM_BG_ASYNC: 178 return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA; 179 case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB: 180 return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA; 181 default: 182 return -EINVAL; 183 } 184} 185 186int ipu_map_irq(struct ipu_soc *ipu, int irq); 187int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, 188 enum ipu_channel_irq irq); 189 190#define IPU_IRQ_DP_SF_START (448 + 2) 191#define IPU_IRQ_DP_SF_END (448 + 3) 192#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END, 193#define IPU_IRQ_DC_FC_0 (448 + 8) 194#define IPU_IRQ_DC_FC_1 (448 + 9) 195#define IPU_IRQ_DC_FC_2 (448 + 10) 196#define IPU_IRQ_DC_FC_3 (448 + 11) 197#define IPU_IRQ_DC_FC_4 (448 + 12) 198#define IPU_IRQ_DC_FC_6 (448 + 13) 199#define IPU_IRQ_VSYNC_PRE_0 (448 + 14) 200#define IPU_IRQ_VSYNC_PRE_1 (448 + 15) 201 202/* 203 * IPU Common functions 204 */ 205int ipu_get_num(struct ipu_soc *ipu); 206void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2); 207void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi); 208void ipu_dump(struct ipu_soc *ipu); 209 210/* 211 * IPU Image DMA Controller (idmac) functions 212 */ 213struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); 214void ipu_idmac_put(struct ipuv3_channel *); 215 216int ipu_idmac_enable_channel(struct ipuv3_channel *channel); 217int ipu_idmac_disable_channel(struct ipuv3_channel *channel); 218void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable); 219int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts); 220int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); 221 222void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, 223 bool doublebuffer); 224int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel); 225bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num); 226void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num); 227void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num); 228int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch); 229int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch); 230int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink); 231int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink); 232 233/* 234 * IPU Channel Parameter Memory (cpmem) functions 235 */ 236struct ipu_rgb { 237 struct fb_bitfield red; 238 struct fb_bitfield green; 239 struct fb_bitfield blue; 240 struct fb_bitfield transp; 241 int bits_per_pixel; 242}; 243 244struct ipu_image { 245 struct v4l2_pix_format pix; 246 struct v4l2_rect rect; 247 dma_addr_t phys0; 248 dma_addr_t phys1; 249 /* chroma plane offset overrides */ 250 u32 u_offset; 251 u32 v_offset; 252}; 253 254void ipu_cpmem_zero(struct ipuv3_channel *ch); 255void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres); 256void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch); 257void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride); 258void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch); 259void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf); 260void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off); 261void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride, 262 u32 pixelformat); 263void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id); 264int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch); 265void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize); 266void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch); 267void ipu_cpmem_set_rotation(struct ipuv3_channel *ch, 268 enum ipu_rotate_mode rot); 269int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, 270 const struct ipu_rgb *rgb); 271int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width); 272void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format); 273void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 274 unsigned int uv_stride, 275 unsigned int u_offset, 276 unsigned int v_offset); 277int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc); 278int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image); 279void ipu_cpmem_dump(struct ipuv3_channel *ch); 280 281/* 282 * IPU Display Controller (dc) functions 283 */ 284struct ipu_dc; 285struct ipu_di; 286struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); 287void ipu_dc_put(struct ipu_dc *dc); 288int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, 289 u32 pixel_fmt, u32 width); 290void ipu_dc_enable(struct ipu_soc *ipu); 291void ipu_dc_enable_channel(struct ipu_dc *dc); 292void ipu_dc_disable_channel(struct ipu_dc *dc); 293void ipu_dc_disable(struct ipu_soc *ipu); 294 295/* 296 * IPU Display Interface (di) functions 297 */ 298struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); 299void ipu_di_put(struct ipu_di *); 300int ipu_di_disable(struct ipu_di *); 301int ipu_di_enable(struct ipu_di *); 302int ipu_di_get_num(struct ipu_di *); 303int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode); 304int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); 305 306/* 307 * IPU Display Multi FIFO Controller (dmfc) functions 308 */ 309struct dmfc_channel; 310int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc); 311void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc); 312void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width); 313struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); 314void ipu_dmfc_put(struct dmfc_channel *dmfc); 315 316/* 317 * IPU Display Processor (dp) functions 318 */ 319#define IPU_DP_FLOW_SYNC_BG 0 320#define IPU_DP_FLOW_SYNC_FG 1 321#define IPU_DP_FLOW_ASYNC0_BG 2 322#define IPU_DP_FLOW_ASYNC0_FG 3 323#define IPU_DP_FLOW_ASYNC1_BG 4 324#define IPU_DP_FLOW_ASYNC1_FG 5 325 326struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); 327void ipu_dp_put(struct ipu_dp *); 328int ipu_dp_enable(struct ipu_soc *ipu); 329int ipu_dp_enable_channel(struct ipu_dp *dp); 330void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync); 331void ipu_dp_disable(struct ipu_soc *ipu); 332int ipu_dp_setup_channel(struct ipu_dp *dp, 333 enum ipu_color_space in, enum ipu_color_space out); 334int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); 335int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, 336 bool bg_chan); 337 338/* 339 * IPU Prefetch Resolve Gasket (prg) functions 340 */ 341int ipu_prg_max_active_channels(void); 342bool ipu_prg_present(struct ipu_soc *ipu); 343bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format, 344 uint64_t modifier); 345int ipu_prg_enable(struct ipu_soc *ipu); 346void ipu_prg_disable(struct ipu_soc *ipu); 347void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan); 348int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan, 349 unsigned int axi_id, unsigned int width, 350 unsigned int height, unsigned int stride, 351 u32 format, uint64_t modifier, unsigned long *eba); 352bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan); 353 354/* 355 * IPU CMOS Sensor Interface (csi) functions 356 */ 357struct ipu_csi; 358int ipu_csi_init_interface(struct ipu_csi *csi, 359 const struct v4l2_mbus_config *mbus_cfg, 360 const struct v4l2_mbus_framefmt *infmt, 361 const struct v4l2_mbus_framefmt *outfmt); 362bool ipu_csi_is_interlaced(struct ipu_csi *csi); 363void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w); 364void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w); 365void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert); 366void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active, 367 u32 r_value, u32 g_value, u32 b_value, 368 u32 pix_clk); 369int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc, 370 struct v4l2_mbus_framefmt *mbus_fmt); 371int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip, 372 u32 max_ratio, u32 id); 373int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest); 374int ipu_csi_enable(struct ipu_csi *csi); 375int ipu_csi_disable(struct ipu_csi *csi); 376struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id); 377void ipu_csi_put(struct ipu_csi *csi); 378void ipu_csi_dump(struct ipu_csi *csi); 379 380/* 381 * IPU Image Converter (ic) functions 382 */ 383enum ipu_ic_task { 384 IC_TASK_ENCODER, 385 IC_TASK_VIEWFINDER, 386 IC_TASK_POST_PROCESSOR, 387 IC_NUM_TASKS, 388}; 389 390/* 391 * The parameters that describe a colorspace according to the 392 * Image Converter: 393 * - Y'CbCr encoding 394 * - quantization 395 * - "colorspace" (RGB or YUV). 396 */ 397struct ipu_ic_colorspace { 398 enum v4l2_ycbcr_encoding enc; 399 enum v4l2_quantization quant; 400 enum ipu_color_space cs; 401}; 402 403static inline void 404ipu_ic_fill_colorspace(struct ipu_ic_colorspace *ic_cs, 405 enum v4l2_ycbcr_encoding enc, 406 enum v4l2_quantization quant, 407 enum ipu_color_space cs) 408{ 409 ic_cs->enc = enc; 410 ic_cs->quant = quant; 411 ic_cs->cs = cs; 412} 413 414struct ipu_ic_csc_params { 415 s16 coeff[3][3]; /* signed 9-bit integer coefficients */ 416 s16 offset[3]; /* signed 11+2-bit fixed point offset */ 417 u8 scale:2; /* scale coefficients * 2^(scale-1) */ 418 bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */ 419}; 420 421struct ipu_ic_csc { 422 struct ipu_ic_colorspace in_cs; 423 struct ipu_ic_colorspace out_cs; 424 struct ipu_ic_csc_params params; 425}; 426 427struct ipu_ic; 428 429int __ipu_ic_calc_csc(struct ipu_ic_csc *csc); 430int ipu_ic_calc_csc(struct ipu_ic_csc *csc, 431 enum v4l2_ycbcr_encoding in_enc, 432 enum v4l2_quantization in_quant, 433 enum ipu_color_space in_cs, 434 enum v4l2_ycbcr_encoding out_enc, 435 enum v4l2_quantization out_quant, 436 enum ipu_color_space out_cs); 437int ipu_ic_task_init(struct ipu_ic *ic, 438 const struct ipu_ic_csc *csc, 439 int in_width, int in_height, 440 int out_width, int out_height); 441int ipu_ic_task_init_rsc(struct ipu_ic *ic, 442 const struct ipu_ic_csc *csc, 443 int in_width, int in_height, 444 int out_width, int out_height, 445 u32 rsc); 446int ipu_ic_task_graphics_init(struct ipu_ic *ic, 447 const struct ipu_ic_colorspace *g_in_cs, 448 bool galpha_en, u32 galpha, 449 bool colorkey_en, u32 colorkey); 450void ipu_ic_task_enable(struct ipu_ic *ic); 451void ipu_ic_task_disable(struct ipu_ic *ic); 452int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel, 453 u32 width, u32 height, int burst_size, 454 enum ipu_rotate_mode rot); 455int ipu_ic_enable(struct ipu_ic *ic); 456int ipu_ic_disable(struct ipu_ic *ic); 457struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task); 458void ipu_ic_put(struct ipu_ic *ic); 459void ipu_ic_dump(struct ipu_ic *ic); 460 461/* 462 * IPU Video De-Interlacer (vdi) functions 463 */ 464struct ipu_vdi; 465void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field); 466void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel); 467void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres); 468void ipu_vdi_unsetup(struct ipu_vdi *vdi); 469int ipu_vdi_enable(struct ipu_vdi *vdi); 470int ipu_vdi_disable(struct ipu_vdi *vdi); 471struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu); 472void ipu_vdi_put(struct ipu_vdi *vdi); 473 474/* 475 * IPU Sensor Multiple FIFO Controller (SMFC) functions 476 */ 477struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno); 478void ipu_smfc_put(struct ipu_smfc *smfc); 479int ipu_smfc_enable(struct ipu_smfc *smfc); 480int ipu_smfc_disable(struct ipu_smfc *smfc); 481int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id); 482int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize); 483int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level); 484 485enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc); 486enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat); 487int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, 488 bool hflip, bool vflip); 489int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, 490 bool hflip, bool vflip); 491 492struct ipu_client_platformdata { 493 int csi; 494 int di; 495 int dc; 496 int dp; 497 int dma[2]; 498 struct device_node *of_node; 499}; 500 501#endif /* __DRM_IPU_H__ */ 502