1/** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11/* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36#ifndef _DRM_H_ 37#define _DRM_H_ 38 39#if defined(__KERNEL__) 40 41#include <linux/types.h> 42#include <asm/ioctl.h> 43typedef unsigned int drm_handle_t; 44 45#elif defined(__linux__) 46 47#include <linux/types.h> 48#include <asm/ioctl.h> 49typedef unsigned int drm_handle_t; 50 51#else /* One of the BSDs */ 52 53#include <stdint.h> 54#include <sys/ioccom.h> 55#include <sys/types.h> 56typedef int8_t __s8; 57typedef uint8_t __u8; 58typedef int16_t __s16; 59typedef uint16_t __u16; 60typedef int32_t __s32; 61typedef uint32_t __u32; 62typedef int64_t __s64; 63typedef uint64_t __u64; 64typedef size_t __kernel_size_t; 65typedef unsigned long drm_handle_t; 66 67#endif 68 69#if defined(__cplusplus) 70extern "C" { 71#endif 72 73#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 74#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 75#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 76#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 77 78#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 79#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 80#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 81#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 82#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 83 84typedef unsigned int drm_context_t; 85typedef unsigned int drm_drawable_t; 86typedef unsigned int drm_magic_t; 87 88/** 89 * Cliprect. 90 * 91 * \warning: If you change this structure, make sure you change 92 * XF86DRIClipRectRec in the server as well 93 * 94 * \note KW: Actually it's illegal to change either for 95 * backwards-compatibility reasons. 96 */ 97struct drm_clip_rect { 98 unsigned short x1; 99 unsigned short y1; 100 unsigned short x2; 101 unsigned short y2; 102}; 103 104/** 105 * Drawable information. 106 */ 107struct drm_drawable_info { 108 unsigned int num_rects; 109 struct drm_clip_rect *rects; 110}; 111 112/** 113 * Texture region, 114 */ 115struct drm_tex_region { 116 unsigned char next; 117 unsigned char prev; 118 unsigned char in_use; 119 unsigned char padding; 120 unsigned int age; 121}; 122 123/** 124 * Hardware lock. 125 * 126 * The lock structure is a simple cache-line aligned integer. To avoid 127 * processor bus contention on a multiprocessor system, there should not be any 128 * other data stored in the same cache line. 129 */ 130struct drm_hw_lock { 131 __volatile__ unsigned int lock; /**< lock variable */ 132 char padding[60]; /**< Pad to cache line */ 133}; 134 135/** 136 * DRM_IOCTL_VERSION ioctl argument type. 137 * 138 * \sa drmGetVersion(). 139 */ 140struct drm_version { 141 int version_major; /**< Major version */ 142 int version_minor; /**< Minor version */ 143 int version_patchlevel; /**< Patch level */ 144 __kernel_size_t name_len; /**< Length of name buffer */ 145 char __user *name; /**< Name of driver */ 146 __kernel_size_t date_len; /**< Length of date buffer */ 147 char __user *date; /**< User-space buffer to hold date */ 148 __kernel_size_t desc_len; /**< Length of desc buffer */ 149 char __user *desc; /**< User-space buffer to hold desc */ 150}; 151 152/** 153 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 154 * 155 * \sa drmGetBusid() and drmSetBusId(). 156 */ 157struct drm_unique { 158 __kernel_size_t unique_len; /**< Length of unique */ 159 char __user *unique; /**< Unique name for driver instantiation */ 160}; 161 162struct drm_list { 163 int count; /**< Length of user-space structures */ 164 struct drm_version __user *version; 165}; 166 167struct drm_block { 168 int unused; 169}; 170 171/** 172 * DRM_IOCTL_CONTROL ioctl argument type. 173 * 174 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 175 */ 176struct drm_control { 177 enum { 178 DRM_ADD_COMMAND, 179 DRM_RM_COMMAND, 180 DRM_INST_HANDLER, 181 DRM_UNINST_HANDLER 182 } func; 183 int irq; 184}; 185 186/** 187 * Type of memory to map. 188 */ 189enum drm_map_type { 190 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 191 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 192 _DRM_SHM = 2, /**< shared, cached */ 193 _DRM_AGP = 3, /**< AGP/GART */ 194 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 195 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ 196}; 197 198/** 199 * Memory mapping flags. 200 */ 201enum drm_map_flags { 202 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 203 _DRM_READ_ONLY = 0x02, 204 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 205 _DRM_KERNEL = 0x08, /**< kernel requires access */ 206 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 207 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 208 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 209 _DRM_DRIVER = 0x80 /**< Managed by driver */ 210}; 211 212struct drm_ctx_priv_map { 213 unsigned int ctx_id; /**< Context requesting private mapping */ 214 void *handle; /**< Handle of map */ 215}; 216 217/** 218 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 219 * argument type. 220 * 221 * \sa drmAddMap(). 222 */ 223struct drm_map { 224 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 225 unsigned long size; /**< Requested physical size (bytes) */ 226 enum drm_map_type type; /**< Type of memory to map */ 227 enum drm_map_flags flags; /**< Flags */ 228 void *handle; /**< User-space: "Handle" to pass to mmap() */ 229 /**< Kernel-space: kernel-virtual address */ 230 int mtrr; /**< MTRR slot used */ 231 /* Private data */ 232}; 233 234/** 235 * DRM_IOCTL_GET_CLIENT ioctl argument type. 236 */ 237struct drm_client { 238 int idx; /**< Which client desired? */ 239 int auth; /**< Is client authenticated? */ 240 unsigned long pid; /**< Process ID */ 241 unsigned long uid; /**< User ID */ 242 unsigned long magic; /**< Magic */ 243 unsigned long iocs; /**< Ioctl count */ 244}; 245 246enum drm_stat_type { 247 _DRM_STAT_LOCK, 248 _DRM_STAT_OPENS, 249 _DRM_STAT_CLOSES, 250 _DRM_STAT_IOCTLS, 251 _DRM_STAT_LOCKS, 252 _DRM_STAT_UNLOCKS, 253 _DRM_STAT_VALUE, /**< Generic value */ 254 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 255 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 256 257 _DRM_STAT_IRQ, /**< IRQ */ 258 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 259 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 260 _DRM_STAT_DMA, /**< DMA */ 261 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 262 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 263 /* Add to the *END* of the list */ 264}; 265 266/** 267 * DRM_IOCTL_GET_STATS ioctl argument type. 268 */ 269struct drm_stats { 270 unsigned long count; 271 struct { 272 unsigned long value; 273 enum drm_stat_type type; 274 } data[15]; 275}; 276 277/** 278 * Hardware locking flags. 279 */ 280enum drm_lock_flags { 281 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 282 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 283 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 284 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 285 /* These *HALT* flags aren't supported yet 286 -- they will be used to support the 287 full-screen DGA-like mode. */ 288 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 289 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 290}; 291 292/** 293 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 294 * 295 * \sa drmGetLock() and drmUnlock(). 296 */ 297struct drm_lock { 298 int context; 299 enum drm_lock_flags flags; 300}; 301 302/** 303 * DMA flags 304 * 305 * \warning 306 * These values \e must match xf86drm.h. 307 * 308 * \sa drm_dma. 309 */ 310enum drm_dma_flags { 311 /* Flags for DMA buffer dispatch */ 312 _DRM_DMA_BLOCK = 0x01, /**< 313 * Block until buffer dispatched. 314 * 315 * \note The buffer may not yet have 316 * been processed by the hardware -- 317 * getting a hardware lock with the 318 * hardware quiescent will ensure 319 * that the buffer has been 320 * processed. 321 */ 322 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 323 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 324 325 /* Flags for DMA buffer request */ 326 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 327 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 328 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 329}; 330 331/** 332 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 333 * 334 * \sa drmAddBufs(). 335 */ 336struct drm_buf_desc { 337 int count; /**< Number of buffers of this size */ 338 int size; /**< Size in bytes */ 339 int low_mark; /**< Low water mark */ 340 int high_mark; /**< High water mark */ 341 enum { 342 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 343 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 344 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 345 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 346 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 347 } flags; 348 unsigned long agp_start; /**< 349 * Start address of where the AGP buffers are 350 * in the AGP aperture 351 */ 352}; 353 354/** 355 * DRM_IOCTL_INFO_BUFS ioctl argument type. 356 */ 357struct drm_buf_info { 358 int count; /**< Entries in list */ 359 struct drm_buf_desc __user *list; 360}; 361 362/** 363 * DRM_IOCTL_FREE_BUFS ioctl argument type. 364 */ 365struct drm_buf_free { 366 int count; 367 int __user *list; 368}; 369 370/** 371 * Buffer information 372 * 373 * \sa drm_buf_map. 374 */ 375struct drm_buf_pub { 376 int idx; /**< Index into the master buffer list */ 377 int total; /**< Buffer size */ 378 int used; /**< Amount of buffer in use (for DMA) */ 379 void __user *address; /**< Address of buffer */ 380}; 381 382/** 383 * DRM_IOCTL_MAP_BUFS ioctl argument type. 384 */ 385struct drm_buf_map { 386 int count; /**< Length of the buffer list */ 387#ifdef __cplusplus 388 void __user *virt; 389#else 390 void __user *virtual; /**< Mmap'd area in user-virtual */ 391#endif 392 struct drm_buf_pub __user *list; /**< Buffer information */ 393}; 394 395/** 396 * DRM_IOCTL_DMA ioctl argument type. 397 * 398 * Indices here refer to the offset into the buffer list in drm_buf_get. 399 * 400 * \sa drmDMA(). 401 */ 402struct drm_dma { 403 int context; /**< Context handle */ 404 int send_count; /**< Number of buffers to send */ 405 int __user *send_indices; /**< List of handles to buffers */ 406 int __user *send_sizes; /**< Lengths of data to send */ 407 enum drm_dma_flags flags; /**< Flags */ 408 int request_count; /**< Number of buffers requested */ 409 int request_size; /**< Desired size for buffers */ 410 int __user *request_indices; /**< Buffer information */ 411 int __user *request_sizes; 412 int granted_count; /**< Number of buffers granted */ 413}; 414 415enum drm_ctx_flags { 416 _DRM_CONTEXT_PRESERVED = 0x01, 417 _DRM_CONTEXT_2DONLY = 0x02 418}; 419 420/** 421 * DRM_IOCTL_ADD_CTX ioctl argument type. 422 * 423 * \sa drmCreateContext() and drmDestroyContext(). 424 */ 425struct drm_ctx { 426 drm_context_t handle; 427 enum drm_ctx_flags flags; 428}; 429 430/** 431 * DRM_IOCTL_RES_CTX ioctl argument type. 432 */ 433struct drm_ctx_res { 434 int count; 435 struct drm_ctx __user *contexts; 436}; 437 438/** 439 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 440 */ 441struct drm_draw { 442 drm_drawable_t handle; 443}; 444 445/** 446 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 447 */ 448typedef enum { 449 DRM_DRAWABLE_CLIPRECTS 450} drm_drawable_info_type_t; 451 452struct drm_update_draw { 453 drm_drawable_t handle; 454 unsigned int type; 455 unsigned int num; 456 unsigned long long data; 457}; 458 459/** 460 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 461 */ 462struct drm_auth { 463 drm_magic_t magic; 464}; 465 466/** 467 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 468 * 469 * \sa drmGetInterruptFromBusID(). 470 */ 471struct drm_irq_busid { 472 int irq; /**< IRQ number */ 473 int busnum; /**< bus number */ 474 int devnum; /**< device number */ 475 int funcnum; /**< function number */ 476}; 477 478enum drm_vblank_seq_type { 479 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 480 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 481 /* bits 1-6 are reserved for high crtcs */ 482 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 483 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 484 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 485 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 486 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 487 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 488}; 489#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 490 491#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 492#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 493 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 494 495struct drm_wait_vblank_request { 496 enum drm_vblank_seq_type type; 497 unsigned int sequence; 498 unsigned long signal; 499}; 500 501struct drm_wait_vblank_reply { 502 enum drm_vblank_seq_type type; 503 unsigned int sequence; 504 long tval_sec; 505 long tval_usec; 506}; 507 508/** 509 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 510 * 511 * \sa drmWaitVBlank(). 512 */ 513union drm_wait_vblank { 514 struct drm_wait_vblank_request request; 515 struct drm_wait_vblank_reply reply; 516}; 517 518#define _DRM_PRE_MODESET 1 519#define _DRM_POST_MODESET 2 520 521/** 522 * DRM_IOCTL_MODESET_CTL ioctl argument type 523 * 524 * \sa drmModesetCtl(). 525 */ 526struct drm_modeset_ctl { 527 __u32 crtc; 528 __u32 cmd; 529}; 530 531/** 532 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 533 * 534 * \sa drmAgpEnable(). 535 */ 536struct drm_agp_mode { 537 unsigned long mode; /**< AGP mode */ 538}; 539 540/** 541 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 542 * 543 * \sa drmAgpAlloc() and drmAgpFree(). 544 */ 545struct drm_agp_buffer { 546 unsigned long size; /**< In bytes -- will round to page boundary */ 547 unsigned long handle; /**< Used for binding / unbinding */ 548 unsigned long type; /**< Type of memory to allocate */ 549 unsigned long physical; /**< Physical used by i810 */ 550}; 551 552/** 553 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 554 * 555 * \sa drmAgpBind() and drmAgpUnbind(). 556 */ 557struct drm_agp_binding { 558 unsigned long handle; /**< From drm_agp_buffer */ 559 unsigned long offset; /**< In bytes -- will round to page boundary */ 560}; 561 562/** 563 * DRM_IOCTL_AGP_INFO ioctl argument type. 564 * 565 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 566 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 567 * drmAgpVendorId() and drmAgpDeviceId(). 568 */ 569struct drm_agp_info { 570 int agp_version_major; 571 int agp_version_minor; 572 unsigned long mode; 573 unsigned long aperture_base; /* physical address */ 574 unsigned long aperture_size; /* bytes */ 575 unsigned long memory_allowed; /* bytes */ 576 unsigned long memory_used; 577 578 /* PCI information */ 579 unsigned short id_vendor; 580 unsigned short id_device; 581}; 582 583/** 584 * DRM_IOCTL_SG_ALLOC ioctl argument type. 585 */ 586struct drm_scatter_gather { 587 unsigned long size; /**< In bytes -- will round to page boundary */ 588 unsigned long handle; /**< Used for mapping / unmapping */ 589}; 590 591/** 592 * DRM_IOCTL_SET_VERSION ioctl argument type. 593 */ 594struct drm_set_version { 595 int drm_di_major; 596 int drm_di_minor; 597 int drm_dd_major; 598 int drm_dd_minor; 599}; 600 601/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 602struct drm_gem_close { 603 /** Handle of the object to be closed. */ 604 __u32 handle; 605 __u32 pad; 606}; 607 608/** DRM_IOCTL_GEM_FLINK ioctl argument type */ 609struct drm_gem_flink { 610 /** Handle for the object being named */ 611 __u32 handle; 612 613 /** Returned global name */ 614 __u32 name; 615}; 616 617/** DRM_IOCTL_GEM_OPEN ioctl argument type */ 618struct drm_gem_open { 619 /** Name of object being opened */ 620 __u32 name; 621 622 /** Returned handle for the object */ 623 __u32 handle; 624 625 /** Returned size of the object */ 626 __u64 size; 627}; 628 629#define DRM_CAP_DUMB_BUFFER 0x1 630#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 631#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 632#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 633#define DRM_CAP_PRIME 0x5 634#define DRM_PRIME_CAP_IMPORT 0x1 635#define DRM_PRIME_CAP_EXPORT 0x2 636#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 637#define DRM_CAP_ASYNC_PAGE_FLIP 0x7 638/* 639 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight 640 * combination for the hardware cursor. The intention is that a hardware 641 * agnostic userspace can query a cursor plane size to use. 642 * 643 * Note that the cross-driver contract is to merely return a valid size; 644 * drivers are free to attach another meaning on top, eg. i915 returns the 645 * maximum plane size. 646 */ 647#define DRM_CAP_CURSOR_WIDTH 0x8 648#define DRM_CAP_CURSOR_HEIGHT 0x9 649#define DRM_CAP_ADDFB2_MODIFIERS 0x10 650#define DRM_CAP_PAGE_FLIP_TARGET 0x11 651#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 652#define DRM_CAP_SYNCOBJ 0x13 653#define DRM_CAP_SYNCOBJ_TIMELINE 0x14 654 655/** DRM_IOCTL_GET_CAP ioctl argument type */ 656struct drm_get_cap { 657 __u64 capability; 658 __u64 value; 659}; 660 661/** 662 * DRM_CLIENT_CAP_STEREO_3D 663 * 664 * if set to 1, the DRM core will expose the stereo 3D capabilities of the 665 * monitor by advertising the supported 3D layouts in the flags of struct 666 * drm_mode_modeinfo. 667 */ 668#define DRM_CLIENT_CAP_STEREO_3D 1 669 670/** 671 * DRM_CLIENT_CAP_UNIVERSAL_PLANES 672 * 673 * If set to 1, the DRM core will expose all planes (overlay, primary, and 674 * cursor) to userspace. 675 */ 676#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 677 678/** 679 * DRM_CLIENT_CAP_ATOMIC 680 * 681 * If set to 1, the DRM core will expose atomic properties to userspace 682 */ 683#define DRM_CLIENT_CAP_ATOMIC 3 684 685/** 686 * DRM_CLIENT_CAP_ASPECT_RATIO 687 * 688 * If set to 1, the DRM core will provide aspect ratio information in modes. 689 */ 690#define DRM_CLIENT_CAP_ASPECT_RATIO 4 691 692/** 693 * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 694 * 695 * If set to 1, the DRM core will expose special connectors to be used for 696 * writing back to memory the scene setup in the commit. Depends on client 697 * also supporting DRM_CLIENT_CAP_ATOMIC 698 */ 699#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 700 701/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ 702struct drm_set_client_cap { 703 __u64 capability; 704 __u64 value; 705}; 706 707#define DRM_RDWR O_RDWR 708#define DRM_CLOEXEC O_CLOEXEC 709struct drm_prime_handle { 710 __u32 handle; 711 712 /** Flags.. only applicable for handle->fd */ 713 __u32 flags; 714 715 /** Returned dmabuf file descriptor */ 716 __s32 fd; 717}; 718 719struct drm_syncobj_create { 720 __u32 handle; 721#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) 722 __u32 flags; 723}; 724 725struct drm_syncobj_destroy { 726 __u32 handle; 727 __u32 pad; 728}; 729 730#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) 731#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) 732struct drm_syncobj_handle { 733 __u32 handle; 734 __u32 flags; 735 736 __s32 fd; 737 __u32 pad; 738}; 739 740struct drm_syncobj_transfer { 741 __u32 src_handle; 742 __u32 dst_handle; 743 __u64 src_point; 744 __u64 dst_point; 745 __u32 flags; 746 __u32 pad; 747}; 748 749#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) 750#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) 751#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ 752struct drm_syncobj_wait { 753 __u64 handles; 754 /* absolute timeout */ 755 __s64 timeout_nsec; 756 __u32 count_handles; 757 __u32 flags; 758 __u32 first_signaled; /* only valid when not waiting all */ 759 __u32 pad; 760}; 761 762struct drm_syncobj_timeline_wait { 763 __u64 handles; 764 /* wait on specific timeline point for every handles*/ 765 __u64 points; 766 /* absolute timeout */ 767 __s64 timeout_nsec; 768 __u32 count_handles; 769 __u32 flags; 770 __u32 first_signaled; /* only valid when not waiting all */ 771 __u32 pad; 772}; 773 774 775struct drm_syncobj_array { 776 __u64 handles; 777 __u32 count_handles; 778 __u32 pad; 779}; 780 781#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */ 782struct drm_syncobj_timeline_array { 783 __u64 handles; 784 __u64 points; 785 __u32 count_handles; 786 __u32 flags; 787}; 788 789 790/* Query current scanout sequence number */ 791struct drm_crtc_get_sequence { 792 __u32 crtc_id; /* requested crtc_id */ 793 __u32 active; /* return: crtc output is active */ 794 __u64 sequence; /* return: most recent vblank sequence */ 795 __s64 sequence_ns; /* return: most recent time of first pixel out */ 796}; 797 798/* Queue event to be delivered at specified sequence. Time stamp marks 799 * when the first pixel of the refresh cycle leaves the display engine 800 * for the display 801 */ 802#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ 803#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ 804 805struct drm_crtc_queue_sequence { 806 __u32 crtc_id; 807 __u32 flags; 808 __u64 sequence; /* on input, target sequence. on output, actual sequence */ 809 __u64 user_data; /* user data passed to event */ 810}; 811 812#if defined(__cplusplus) 813} 814#endif 815 816#include "drm_mode.h" 817 818#if defined(__cplusplus) 819extern "C" { 820#endif 821 822#define DRM_IOCTL_BASE 'd' 823#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 824#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 825#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 826#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 827 828#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 829#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 830#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 831#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 832#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 833#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 834#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 835#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 836#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 837#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 838#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 839#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 840#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 841#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) 842 843#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 844#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 845#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 846#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 847#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 848#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 849#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 850#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 851#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 852#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 853#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 854 855#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 856 857#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 858#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 859 860#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 861#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 862 863#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 864#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 865#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 866#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 867#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 868#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 869#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 870#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 871#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 872#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 873#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 874#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 875#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 876 877#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 878#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 879 880#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 881#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 882#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 883#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 884#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 885#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 886#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 887#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 888 889#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 890#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 891 892#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 893 894#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) 895#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) 896 897#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 898 899#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 900#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 901#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 902#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 903#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 904#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 905#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 906#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 907#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 908#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 909 910#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 911#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 912#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 913#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 914#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 915#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 916#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 917#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 918 919#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 920#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 921#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 922#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 923#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 924#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 925#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 926#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 927#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 928#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) 929#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) 930#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) 931#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) 932 933#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) 934#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) 935#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) 936#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) 937#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) 938#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) 939#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) 940 941#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) 942#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) 943#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) 944#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) 945 946#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) 947#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) 948#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) 949#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) 950 951#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) 952 953/** 954 * Device specific ioctls should only be in their respective headers 955 * The device specific ioctl range is from 0x40 to 0x9f. 956 * Generic IOCTLS restart at 0xA0. 957 * 958 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 959 * drmCommandReadWrite(). 960 */ 961#define DRM_COMMAND_BASE 0x40 962#define DRM_COMMAND_END 0xA0 963 964/** 965 * Header for events written back to userspace on the drm fd. The 966 * type defines the type of event, the length specifies the total 967 * length of the event (including the header), and user_data is 968 * typically a 64 bit value passed with the ioctl that triggered the 969 * event. A read on the drm fd will always only return complete 970 * events, that is, if for example the read buffer is 100 bytes, and 971 * there are two 64 byte events pending, only one will be returned. 972 * 973 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 974 * up are chipset specific. 975 */ 976struct drm_event { 977 __u32 type; 978 __u32 length; 979}; 980 981#define DRM_EVENT_VBLANK 0x01 982#define DRM_EVENT_FLIP_COMPLETE 0x02 983#define DRM_EVENT_CRTC_SEQUENCE 0x03 984 985struct drm_event_vblank { 986 struct drm_event base; 987 __u64 user_data; 988 __u32 tv_sec; 989 __u32 tv_usec; 990 __u32 sequence; 991 __u32 crtc_id; /* 0 on older kernels that do not support this */ 992}; 993 994/* Event delivered at sequence. Time stamp marks when the first pixel 995 * of the refresh cycle leaves the display engine for the display 996 */ 997struct drm_event_crtc_sequence { 998 struct drm_event base; 999 __u64 user_data; 1000 __s64 time_ns; 1001 __u64 sequence; 1002}; 1003 1004/* typedef area */ 1005#ifndef __KERNEL__ 1006typedef struct drm_clip_rect drm_clip_rect_t; 1007typedef struct drm_drawable_info drm_drawable_info_t; 1008typedef struct drm_tex_region drm_tex_region_t; 1009typedef struct drm_hw_lock drm_hw_lock_t; 1010typedef struct drm_version drm_version_t; 1011typedef struct drm_unique drm_unique_t; 1012typedef struct drm_list drm_list_t; 1013typedef struct drm_block drm_block_t; 1014typedef struct drm_control drm_control_t; 1015typedef enum drm_map_type drm_map_type_t; 1016typedef enum drm_map_flags drm_map_flags_t; 1017typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 1018typedef struct drm_map drm_map_t; 1019typedef struct drm_client drm_client_t; 1020typedef enum drm_stat_type drm_stat_type_t; 1021typedef struct drm_stats drm_stats_t; 1022typedef enum drm_lock_flags drm_lock_flags_t; 1023typedef struct drm_lock drm_lock_t; 1024typedef enum drm_dma_flags drm_dma_flags_t; 1025typedef struct drm_buf_desc drm_buf_desc_t; 1026typedef struct drm_buf_info drm_buf_info_t; 1027typedef struct drm_buf_free drm_buf_free_t; 1028typedef struct drm_buf_pub drm_buf_pub_t; 1029typedef struct drm_buf_map drm_buf_map_t; 1030typedef struct drm_dma drm_dma_t; 1031typedef union drm_wait_vblank drm_wait_vblank_t; 1032typedef struct drm_agp_mode drm_agp_mode_t; 1033typedef enum drm_ctx_flags drm_ctx_flags_t; 1034typedef struct drm_ctx drm_ctx_t; 1035typedef struct drm_ctx_res drm_ctx_res_t; 1036typedef struct drm_draw drm_draw_t; 1037typedef struct drm_update_draw drm_update_draw_t; 1038typedef struct drm_auth drm_auth_t; 1039typedef struct drm_irq_busid drm_irq_busid_t; 1040typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 1041 1042typedef struct drm_agp_buffer drm_agp_buffer_t; 1043typedef struct drm_agp_binding drm_agp_binding_t; 1044typedef struct drm_agp_info drm_agp_info_t; 1045typedef struct drm_scatter_gather drm_scatter_gather_t; 1046typedef struct drm_set_version drm_set_version_t; 1047#endif 1048 1049#if defined(__cplusplus) 1050} 1051#endif 1052 1053#endif 1054