1/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32#ifndef __AMDGPU_DRM_H__ 33#define __AMDGPU_DRM_H__ 34 35#include "drm.h" 36 37#if defined(__cplusplus) 38extern "C" { 39#endif 40 41#define DRM_AMDGPU_GEM_CREATE 0x00 42#define DRM_AMDGPU_GEM_MMAP 0x01 43#define DRM_AMDGPU_CTX 0x02 44#define DRM_AMDGPU_BO_LIST 0x03 45#define DRM_AMDGPU_CS 0x04 46#define DRM_AMDGPU_INFO 0x05 47#define DRM_AMDGPU_GEM_METADATA 0x06 48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49#define DRM_AMDGPU_GEM_VA 0x08 50#define DRM_AMDGPU_WAIT_CS 0x09 51#define DRM_AMDGPU_GEM_OP 0x10 52#define DRM_AMDGPU_GEM_USERPTR 0x11 53#define DRM_AMDGPU_WAIT_FENCES 0x12 54#define DRM_AMDGPU_VM 0x13 55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56#define DRM_AMDGPU_SCHED 0x15 57 58#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75/** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linezrized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98#define AMDGPU_GEM_DOMAIN_CPU 0x1 99#define AMDGPU_GEM_DOMAIN_GTT 0x2 100#define AMDGPU_GEM_DOMAIN_VRAM 0x4 101#define AMDGPU_GEM_DOMAIN_GDS 0x8 102#define AMDGPU_GEM_DOMAIN_GWS 0x10 103#define AMDGPU_GEM_DOMAIN_OA 0x20 104#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111/* Flag that CPU access will be required for the case of VRAM domain */ 112#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113/* Flag that CPU access will not work, this VRAM domain is invisible */ 114#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115/* Flag that USWC attributes should be used for GTT */ 116#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117/* Flag that the memory should be in VRAM and cleared */ 118#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119/* Flag that create shadow bo(GTT) while allocating vram bo */ 120#define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 121/* Flag that allocating the BO should use linear VRAM */ 122#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123/* Flag that BO is always valid in this VM */ 124#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125/* Flag that BO sharing will be explicitly synchronized */ 126#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127/* Flag that indicates allocating MQD gart on GFX9, where the mtype 128 * for the second page onward should be set to NC. It should never 129 * be used by user space applications. 130 */ 131#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 132/* Flag that BO may contain sensitive data that must be wiped before 133 * releasing the memory 134 */ 135#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 136/* Flag that BO will be encrypted and that the TMZ bit should be 137 * set in the PTEs when mapping this buffer via GPUVM or 138 * accessing it with various hw blocks 139 */ 140#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 141 142struct drm_amdgpu_gem_create_in { 143 /** the requested memory size */ 144 __u64 bo_size; 145 /** physical start_addr alignment in bytes for some HW requirements */ 146 __u64 alignment; 147 /** the requested memory domains */ 148 __u64 domains; 149 /** allocation flags */ 150 __u64 domain_flags; 151}; 152 153struct drm_amdgpu_gem_create_out { 154 /** returned GEM object handle */ 155 __u32 handle; 156 __u32 _pad; 157}; 158 159union drm_amdgpu_gem_create { 160 struct drm_amdgpu_gem_create_in in; 161 struct drm_amdgpu_gem_create_out out; 162}; 163 164/** Opcode to create new residency list. */ 165#define AMDGPU_BO_LIST_OP_CREATE 0 166/** Opcode to destroy previously created residency list */ 167#define AMDGPU_BO_LIST_OP_DESTROY 1 168/** Opcode to update resource information in the list */ 169#define AMDGPU_BO_LIST_OP_UPDATE 2 170 171struct drm_amdgpu_bo_list_in { 172 /** Type of operation */ 173 __u32 operation; 174 /** Handle of list or 0 if we want to create one */ 175 __u32 list_handle; 176 /** Number of BOs in list */ 177 __u32 bo_number; 178 /** Size of each element describing BO */ 179 __u32 bo_info_size; 180 /** Pointer to array describing BOs */ 181 __u64 bo_info_ptr; 182}; 183 184struct drm_amdgpu_bo_list_entry { 185 /** Handle of BO */ 186 __u32 bo_handle; 187 /** New (if specified) BO priority to be used during migration */ 188 __u32 bo_priority; 189}; 190 191struct drm_amdgpu_bo_list_out { 192 /** Handle of resource list */ 193 __u32 list_handle; 194 __u32 _pad; 195}; 196 197union drm_amdgpu_bo_list { 198 struct drm_amdgpu_bo_list_in in; 199 struct drm_amdgpu_bo_list_out out; 200}; 201 202/* context related */ 203#define AMDGPU_CTX_OP_ALLOC_CTX 1 204#define AMDGPU_CTX_OP_FREE_CTX 2 205#define AMDGPU_CTX_OP_QUERY_STATE 3 206#define AMDGPU_CTX_OP_QUERY_STATE2 4 207 208/* GPU reset status */ 209#define AMDGPU_CTX_NO_RESET 0 210/* this the context caused it */ 211#define AMDGPU_CTX_GUILTY_RESET 1 212/* some other context caused it */ 213#define AMDGPU_CTX_INNOCENT_RESET 2 214/* unknown cause */ 215#define AMDGPU_CTX_UNKNOWN_RESET 3 216 217/* indicate gpu reset occured after ctx created */ 218#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 219/* indicate vram lost occured after ctx created */ 220#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 221/* indicate some job from this context once cause gpu hang */ 222#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 223/* indicate some errors are detected by RAS */ 224#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 225#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 226 227/* Context priority level */ 228#define AMDGPU_CTX_PRIORITY_UNSET -2048 229#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 230#define AMDGPU_CTX_PRIORITY_LOW -512 231#define AMDGPU_CTX_PRIORITY_NORMAL 0 232/* 233 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 234 * CAP_SYS_NICE or DRM_MASTER 235*/ 236#define AMDGPU_CTX_PRIORITY_HIGH 512 237#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 238 239struct drm_amdgpu_ctx_in { 240 /** AMDGPU_CTX_OP_* */ 241 __u32 op; 242 /** For future use, no flags defined so far */ 243 __u32 flags; 244 __u32 ctx_id; 245 /** AMDGPU_CTX_PRIORITY_* */ 246 __s32 priority; 247}; 248 249union drm_amdgpu_ctx_out { 250 struct { 251 __u32 ctx_id; 252 __u32 _pad; 253 } alloc; 254 255 struct { 256 /** For future use, no flags defined so far */ 257 __u64 flags; 258 /** Number of resets caused by this context so far. */ 259 __u32 hangs; 260 /** Reset status since the last call of the ioctl. */ 261 __u32 reset_status; 262 } state; 263}; 264 265union drm_amdgpu_ctx { 266 struct drm_amdgpu_ctx_in in; 267 union drm_amdgpu_ctx_out out; 268}; 269 270/* vm ioctl */ 271#define AMDGPU_VM_OP_RESERVE_VMID 1 272#define AMDGPU_VM_OP_UNRESERVE_VMID 2 273 274struct drm_amdgpu_vm_in { 275 /** AMDGPU_VM_OP_* */ 276 __u32 op; 277 __u32 flags; 278}; 279 280struct drm_amdgpu_vm_out { 281 /** For future use, no flags defined so far */ 282 __u64 flags; 283}; 284 285union drm_amdgpu_vm { 286 struct drm_amdgpu_vm_in in; 287 struct drm_amdgpu_vm_out out; 288}; 289 290/* sched ioctl */ 291#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 292#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 293 294struct drm_amdgpu_sched_in { 295 /* AMDGPU_SCHED_OP_* */ 296 __u32 op; 297 __u32 fd; 298 /** AMDGPU_CTX_PRIORITY_* */ 299 __s32 priority; 300 __u32 ctx_id; 301}; 302 303union drm_amdgpu_sched { 304 struct drm_amdgpu_sched_in in; 305}; 306 307/* 308 * This is not a reliable API and you should expect it to fail for any 309 * number of reasons and have fallback path that do not use userptr to 310 * perform any operation. 311 */ 312#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 313#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 314#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 315#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 316 317struct drm_amdgpu_gem_userptr { 318 __u64 addr; 319 __u64 size; 320 /* AMDGPU_GEM_USERPTR_* */ 321 __u32 flags; 322 /* Resulting GEM handle */ 323 __u32 handle; 324}; 325 326/* SI-CI-VI: */ 327/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 328#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 329#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 330#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 331#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 332#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 333#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 334#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 335#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 336#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 337#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 338#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 339#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 340#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 341#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 342#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 343#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 344 345/* GFX9 and later: */ 346#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 347#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 348#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 349#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 350#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 351#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 352#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 353#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 354#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 355#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 356#define AMDGPU_TILING_SCANOUT_SHIFT 63 357#define AMDGPU_TILING_SCANOUT_MASK 0x1 358 359/* Set/Get helpers for tiling flags. */ 360#define AMDGPU_TILING_SET(field, value) \ 361 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 362#define AMDGPU_TILING_GET(value, field) \ 363 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 364 365#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 366#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 367 368/** The same structure is shared for input/output */ 369struct drm_amdgpu_gem_metadata { 370 /** GEM Object handle */ 371 __u32 handle; 372 /** Do we want get or set metadata */ 373 __u32 op; 374 struct { 375 /** For future use, no flags defined so far */ 376 __u64 flags; 377 /** family specific tiling info */ 378 __u64 tiling_info; 379 __u32 data_size_bytes; 380 __u32 data[64]; 381 } data; 382}; 383 384struct drm_amdgpu_gem_mmap_in { 385 /** the GEM object handle */ 386 __u32 handle; 387 __u32 _pad; 388}; 389 390struct drm_amdgpu_gem_mmap_out { 391 /** mmap offset from the vma offset manager */ 392 __u64 addr_ptr; 393}; 394 395union drm_amdgpu_gem_mmap { 396 struct drm_amdgpu_gem_mmap_in in; 397 struct drm_amdgpu_gem_mmap_out out; 398}; 399 400struct drm_amdgpu_gem_wait_idle_in { 401 /** GEM object handle */ 402 __u32 handle; 403 /** For future use, no flags defined so far */ 404 __u32 flags; 405 /** Absolute timeout to wait */ 406 __u64 timeout; 407}; 408 409struct drm_amdgpu_gem_wait_idle_out { 410 /** BO status: 0 - BO is idle, 1 - BO is busy */ 411 __u32 status; 412 /** Returned current memory domain */ 413 __u32 domain; 414}; 415 416union drm_amdgpu_gem_wait_idle { 417 struct drm_amdgpu_gem_wait_idle_in in; 418 struct drm_amdgpu_gem_wait_idle_out out; 419}; 420 421struct drm_amdgpu_wait_cs_in { 422 /* Command submission handle 423 * handle equals 0 means none to wait for 424 * handle equals ~0ull means wait for the latest sequence number 425 */ 426 __u64 handle; 427 /** Absolute timeout to wait */ 428 __u64 timeout; 429 __u32 ip_type; 430 __u32 ip_instance; 431 __u32 ring; 432 __u32 ctx_id; 433}; 434 435struct drm_amdgpu_wait_cs_out { 436 /** CS status: 0 - CS completed, 1 - CS still busy */ 437 __u64 status; 438}; 439 440union drm_amdgpu_wait_cs { 441 struct drm_amdgpu_wait_cs_in in; 442 struct drm_amdgpu_wait_cs_out out; 443}; 444 445struct drm_amdgpu_fence { 446 __u32 ctx_id; 447 __u32 ip_type; 448 __u32 ip_instance; 449 __u32 ring; 450 __u64 seq_no; 451}; 452 453struct drm_amdgpu_wait_fences_in { 454 /** This points to uint64_t * which points to fences */ 455 __u64 fences; 456 __u32 fence_count; 457 __u32 wait_all; 458 __u64 timeout_ns; 459}; 460 461struct drm_amdgpu_wait_fences_out { 462 __u32 status; 463 __u32 first_signaled; 464}; 465 466union drm_amdgpu_wait_fences { 467 struct drm_amdgpu_wait_fences_in in; 468 struct drm_amdgpu_wait_fences_out out; 469}; 470 471#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 472#define AMDGPU_GEM_OP_SET_PLACEMENT 1 473 474/* Sets or returns a value associated with a buffer. */ 475struct drm_amdgpu_gem_op { 476 /** GEM object handle */ 477 __u32 handle; 478 /** AMDGPU_GEM_OP_* */ 479 __u32 op; 480 /** Input or return value */ 481 __u64 value; 482}; 483 484#define AMDGPU_VA_OP_MAP 1 485#define AMDGPU_VA_OP_UNMAP 2 486#define AMDGPU_VA_OP_CLEAR 3 487#define AMDGPU_VA_OP_REPLACE 4 488 489/* Delay the page table update till the next CS */ 490#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 491 492/* Mapping flags */ 493/* readable mapping */ 494#define AMDGPU_VM_PAGE_READABLE (1 << 1) 495/* writable mapping */ 496#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 497/* executable mapping, new for VI */ 498#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 499/* partially resident texture */ 500#define AMDGPU_VM_PAGE_PRT (1 << 4) 501/* MTYPE flags use bit 5 to 8 */ 502#define AMDGPU_VM_MTYPE_MASK (0xf << 5) 503/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 504#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 505/* Use Non Coherent MTYPE instead of default MTYPE */ 506#define AMDGPU_VM_MTYPE_NC (1 << 5) 507/* Use Write Combine MTYPE instead of default MTYPE */ 508#define AMDGPU_VM_MTYPE_WC (2 << 5) 509/* Use Cache Coherent MTYPE instead of default MTYPE */ 510#define AMDGPU_VM_MTYPE_CC (3 << 5) 511/* Use UnCached MTYPE instead of default MTYPE */ 512#define AMDGPU_VM_MTYPE_UC (4 << 5) 513/* Use Read Write MTYPE instead of default MTYPE */ 514#define AMDGPU_VM_MTYPE_RW (5 << 5) 515 516struct drm_amdgpu_gem_va { 517 /** GEM object handle */ 518 __u32 handle; 519 __u32 _pad; 520 /** AMDGPU_VA_OP_* */ 521 __u32 operation; 522 /** AMDGPU_VM_PAGE_* */ 523 __u32 flags; 524 /** va address to assign . Must be correctly aligned.*/ 525 __u64 va_address; 526 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 527 __u64 offset_in_bo; 528 /** Specify mapping size. Must be correctly aligned. */ 529 __u64 map_size; 530}; 531 532#define AMDGPU_HW_IP_GFX 0 533#define AMDGPU_HW_IP_COMPUTE 1 534#define AMDGPU_HW_IP_DMA 2 535#define AMDGPU_HW_IP_UVD 3 536#define AMDGPU_HW_IP_VCE 4 537#define AMDGPU_HW_IP_UVD_ENC 5 538#define AMDGPU_HW_IP_VCN_DEC 6 539#define AMDGPU_HW_IP_VCN_ENC 7 540#define AMDGPU_HW_IP_VCN_JPEG 8 541#define AMDGPU_HW_IP_NUM 9 542 543#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 544 545#define AMDGPU_CHUNK_ID_IB 0x01 546#define AMDGPU_CHUNK_ID_FENCE 0x02 547#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 548#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 549#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 550#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 551#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 552#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 553#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 554 555struct drm_amdgpu_cs_chunk { 556 __u32 chunk_id; 557 __u32 length_dw; 558 __u64 chunk_data; 559}; 560 561struct drm_amdgpu_cs_in { 562 /** Rendering context id */ 563 __u32 ctx_id; 564 /** Handle of resource list associated with CS */ 565 __u32 bo_list_handle; 566 __u32 num_chunks; 567 __u32 flags; 568 /** this points to __u64 * which point to cs chunks */ 569 __u64 chunks; 570}; 571 572struct drm_amdgpu_cs_out { 573 __u64 handle; 574}; 575 576union drm_amdgpu_cs { 577 struct drm_amdgpu_cs_in in; 578 struct drm_amdgpu_cs_out out; 579}; 580 581/* Specify flags to be used for IB */ 582 583/* This IB should be submitted to CE */ 584#define AMDGPU_IB_FLAG_CE (1<<0) 585 586/* Preamble flag, which means the IB could be dropped if no context switch */ 587#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 588 589/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 590#define AMDGPU_IB_FLAG_PREEMPT (1<<2) 591 592/* The IB fence should do the L2 writeback but not invalidate any shader 593 * caches (L2/vL1/sL1/I$). */ 594#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 595 596/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 597 * This will reset wave ID counters for the IB. 598 */ 599#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 600 601/* Flag the IB as secure (TMZ) 602 */ 603#define AMDGPU_IB_FLAGS_SECURE (1 << 5) 604 605/* Tell KMD to flush and invalidate caches 606 */ 607#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 608 609struct drm_amdgpu_cs_chunk_ib { 610 __u32 _pad; 611 /** AMDGPU_IB_FLAG_* */ 612 __u32 flags; 613 /** Virtual address to begin IB execution */ 614 __u64 va_start; 615 /** Size of submission */ 616 __u32 ib_bytes; 617 /** HW IP to submit to */ 618 __u32 ip_type; 619 /** HW IP index of the same type to submit to */ 620 __u32 ip_instance; 621 /** Ring index to submit to */ 622 __u32 ring; 623}; 624 625struct drm_amdgpu_cs_chunk_dep { 626 __u32 ip_type; 627 __u32 ip_instance; 628 __u32 ring; 629 __u32 ctx_id; 630 __u64 handle; 631}; 632 633struct drm_amdgpu_cs_chunk_fence { 634 __u32 handle; 635 __u32 offset; 636}; 637 638struct drm_amdgpu_cs_chunk_sem { 639 __u32 handle; 640}; 641 642struct drm_amdgpu_cs_chunk_syncobj { 643 __u32 handle; 644 __u32 flags; 645 __u64 point; 646}; 647 648#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 649#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 650#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 651 652union drm_amdgpu_fence_to_handle { 653 struct { 654 struct drm_amdgpu_fence fence; 655 __u32 what; 656 __u32 pad; 657 } in; 658 struct { 659 __u32 handle; 660 } out; 661}; 662 663struct drm_amdgpu_cs_chunk_data { 664 union { 665 struct drm_amdgpu_cs_chunk_ib ib_data; 666 struct drm_amdgpu_cs_chunk_fence fence_data; 667 }; 668}; 669 670/** 671 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 672 * 673 */ 674#define AMDGPU_IDS_FLAGS_FUSION 0x1 675#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 676#define AMDGPU_IDS_FLAGS_TMZ 0x4 677 678/* indicate if acceleration can be working */ 679#define AMDGPU_INFO_ACCEL_WORKING 0x00 680/* get the crtc_id from the mode object id? */ 681#define AMDGPU_INFO_CRTC_FROM_ID 0x01 682/* query hw IP info */ 683#define AMDGPU_INFO_HW_IP_INFO 0x02 684/* query hw IP instance count for the specified type */ 685#define AMDGPU_INFO_HW_IP_COUNT 0x03 686/* timestamp for GL_ARB_timer_query */ 687#define AMDGPU_INFO_TIMESTAMP 0x05 688/* Query the firmware version */ 689#define AMDGPU_INFO_FW_VERSION 0x0e 690 /* Subquery id: Query VCE firmware version */ 691 #define AMDGPU_INFO_FW_VCE 0x1 692 /* Subquery id: Query UVD firmware version */ 693 #define AMDGPU_INFO_FW_UVD 0x2 694 /* Subquery id: Query GMC firmware version */ 695 #define AMDGPU_INFO_FW_GMC 0x03 696 /* Subquery id: Query GFX ME firmware version */ 697 #define AMDGPU_INFO_FW_GFX_ME 0x04 698 /* Subquery id: Query GFX PFP firmware version */ 699 #define AMDGPU_INFO_FW_GFX_PFP 0x05 700 /* Subquery id: Query GFX CE firmware version */ 701 #define AMDGPU_INFO_FW_GFX_CE 0x06 702 /* Subquery id: Query GFX RLC firmware version */ 703 #define AMDGPU_INFO_FW_GFX_RLC 0x07 704 /* Subquery id: Query GFX MEC firmware version */ 705 #define AMDGPU_INFO_FW_GFX_MEC 0x08 706 /* Subquery id: Query SMC firmware version */ 707 #define AMDGPU_INFO_FW_SMC 0x0a 708 /* Subquery id: Query SDMA firmware version */ 709 #define AMDGPU_INFO_FW_SDMA 0x0b 710 /* Subquery id: Query PSP SOS firmware version */ 711 #define AMDGPU_INFO_FW_SOS 0x0c 712 /* Subquery id: Query PSP ASD firmware version */ 713 #define AMDGPU_INFO_FW_ASD 0x0d 714 /* Subquery id: Query VCN firmware version */ 715 #define AMDGPU_INFO_FW_VCN 0x0e 716 /* Subquery id: Query GFX RLC SRLC firmware version */ 717 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 718 /* Subquery id: Query GFX RLC SRLG firmware version */ 719 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 720 /* Subquery id: Query GFX RLC SRLS firmware version */ 721 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 722 /* Subquery id: Query DMCU firmware version */ 723 #define AMDGPU_INFO_FW_DMCU 0x12 724 #define AMDGPU_INFO_FW_TA 0x13 725 /* Subquery id: Query DMCUB firmware version */ 726 #define AMDGPU_INFO_FW_DMCUB 0x14 727 728/* number of bytes moved for TTM migration */ 729#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 730/* the used VRAM size */ 731#define AMDGPU_INFO_VRAM_USAGE 0x10 732/* the used GTT size */ 733#define AMDGPU_INFO_GTT_USAGE 0x11 734/* Information about GDS, etc. resource configuration */ 735#define AMDGPU_INFO_GDS_CONFIG 0x13 736/* Query information about VRAM and GTT domains */ 737#define AMDGPU_INFO_VRAM_GTT 0x14 738/* Query information about register in MMR address space*/ 739#define AMDGPU_INFO_READ_MMR_REG 0x15 740/* Query information about device: rev id, family, etc. */ 741#define AMDGPU_INFO_DEV_INFO 0x16 742/* visible vram usage */ 743#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 744/* number of TTM buffer evictions */ 745#define AMDGPU_INFO_NUM_EVICTIONS 0x18 746/* Query memory about VRAM and GTT domains */ 747#define AMDGPU_INFO_MEMORY 0x19 748/* Query vce clock table */ 749#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 750/* Query vbios related information */ 751#define AMDGPU_INFO_VBIOS 0x1B 752 /* Subquery id: Query vbios size */ 753 #define AMDGPU_INFO_VBIOS_SIZE 0x1 754 /* Subquery id: Query vbios image */ 755 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 756/* Query UVD handles */ 757#define AMDGPU_INFO_NUM_HANDLES 0x1C 758/* Query sensor related information */ 759#define AMDGPU_INFO_SENSOR 0x1D 760 /* Subquery id: Query GPU shader clock */ 761 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 762 /* Subquery id: Query GPU memory clock */ 763 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 764 /* Subquery id: Query GPU temperature */ 765 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 766 /* Subquery id: Query GPU load */ 767 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 768 /* Subquery id: Query average GPU power */ 769 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 770 /* Subquery id: Query northbridge voltage */ 771 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 772 /* Subquery id: Query graphics voltage */ 773 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 774 /* Subquery id: Query GPU stable pstate shader clock */ 775 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 776 /* Subquery id: Query GPU stable pstate memory clock */ 777 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 778/* Number of VRAM page faults on CPU access. */ 779#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 780#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 781/* query ras mask of enabled features*/ 782#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 783 784/* RAS MASK: UMC (VRAM) */ 785#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 786/* RAS MASK: SDMA */ 787#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 788/* RAS MASK: GFX */ 789#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 790/* RAS MASK: MMHUB */ 791#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 792/* RAS MASK: ATHUB */ 793#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 794/* RAS MASK: PCIE */ 795#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 796/* RAS MASK: HDP */ 797#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 798/* RAS MASK: XGMI */ 799#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 800/* RAS MASK: DF */ 801#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 802/* RAS MASK: SMN */ 803#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 804/* RAS MASK: SEM */ 805#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 806/* RAS MASK: MP0 */ 807#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 808/* RAS MASK: MP1 */ 809#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 810/* RAS MASK: FUSE */ 811#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 812 813#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 814#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 815#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 816#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 817 818struct drm_amdgpu_query_fw { 819 /** AMDGPU_INFO_FW_* */ 820 __u32 fw_type; 821 /** 822 * Index of the IP if there are more IPs of 823 * the same type. 824 */ 825 __u32 ip_instance; 826 /** 827 * Index of the engine. Whether this is used depends 828 * on the firmware type. (e.g. MEC, SDMA) 829 */ 830 __u32 index; 831 __u32 _pad; 832}; 833 834/* Input structure for the INFO ioctl */ 835struct drm_amdgpu_info { 836 /* Where the return value will be stored */ 837 __u64 return_pointer; 838 /* The size of the return value. Just like "size" in "snprintf", 839 * it limits how many bytes the kernel can write. */ 840 __u32 return_size; 841 /* The query request id. */ 842 __u32 query; 843 844 union { 845 struct { 846 __u32 id; 847 __u32 _pad; 848 } mode_crtc; 849 850 struct { 851 /** AMDGPU_HW_IP_* */ 852 __u32 type; 853 /** 854 * Index of the IP if there are more IPs of the same 855 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 856 */ 857 __u32 ip_instance; 858 } query_hw_ip; 859 860 struct { 861 __u32 dword_offset; 862 /** number of registers to read */ 863 __u32 count; 864 __u32 instance; 865 /** For future use, no flags defined so far */ 866 __u32 flags; 867 } read_mmr_reg; 868 869 struct drm_amdgpu_query_fw query_fw; 870 871 struct { 872 __u32 type; 873 __u32 offset; 874 } vbios_info; 875 876 struct { 877 __u32 type; 878 } sensor_info; 879 }; 880}; 881 882struct drm_amdgpu_info_gds { 883 /** GDS GFX partition size */ 884 __u32 gds_gfx_partition_size; 885 /** GDS compute partition size */ 886 __u32 compute_partition_size; 887 /** total GDS memory size */ 888 __u32 gds_total_size; 889 /** GWS size per GFX partition */ 890 __u32 gws_per_gfx_partition; 891 /** GSW size per compute partition */ 892 __u32 gws_per_compute_partition; 893 /** OA size per GFX partition */ 894 __u32 oa_per_gfx_partition; 895 /** OA size per compute partition */ 896 __u32 oa_per_compute_partition; 897 __u32 _pad; 898}; 899 900struct drm_amdgpu_info_vram_gtt { 901 __u64 vram_size; 902 __u64 vram_cpu_accessible_size; 903 __u64 gtt_size; 904}; 905 906struct drm_amdgpu_heap_info { 907 /** max. physical memory */ 908 __u64 total_heap_size; 909 910 /** Theoretical max. available memory in the given heap */ 911 __u64 usable_heap_size; 912 913 /** 914 * Number of bytes allocated in the heap. This includes all processes 915 * and private allocations in the kernel. It changes when new buffers 916 * are allocated, freed, and moved. It cannot be larger than 917 * heap_size. 918 */ 919 __u64 heap_usage; 920 921 /** 922 * Theoretical possible max. size of buffer which 923 * could be allocated in the given heap 924 */ 925 __u64 max_allocation; 926}; 927 928struct drm_amdgpu_memory_info { 929 struct drm_amdgpu_heap_info vram; 930 struct drm_amdgpu_heap_info cpu_accessible_vram; 931 struct drm_amdgpu_heap_info gtt; 932}; 933 934struct drm_amdgpu_info_firmware { 935 __u32 ver; 936 __u32 feature; 937}; 938 939#define AMDGPU_VRAM_TYPE_UNKNOWN 0 940#define AMDGPU_VRAM_TYPE_GDDR1 1 941#define AMDGPU_VRAM_TYPE_DDR2 2 942#define AMDGPU_VRAM_TYPE_GDDR3 3 943#define AMDGPU_VRAM_TYPE_GDDR4 4 944#define AMDGPU_VRAM_TYPE_GDDR5 5 945#define AMDGPU_VRAM_TYPE_HBM 6 946#define AMDGPU_VRAM_TYPE_DDR3 7 947#define AMDGPU_VRAM_TYPE_DDR4 8 948#define AMDGPU_VRAM_TYPE_GDDR6 9 949 950struct drm_amdgpu_info_device { 951 /** PCI Device ID */ 952 __u32 device_id; 953 /** Internal chip revision: A0, A1, etc.) */ 954 __u32 chip_rev; 955 __u32 external_rev; 956 /** Revision id in PCI Config space */ 957 __u32 pci_rev; 958 __u32 family; 959 __u32 num_shader_engines; 960 __u32 num_shader_arrays_per_engine; 961 /* in KHz */ 962 __u32 gpu_counter_freq; 963 __u64 max_engine_clock; 964 __u64 max_memory_clock; 965 /* cu information */ 966 __u32 cu_active_number; 967 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 968 __u32 cu_ao_mask; 969 __u32 cu_bitmap[4][4]; 970 /** Render backend pipe mask. One render backend is CB+DB. */ 971 __u32 enabled_rb_pipes_mask; 972 __u32 num_rb_pipes; 973 __u32 num_hw_gfx_contexts; 974 __u32 _pad; 975 __u64 ids_flags; 976 /** Starting virtual address for UMDs. */ 977 __u64 virtual_address_offset; 978 /** The maximum virtual address */ 979 __u64 virtual_address_max; 980 /** Required alignment of virtual addresses. */ 981 __u32 virtual_address_alignment; 982 /** Page table entry - fragment size */ 983 __u32 pte_fragment_size; 984 __u32 gart_page_size; 985 /** constant engine ram size*/ 986 __u32 ce_ram_size; 987 /** video memory type info*/ 988 __u32 vram_type; 989 /** video memory bit width*/ 990 __u32 vram_bit_width; 991 /* vce harvesting instance */ 992 __u32 vce_harvest_config; 993 /* gfx double offchip LDS buffers */ 994 __u32 gc_double_offchip_lds_buf; 995 /* NGG Primitive Buffer */ 996 __u64 prim_buf_gpu_addr; 997 /* NGG Position Buffer */ 998 __u64 pos_buf_gpu_addr; 999 /* NGG Control Sideband */ 1000 __u64 cntl_sb_buf_gpu_addr; 1001 /* NGG Parameter Cache */ 1002 __u64 param_buf_gpu_addr; 1003 __u32 prim_buf_size; 1004 __u32 pos_buf_size; 1005 __u32 cntl_sb_buf_size; 1006 __u32 param_buf_size; 1007 /* wavefront size*/ 1008 __u32 wave_front_size; 1009 /* shader visible vgprs*/ 1010 __u32 num_shader_visible_vgprs; 1011 /* CU per shader array*/ 1012 __u32 num_cu_per_sh; 1013 /* number of tcc blocks*/ 1014 __u32 num_tcc_blocks; 1015 /* gs vgt table depth*/ 1016 __u32 gs_vgt_table_depth; 1017 /* gs primitive buffer depth*/ 1018 __u32 gs_prim_buffer_depth; 1019 /* max gs wavefront per vgt*/ 1020 __u32 max_gs_waves_per_vgt; 1021 __u32 _pad1; 1022 /* always on cu bitmap */ 1023 __u32 cu_ao_bitmap[4][4]; 1024 /** Starting high virtual address for UMDs. */ 1025 __u64 high_va_offset; 1026 /** The maximum high virtual address */ 1027 __u64 high_va_max; 1028 /* gfx10 pa_sc_tile_steering_override */ 1029 __u32 pa_sc_tile_steering_override; 1030 /* disabled TCCs */ 1031 __u64 tcc_disabled_mask; 1032}; 1033 1034struct drm_amdgpu_info_hw_ip { 1035 /** Version of h/w IP */ 1036 __u32 hw_ip_version_major; 1037 __u32 hw_ip_version_minor; 1038 /** Capabilities */ 1039 __u64 capabilities_flags; 1040 /** command buffer address start alignment*/ 1041 __u32 ib_start_alignment; 1042 /** command buffer size alignment*/ 1043 __u32 ib_size_alignment; 1044 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1045 __u32 available_rings; 1046 __u32 _pad; 1047}; 1048 1049struct drm_amdgpu_info_num_handles { 1050 /** Max handles as supported by firmware for UVD */ 1051 __u32 uvd_max_handles; 1052 /** Handles currently in use for UVD */ 1053 __u32 uvd_used_handles; 1054}; 1055 1056#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1057 1058struct drm_amdgpu_info_vce_clock_table_entry { 1059 /** System clock */ 1060 __u32 sclk; 1061 /** Memory clock */ 1062 __u32 mclk; 1063 /** VCE clock */ 1064 __u32 eclk; 1065 __u32 pad; 1066}; 1067 1068struct drm_amdgpu_info_vce_clock_table { 1069 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1070 __u32 num_valid_entries; 1071 __u32 pad; 1072}; 1073 1074/* 1075 * Supported GPU families 1076 */ 1077#define AMDGPU_FAMILY_UNKNOWN 0 1078#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1079#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1080#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1081#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1082#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1083#define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1084#define AMDGPU_FAMILY_RV 142 /* Raven */ 1085#define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1086 1087#if defined(__cplusplus) 1088} 1089#endif 1090 1091#endif 1092