18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Definitions for CS4271 ASoC codec driver 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef __CS4271_H 98c2ecf20Sopenharmony_ci#define __CS4271_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_cistruct cs4271_platform_data { 128c2ecf20Sopenharmony_ci int gpio_nreset; /* GPIO driving Reset pin, if any */ 138c2ecf20Sopenharmony_ci bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci /* 168c2ecf20Sopenharmony_ci * The CS4271 requires its LRCLK and MCLK to be stable before its RESET 178c2ecf20Sopenharmony_ci * line is de-asserted. That also means that clocks cannot be changed 188c2ecf20Sopenharmony_ci * without putting the chip back into hardware reset, which also requires 198c2ecf20Sopenharmony_ci * a complete re-initialization of all registers. 208c2ecf20Sopenharmony_ci * 218c2ecf20Sopenharmony_ci * One (undocumented) workaround is to assert and de-assert the PDN bit 228c2ecf20Sopenharmony_ci * in the MODE2 register. This workaround can be enabled with the 238c2ecf20Sopenharmony_ci * following flag. 248c2ecf20Sopenharmony_ci * 258c2ecf20Sopenharmony_ci * Note that this is not needed in case the clocks are stable 268c2ecf20Sopenharmony_ci * throughout the entire runtime of the codec. 278c2ecf20Sopenharmony_ci */ 288c2ecf20Sopenharmony_ci bool enable_soft_reset; 298c2ecf20Sopenharmony_ci}; 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci#endif /* __CS4271_H */ 32